Stacked field effect transistor with shielded output

Abstract

The present invention relates to a stacked field effect transistor with shielded output, and provides a structure including a stacked field effect transistor and a method of forming a structure including a stacked field effect transistor. The structure includes a field effect transistor having a first active gate, a second active gate, and a drain region disposed in a horizontal direction between the first and second active gates. The structure also includes a back end of line (BEOL) stack having a first metal level and a second metal level above the field effect transistor. The first metal level includes a first interconnect, a second interconnect, and a third interconnect, and the second metal level includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is disposed in a vertical direction between the fourth interconnect and the drain region, and the third interconnect is disposed in the horizontal direction between the first and second interconnects.

Description

Technical Field

[0001] This disclosure relates to the manufacture of semiconductor devices and integrated circuits, and more particularly to structures including stacked field-effect transistors and methods for forming structures including stacked field-effect transistors. Background Technology

[0002] Stackable field-effect transistors (FETs) can distribute voltage stress among different transistors. Stacking allows for the use of larger supply voltages, thus providing greater output power to the load without increasing current. Stacked FETs can also be interconnected for use in cascode. Unacceptably high reverse coupling and return losses can occur in stacked FETs formed using a single active region. Furthermore, for specific applications, the maximum stable gain may be lower than expected.

[0003] The improvements needed include the structure of stacked field-effect transistors and the methods for forming structures including stacked field-effect transistors. Summary of the Invention

[0004] In one embodiment of the present invention, a structure includes a field-effect transistor (FET) having a first active gate, a second active gate, and a drain region disposed horizontally between the first and second active gates. The structure also includes a back-end process stack having a first metal layer and a second metal layer located above the FET. The first metal layer includes a first interconnect, a second interconnect, and a third interconnect, and the second metal layer includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is disposed vertically between the fourth interconnect and the drain region, and the third interconnect is disposed horizontally between the first interconnect and the second interconnect.

[0005] In one embodiment of the present invention, a method includes forming a field-effect transistor (FET) including a first active gate, a second active gate, and a drain region, and forming a back-end process stack including a first metal layer and a second metal layer located above the FET. The drain region is disposed horizontally between the first active gate and the second active gate. The first metal layer includes a first interconnect, a second interconnect, and a third interconnect, and the second metal layer includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is disposed vertically between the fourth interconnect and the drain region, and the third interconnect is disposed horizontally between the first interconnect and the second interconnect. Attached Figure Description

[0006] The accompanying drawings, which are included and constitute a part of this specification, illustrate various embodiments of the invention and, together with the foregoing general description of the invention and the following detailed description of these embodiments, serve to explain these embodiments of the invention. In these drawings, similar reference numerals denote similar features in different views.

[0007] Figure 1 A top view showing the structure according to an embodiment of the present invention.

[0008] Figure 2 Showing the general outline Figure 1 The sectional view made by line 2-2 in the diagram.

[0009] Figure 3 Display in Figure 1 A top view of the structure during the subsequent manufacturing phase.

[0010] Figure 4 Showing the general outline Figure 3 The sectional view made along line 4-4 in the diagram.

[0011] Figure 5 Display in Figure 3 A top view of the structure during the subsequent manufacturing phase.

[0012] Figure 6 Showing the general outline Figure 5 The sectional view made along line 6-6 in the diagram.

[0013] Figure 7 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0014] Figure 8 A cross-sectional view showing a structure according to an alternative embodiment of the present invention.

[0015] Figure 9 A cross-sectional view showing a structure according to an alternative embodiment of the present invention. Detailed Implementation

[0016] Please refer to Figure 1 , 2 According to an embodiment of the present invention, a structure 10 is formed using a silicon-on-insulator (SOI) substrate. The SOI substrate includes a device layer 12, a buried oxide (BOX) layer 14 composed of silicon dioxide, and an operating substrate 16. The device layer 12 is separated from the operating substrate 16 by the intermediate buried oxide layer 14 and may be much thinner than the operating substrate 16. The device layer 12 is electrically isolated from the operating substrate 16 by the buried oxide layer 14. The device layer 12 and the operating substrate 16 may be composed of a semiconductor material, such as single-crystal silicon.

[0017] A trench isolation region 18 is formed in device layer 12. In one embodiment, the trench isolation region 18 can extend completely through device layer 12 to reach buried oxide layer 14. The trench isolation region 18 surrounds a single active region comprised of a portion of the semiconductor material of device layer 12. The trench isolation region 18 can be formed using a shallow trench isolation technique, which utilizes photolithography and etching processes to pattern trenches in device layer 12, deposit dielectric material to overfill the trenches, and planarize the dielectric material using chemical mechanical polishing and / or etch-back to remove excess dielectric material from the site. The dielectric material can consist of an electrically insulating material such as silicon dioxide deposited by chemical vapor deposition.

[0018] A field-effect transistor 20 can be fabricated using front-end processing techniques as a device located in the active region of device layer 12. The field-effect transistor 20 may include active gates 22 and 23 disposed on device layer 12, and source regions 24 and drain regions 26 formed in device layer 12. The active gates 22 and 23 may be arranged along the vertical axis 15. The source regions 24 and drain regions 26 may be formed by ion implantation of p-type or n-type dopants. A channel region is disposed in device layer 12 below each active gate 22 and 23 and laterally located between each source region 24 and drain region 26. The active gates 22 and 23 may be formed, for example, by patterning a heavily doped polysilicon deposition layer using photolithography and etching processes. Although not shown, the active gates 22 and 23 may define gate fingers that are connected at one end to provide a connected or integral gate structure for the field-effect transistor 20. The field-effect transistor 20 may include other elements, such as a gate dielectric 21 disposed between the active gates 22, 23 and the device layer 12, an annular region and a lightly doped drain extension region located in the device layer 12, and sidewalls located on the active gates 22, 23. Each active gate 22, 23 is disposed horizontally between the drain region 26 and one of the source regions 24. In one embodiment, the active gates 22, 23 may be arranged symmetrically with respect to the drain region 26 along the horizontal direction.

[0019] Please refer to Figure 3 , 4 In which similar reference numerals indicate Figure 1 , 2Similar features are found in the next manufacturing stage of this process, where a local interconnect structure or contact layer is formed above the field-effect transistor 20 via an intermediate process. This local interconnect structure includes a dielectric layer 30, and source contacts 34 and drain contacts 36 disposed within the dielectric layer 30. The dielectric layer 30 may be composed of an insulating material such as silicon dioxide, and the source contacts 34 and drain contacts 36 may include tungsten, metal silicides, etc. The source contacts 34 penetrate the dielectric layer 30 to land at a series of locations on each source region 24. Similarly, the drain contacts 36 penetrate the dielectric layer 30 to land at a series of locations on the drain region 26.

[0020] A dielectric layer 37 and interconnects 38, 40, 42, and 44 are formed above the contact layer as metal layers (e.g., a first metal (M1) layer) of the back-end process interconnect structure. This metal layer, including the dielectric layer 37 and interconnects 38, 40, 42, and 44, represents the metal layer closest to the field-effect transistor 20 among multiple metal layers of the back-end process interconnect structure. The dielectric layer 37 may be composed of an insulating material such as silicon dioxide, which can be deposited, for example, by chemical vapor deposition. This metal layer, including the dielectric layer 37 and interconnects 38, 40, 42, and 44, can be formed by deposition, polishing, photolithography, and etching techniques with damascene process characteristics. Specifically, the dielectric layer 37 can be deposited and patterned using photolithography and etching processes to define trenches filled with planarizing metal (e.g., copper) to define the interconnects 38, 40, 42, and 44.

[0021] Interconnects 38, 40, 42, and 44 may extend parallel to the active gates 22 and 23 along their length. Interconnect 40 is laterally disposed in the horizontal direction between interconnects 42 and 44. Interconnects 42 and 44 may be equidistant from interconnect 40, and are therefore symmetrically disposed in the horizontal direction with respect to interconnect 40. Interconnect 38 is connected to the source region 24 via source contact 34, and interconnect 40 is connected to the drain region 26 via drain contact 36. Interconnects 42 and 44 are not connected to any part of the field-effect transistor 20 or any part of the single active region surrounded by the trench isolation region 18 via contacts. In one embodiment, interconnect 40 may be symmetrically arranged in the horizontal direction between interconnects 42 and 44, such that the lateral spacing between interconnects 40 and 42 is equal to the lateral spacing between interconnects 40 and 44. In one embodiment, interconnect 40 may be symmetrically arranged in the horizontal direction between active gates 22 and 23. The interconnect 40 is connected to the load 54.

[0022] Please refer to Figure 5 , 6 In which similar reference numerals indicate Figure 3 , 4Similar features are present in the next manufacturing stage of this process, where a dielectric layer 45, interconnects 46, and vias 48 and 50 are formed above the dielectric layer 37 as the metal level (e.g., a second metal (M2) level) of the back-end process interconnect structure. In this representative embodiment, the metal level including the dielectric layer 45 and interconnects 46 is directly adjacent to the metal levels including the dielectric layer 37 and interconnects 38, 40, 42, and 44, and the metal level including the dielectric layer 45 and interconnects 46 is separated from the field-effect transistor 20 by the metal levels including the dielectric layer 37 and interconnects 38, 40, 42, and 44. The dielectric layer 45 may be composed of a dielectric material such as silicon dioxide, which may be deposited by, for example, chemical vapor deposition. The metal levels including the dielectric layer 45, interconnects 46, and vias 48 and 50 may be formed by deposition, polishing, photolithography, and etching techniques with damascene process features. Specifically, a dielectric layer 45 can be deposited and patterned using photolithography and etching processes to define trenches and via openings, which are filled with planarized metal (e.g., copper) to define interconnects 46 and vias 48 and 50.

[0023] Interconnect 46 extends longitudinally parallel to the active gates 22 and 23 and longitudinally parallel to interconnects 38, 40, 42, and 44 in the underlying metal layer. Interconnect 46 is connected to interconnect 42 via via 48 and to interconnect 44 via via 50. Interconnect 46 has a side 49 and an opposite side 51. Interconnect 46 overlaps with interconnect 42 at side 49 and with interconnect 44 at side 51. Via 48 is disposed adjacent to side 49 and side 51 in a horizontal direction. Interconnect 46 spans over interconnect 40, drain contact 36, and drain region 26. In one embodiment, interconnect 46 may be centered above interconnect 40. Interconnect 40 and drain contact 36 are disposed vertically between interconnect 46 and drain region 26.

[0024] Interconnect 40 is fully enclosed on multiple (e.g., three) sides via interconnects 42, 44, interconnect 46, and vias 48, 50. Interconnects 42, 44, 46, and vias 48, 50 (which are electrically floating) define a metal shell as a metal shield between the active gates 22, 23 and interconnect 40. This metal shell is not aligned with respect to either active gate 22, 23. This metal shield may be electrically grounded to reduce reverse coupling and return loss, and to improve maximum stable gain.

[0025] In an alternative embodiment, interconnect 46 may be formed on a higher metal level of the back-end process stack, such as a third metal (M3) level, which is not directly adjacent to the metal level including dielectric layer 37 and interconnects 38, 40, 42, 44.

[0026] During operation, driver 52 provides radio frequency (RF) signals as input to the active gates 22, 23 of field-effect transistor 20. Source region 24 is grounded via interconnect 38. Interconnect 40 receives switched RF signals and outputs these signals from the stacked field-effect transistor 20 to load 54. The metal shield defined by interconnects 42, 44, interconnect 46, and vias 48, 50 provides electrical isolation between the active gates 22, 23 and the interconnect 40 located at the output of the field-effect transistor 20.

[0027] Please refer to Figure 7 According to an alternative embodiment, structure 10 may further include dummy gates 60, 62 arranged laterally between active gate 22 and active gate 23. The spacing of vias 48, 50 and interconnects 42, 44 may be widened to accommodate the introduction of dummy gates 60, 62. Dummy gates 60, 62 may be arranged parallel to the longitudinal direction of active gate 22. Dummy gate 60 is disposed horizontally between interconnects 42 and 40, and dummy gate 62 is disposed horizontally between interconnects 44 and 40. Dummy gates 60, 62 are not connected to interconnects in the metal layer including interconnects 40, 42, 44, and interconnects 42, 44 may be misaligned relative to dummy gates 60, 62. Dummy gates 60, 62 may be biased to AC ground during operation, but are not active features associated with the field-effect transistor 20 or its operation. In this regard, dummy gates 60, 62 may be connected to power supply 58, which is configured to provide a DC bias voltage to dummy gates 60, 62, thereby ensuring that dummy gates 60, 62 do not interfere with the operation of field-effect transistor 20.

[0028] Please refer to Figure 8 In which similar reference numerals indicate Figure 7 Similar features are present in the embodiment, and according to an alternative embodiment, interconnects 42, 44 may be aligned relative to dummy gates 60, 62 and connected to dummy gates 60, 62 via contact 64 in an over-active gate contact scheme. In particular, interconnect 42 may overlap with dummy gate 60 to facilitate connection with dummy gate 60, and interconnect 44 may overlap with dummy gate 62 to facilitate connection with dummy gate 62.

[0029] Please refer to Figure 9 In which similar reference numerals indicate Figure 8Similar features are present, and according to alternative embodiments, an additional metal layer may be provided between the field-effect transistor 20 and the metal layer including interconnects 40, 42, and 44. An additional interconnect 66 may be formed in the dielectric layer 70 and connected to the dummy gates 60 and 62 via contacts 64. The interconnect 66 may be connected to the interconnects 40, 42, and 44 via vias 68, respectively. The interconnect 66 connected to the interconnects 42 and 44 may participate in forming a metal shell surrounding the interconnect 40 to define a metal shield.

[0030] The method described above is used for the manufacture of integrated circuit chips. Manufacturers can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product. The final product can be any product including the integrated circuit chip, such as a computer product with a central processing unit or a smartphone.

[0031] The terms used herein, modified by approximate language such as “approximately,” “roughly,” and “substantially,” are not limited to the specified precise values. This approximate language may correspond to the accuracy of the instrument used to measure the value, and may represent + / - 10% of the value unless otherwise dependent on the accuracy of that instrument.

[0032] The terms "vertical" and "horizontal" are used in this document as examples to establish a reference framework and are not intended to be limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the layers defined above. The term "lateral" refers to a direction within this horizontal plane.

[0033] A feature "connected" or "coupled" to another feature may be directly connected or coupled to that other feature, or one or more intermediate features may exist. If no intermediate features exist, the feature may be "directly connected" or "directly coupled" to the other feature. If at least one intermediate feature exists, the feature may be "indirectly connected" or "indirectly coupled" to the other feature. A feature "on" or "in contact" with another feature may be directly on or in contact with that other feature, or one or more intermediate features may exist. If no intermediate features exist, the feature may be directly "on" or in contact with that other feature. If at least one intermediate feature exists, the feature may not be "directly" on or in contact with that other feature. If one feature extends over and covers a portion of another feature, the different features may "overlap".

[0034] The descriptions of various embodiments of the invention are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements upon technical techniques known in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising stacked field-effect transistors, characterized in that, include: A field-effect transistor includes a first active gate, a second active gate, and a drain region, wherein the drain region is disposed horizontally between the first active gate and the second active gate; as well as The back-end process stack includes a first metal layer and a second metal layer located above the field-effect transistor. The second metal layer is disposed on the first metal layer. The first metal layer includes a first interconnect, a second interconnect, a third interconnect, and other interconnects. The second metal layer includes a fourth interconnect, a first via, and a second via. The first interconnect, the second interconnect, and the third interconnect are disposed horizontally between the other interconnects. The third interconnect is connected to the drain region through a drain contact. The fourth interconnect is directly connected to the first interconnect and the second interconnect through the first via and the second via, respectively. The third interconnect is disposed vertically between the fourth interconnect and the drain region. The third interconnect is disposed horizontally between the first interconnect and the second interconnect, and the third interconnect is completely closed on multiple sides through the first interconnect, the second interconnect, the fourth interconnect, the first via, and the second via.

2. The structure as described in claim 1, characterized in that, Compared to the second metal layer, the first metal layer is closer to the field-effect transistor.

3. The structure as described in claim 1, characterized in that, The fourth interconnect includes a first side and a second side opposite to the first side, the first via being disposed adjacent to the first side along the horizontal direction, and the second via being adjacent to the second side along the horizontal direction.

4. The structure as described in claim 1, characterized in that, The fourth interconnect includes a first side and a second side opposite to the first side, the fourth interconnect overlapping the first interconnect on the first side and the fourth interconnect overlapping the second interconnect on the second side.

5. The structure as described in claim 1, characterized in that, Also includes: First pseudo-gate; as well as Second pseudo-gate, The first dummy gate is disposed along the horizontal direction between the first active gate and the drain region, and the second dummy gate is disposed along the horizontal direction between the second active gate and the drain region.

6. The structure as described in claim 5, characterized in that, Also includes: A contact layer is vertically disposed between the first metal layer and the field-effect transistor. The contact layer includes a first contact that directly connects the first interconnect to the first dummy gate, and a second contact that directly connects the second interconnect to the second dummy gate.

7. The structure as described in claim 6, characterized in that, The first interconnect overlaps with the first dummy gate, and the second interconnect overlaps with the second dummy gate.

8. The structure as described in claim 5, characterized in that, The first interconnect is disposed along the horizontal direction between the first active gate and the first dummy gate, and the second interconnect is disposed along the horizontal direction between the second active gate and the second dummy gate.

9. The structure as described in claim 5, characterized in that, Also includes: A power supply, connected to the first dummy gate and the second dummy gate, is configured to provide a DC bias voltage to the first dummy gate and the second dummy gate.

10. The structure as described in claim 1, characterized in that, The field-effect transistor includes a single active region made of semiconductor material, a first source region located in the single active region, and a second source region located in the single active region. The drain region is located in the single active region. The first active gate is laterally disposed between the first source region and the drain region, and the second active gate is disposed along the horizontal direction between the second source region and the drain region.

11. The structure as described in claim 1, characterized in that, The third interconnect is arranged symmetrically along the horizontal direction between the first interconnect and the second interconnect.

12. The structure as described in claim 1, characterized in that, The first active gate and the second active gate are symmetrically arranged relative to the drain region along the horizontal direction.

13. A method for forming a structure including stacked field-effect transistors, characterized in that, include: A field-effect transistor is formed, the field-effect transistor including a first active gate, a second active gate, and a drain region, wherein the drain region is disposed horizontally between the first active gate and the second active gate; and A back-end process stack is formed, which includes a first metal layer and a second metal layer located above the field-effect transistor. The second metal layer is disposed on the first metal layer. The first metal layer includes a first interconnect, a second interconnect, a third interconnect, and other interconnects. The second metal layer includes a fourth interconnect, a first via, and a second via. The first interconnect, the second interconnect, and the third interconnect are disposed horizontally between the other interconnects. The third interconnect is connected to the drain region through a drain contact. The fourth interconnect is directly connected to the first interconnect and the second interconnect through the first via and the second via, respectively. The third interconnect is disposed vertically between the fourth interconnect and the drain region. The third interconnect is disposed horizontally between the first interconnect and the second interconnect, and the third interconnect is completely closed on multiple sides through the first interconnect, the second interconnect, the fourth interconnect, the first via, and the second via.

14. The method as described in claim 13, characterized in that, The fourth interconnect includes a first side and a second side opposite to the first side, the fourth interconnect overlapping the first interconnect on the first side and the fourth interconnect overlapping the second interconnect on the second side.

15. The method as described in claim 13, characterized in that, Also includes: Forming a first pseudo-gate and a second pseudo-gate, The first dummy gate is disposed along the horizontal direction between the first active gate and the drain region, and the second dummy gate is disposed along the horizontal direction between the second active gate and the drain region.

16. The method as described in claim 15, characterized in that, Also includes: A contact layer is formed vertically between the first metal layer and the field-effect transistor. The contact layer includes a first contact that directly connects the first interconnect to the first dummy gate, and a second contact that directly connects the second interconnect to the second dummy gate.

17. The method as described in claim 13, characterized in that, The field-effect transistor includes a single active region made of semiconductor material, a first source region located in the single active region, and a second source region located in the single active region. The drain region is located in the single active region. The first active gate is laterally disposed between the first source region and the drain region, and the second active gate is disposed along the horizontal direction between the second source region and the drain region.

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