Charge pump circuit for load switch

Abstract

The application discloses a charge pump circuit for load switch, which is used for converting input voltage into gate drive voltage of load switch, comprising: a boost module with a first input end for receiving a first voltage, a second input end for receiving a second voltage, a third input end for receiving a reference voltage, and an output end for outputting the gate drive voltage after boosting; a first drive module and a second drive module, which respectively convert the input voltage into the first voltage and the second voltage according to a clock signal; and a first auxiliary module and a second auxiliary module, which are used for providing an auxiliary channel for converting the input voltage into the first voltage and the second voltage when the input voltage is low, so that the whole circuit is no longer limited by threshold voltage of a transistor and can work normally when the input voltage is very low, and the efficiency of the circuit is improved.

Description

Technical Field

[0001] This invention relates to the field of electrical control technology, and in particular to a charge pump circuit for load switching. Background Technology

[0002] Load switches are widely used in various power management systems and are an important component of power supply and system monitoring products, providing protection for both the power supply and the load. Because the electron carrier mobility is greater than the hole carrier mobility (approximately 2.6:1), existing load switches typically use NMOS transistors, which effectively reduces chip area and saves costs. To ensure that the input voltage Vin of the load switch is fully transferred to the output, a charge pump circuit is needed to boost the gate voltage of the load switch above Vin. Normally, during normal operation, the gate-source voltage needs to be controlled at around 5V. This not only effectively improves conduction efficiency but also reduces the on-resistance of the power transistor, while allowing it to operate within a safer operating range.

[0003] However, existing charge pump circuits are susceptible to the threshold voltage of transistors. When the input voltage Vin is low, the circuit cannot start properly and its efficiency is low. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a charge pump circuit for load switching, which solves the problem that existing charge pump circuits cannot work properly when the input voltage is low, thereby improving circuit efficiency.

[0005] According to an embodiment of the present invention, a charge pump circuit for a load switch is provided, the charge pump circuit being used to convert an input voltage into a gate drive voltage of the load switch, wherein the charge pump circuit includes: a boost module having a first input terminal for receiving a first voltage, a second input terminal for receiving a second voltage, a third input terminal for receiving a reference voltage, and an output terminal for outputting a boosted gate drive voltage; a first drive module coupled to the boost module, for providing the first voltage to the first input terminal according to a first clock signal and the input voltage; and a second drive module coupled to the boost module, for providing the second voltage to the second input terminal according to a second clock signal and the input voltage; wherein the charge pump circuit further includes: a first auxiliary module coupled to the first drive module and the boost module, for providing a first auxiliary channel for converting the input voltage into the first voltage when the input voltage is low; and a second auxiliary module coupled to the second drive module and the boost module, for providing a second auxiliary channel for converting the input voltage into the second voltage when the input voltage is low.

[0006] Optionally, the first auxiliary module and the second auxiliary module are further configured to pump the bias voltage to the boost module.

[0007] Optionally, the boost module includes: a first pumping capacitor, a second pumping capacitor, and first to fourth transistors, wherein a first end of the first pumping capacitor is coupled to the first input terminal, and a second end is coupled to a first intermediate node; a first end of the second pumping capacitor is coupled to the second input terminal, and a second end is coupled to a second intermediate node; the sources of the first and second transistors are coupled to the third input terminal; the sources of the third and fourth transistors are coupled to the output terminal; the drains of the first and third transistors and the gates of the second and fourth transistors are coupled to the first intermediate node; and the drains of the second and fourth transistors and the gates of the first and third transistors are coupled to the second intermediate node.

[0008] Optionally, the first driving module includes: first and second inverters, the power supply terminals of the first and second inverters being used to receive the bias voltage, the input terminal of the first inverter being used to receive the first clock signal, the output terminal of the first inverter being coupled to the input terminal of the second inverter, and a fifth and a sixth transistor, the source of the fifth transistor being coupled to the input voltage, the drain being coupled to the drain of the sixth transistor, the source of the sixth transistor being coupled to ground, and the gates of the fifth and sixth transistors being coupled to the output terminal of the second inverter, wherein the common terminal of the drains of the fifth and sixth transistors serves as the output terminal of the first voltage.

[0009] Optionally, the first auxiliary module includes: a first auxiliary transistor, the drain of which is coupled to the input voltage, the gate of which is coupled to the output terminal of the first inverter, and the source of which is coupled to the common terminal of the drains of the fifth and sixth transistors; and a first auxiliary capacitor, the first end of which is coupled to the output terminal of the first inverter, and the second end of which is coupled to the first intermediate node.

[0010] Optionally, the first auxiliary transistor and the fifth transistor are complementary in conduction.

[0011] Optionally, the second driving module includes: a third and a fourth inverter, the power supply terminals of the third and fourth inverters being used to receive the bias voltage, the input terminal of the third inverter being used to receive the second clock signal, the output terminal of the third inverter being coupled to the input terminal of the fourth inverter, and a seventh and an eighth transistor, the source of the seventh transistor being coupled to the input voltage, the drain being coupled to the drain of the eighth transistor, the source of the eighth transistor being coupled to ground, and the gates of the seventh and eighth transistors being coupled to the output terminal of the fourth inverter, wherein the common terminal of the drains of the seventh and eighth transistors serves as the output terminal of the second voltage.

[0012] Optionally, the second auxiliary module includes: a second auxiliary transistor, the drain of which is coupled to the input voltage, the gate of which is coupled to the output terminal of the third inverter, and the source of which is coupled to the common terminal of the drains of the seventh and eighth transistors; and a second auxiliary capacitor, the first terminal of which is coupled to the output terminal of the third inverter, and the second terminal of which is coupled to the second intermediate node.

[0013] Optionally, the second auxiliary transistor and the seventh transistor are complementary in conduction.

[0014] Optionally, the first clock signal and the second clock signal are differential clock signals.

[0015] The charge pump circuit for load switching in this invention has the following advantages: The auxiliary module provides an auxiliary channel to convert the input voltage into the voltage at the input terminal of the boost module when the input voltage is low. This effectively transfers the input voltage to the boost module when the low input voltage prevents the transistors in the drive module from conducting properly. Furthermore, the auxiliary module pumps a bias voltage to the intermediate node of the boost module, raising the potential of the intermediate node and ensuring that the P-type field-effect transistors in the boost module can also conduct normally. The entire circuit is no longer limited by the threshold voltage of the transistors and can operate normally even when the input voltage is very low, thus improving circuit efficiency. Attached Figure Description

[0016] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic circuit diagram of a charge pump circuit for a load switch in the prior art is shown.

[0018] Figure 2 A schematic circuit diagram of another prior art charge pump circuit for load switching is shown;

[0019] Figure 3 A schematic circuit diagram of a charge pump circuit for a load switch according to an embodiment of the present invention is shown. Detailed Implementation

[0020] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0021] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "coupled" to another element or "coupled" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0022] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0023] Figure 1 A schematic circuit diagram of a prior art charge pump circuit for a load switch is shown. Figure 1 As shown, the charge pump circuit 100 includes a boost module 110, a first drive module 120, and a second drive module 130. The boost module 110 includes a first input terminal 101 for receiving a first voltage V1, a second input terminal 102 for receiving a second voltage V2, a third input terminal 103 for receiving a reference voltage Vref, and an output terminal 104 for outputting the boosted gate drive voltage Vgate. The first drive module 120 is coupled to the boost module 110 and provides the first voltage V1 to the first input terminal 101 according to a first clock signal CLK and an input voltage Vin. The second drive module 130 is coupled to the boost module 110 and provides the second voltage V2 to the second input terminal 102 according to a second clock signal CLKB and an input voltage Vin. The first clock signal CLK and the second clock signal CLKB are differential clock signals, and the reference voltage Vref is a 5V voltage generated internally by the circuit.

[0024] Specifically, the boost module 110 includes pump capacitor C1, pump capacitor C2, and transistors T1-T4. The first end of pump capacitor C1 is coupled to the first input terminal 101 to receive the first voltage V1, and the second end is coupled to the intermediate node 1a inside the boost module 110. The first end of pump capacitor C2 is coupled to the second input terminal 102 to receive the second voltage V2, and the second end is coupled to the intermediate node 1b inside the boost module 110. Transistors T1-T4 adopt a differential cross-coupled architecture. Transistors T1 and T2 are N-type field-effect transistors, and transistors T3 and T4 are P-type field-effect transistors. The sources of transistors T1 and T2 are coupled to the third input terminal 103 to receive the reference voltage Vref. The drains of transistors T1 and T3, and the gates of transistors T2 and T4 are coupled to the intermediate node 1a. The drains of transistors T2 and T4, and the gates of transistors T1 and T3 are coupled to the intermediate node 1b. The sources of transistors T3 and T4 are coupled to the output terminal 104.

[0025] The first driving module 120 includes inverters INV1 and INV2, and transistors T5 and T6. The power supply terminals of inverters INV1 and INV2 are coupled to a bias voltage Vbias. The input terminal of inverter INV1 receives a first clock signal CLK, and its output terminal is coupled to the input terminal of inverter INV2. The source of transistor T5 is coupled to the input voltage Vin, its drain is coupled to the drain of transistor T6, the source of transistor T6 is coupled to ground, and the gates of transistors T5 and T6 are coupled to the output terminal of inverter INV2. The common terminal of the drains of transistors T5 and T6 is used to output the first voltage V1.

[0026] Similarly, the second drive module 130 includes inverters INV3 and INV4, and transistors T7 and T8. The power supply terminals of inverters INV3 and INV4 are coupled to a bias voltage Vbias. The input terminal of inverter INV3 receives the second clock signal CLKB, and its output terminal is coupled to the input terminal of inverter INV4. The source of transistor T7 is coupled to the input voltage Vin, its drain is coupled to the drain of transistor T8, the source of transistor T8 is coupled to ground, and the gates of transistors T7 and T8 are coupled to the output terminal of inverter INV4. The common terminal of the drains of transistors T7 and T8 is used to output the second voltage V2.

[0027] The charge pump circuit 100 utilizes the high-pass characteristics of pumping capacitors C1 and C2 to continuously superimpose the input voltage Vin onto the reference voltage Vref, thereby maintaining the gate drive voltage Vgate at the output terminal at a high voltage.

[0028] In the prior art charge pump circuit 100, transistors T5 and T7 are P-type field-effect transistors. When the input voltage Vin is low, for example, below the threshold voltage of transistors T5 and T7, transistors T5 and T7 cannot be turned on, which in turn causes the circuit to malfunction.

[0029] Figure 2 A schematic circuit diagram of another prior art charge pump circuit for load switching is shown. (Example) Figure 2 As shown, the main difference between charge pump circuit 200 and charge pump circuit 100 is that the positions of the reference voltage Vref and the input voltage Vin are interchanged. At this time, the circuit can still work normally when the input voltage Vin is low. However, the reference voltage Vref is not a strong power supply, its driving capability is weak, and it may even be higher than the power supply voltage of the internal circuit. Therefore, the entire charge pump circuit 200 needs to be powered by the reference voltage Vref, which causes the voltage to have a large attenuation. As a result, the output gate drive voltage Vgate may not reach the level of Vin+5V, which increases the on-resistance of the driven load switch and reduces the driving efficiency.

[0030] Figure 3 A schematic circuit diagram of a charge pump circuit for a load switch according to an embodiment of the present invention is shown. Figure 3 As shown, the charge pump circuit 300 includes a boost module 310, a first drive module 320, a second drive module 330, a first auxiliary module 340, and a second auxiliary module 350. The boost module 310 includes a first input terminal 101 for receiving a first voltage V1, a second input terminal 102 for receiving a second voltage V2, a third input terminal 103 for receiving a reference voltage Vref, and an output terminal 104 for outputting the boosted gate drive voltage Vgate. The first drive module 320 is coupled to the boost module 310 and provides the first voltage V1 to the first input terminal 101 according to a first clock signal CLK and an input voltage Vin. The second drive module 330 is coupled to the boost module 310 and provides the second voltage V2 to the second input terminal 102 according to a second clock signal CLKB and an input voltage Vin. The first clock signal CLK and the second clock signal CLKB are differential clock signals, and the reference voltage Vref is a 5V voltage generated internally by the circuit.

[0031] Specifically, the boost module 310 includes pump capacitor C1, pump capacitor C2, and transistors T1-T4. The first end of pump capacitor C1 is coupled to the first input terminal 101 to receive the first voltage V1, and the second end is coupled to the intermediate node 1a inside the boost module 310. The first end of pump capacitor C2 is coupled to the second input terminal 102 to receive the second voltage V2, and the second end is coupled to the intermediate node 1b inside the boost module 310. Transistors T1-T4 adopt a differential cross-coupled architecture. Transistors T1 and T2 are N-type field-effect transistors, and transistors T3 and T4 are P-type field-effect transistors. The sources of transistors T1 and T2 are coupled to the third input terminal 103 to receive the reference voltage Vref. The drains of transistors T1 and T3, and the gates of transistors T2 and T4 are coupled to the intermediate node 1a. The drains of transistors T2 and T4, and the gates of transistors T1 and T3 are coupled to the intermediate node 1b. The sources of transistors T3 and T4 are coupled to the output terminal 104.

[0032] The first driving module 320 includes inverters INV1 and INV2, and transistors T5 and T6. The power supply terminals of inverters INV1 and INV2 are coupled to a bias voltage Vbias. The input terminal of inverter INV1 receives a first clock signal CLK, and its output terminal is coupled to the input terminal of inverter INV2. The source of transistor T5 is coupled to the input voltage Vin, its drain is coupled to the drain of transistor T6, the source of transistor T6 is coupled to ground, and the gates of transistors T5 and T6 are coupled to the output terminal of inverter INV2. Transistor T5 is a P-type field-effect transistor, and transistor T6 is an N-type field-effect transistor. The common terminal of the drains of transistors T5 and T6 is used to output the first voltage V1.

[0033] Similarly, the second drive module 330 includes inverters INV3 and INV4, and transistors T7 and T8. The power supply terminals of inverters INV3 and INV4 are coupled to a bias voltage Vbias. The input terminal of inverter INV3 receives the second clock signal CLKB, and its output terminal is coupled to the input terminal of inverter INV4. The source of transistor T7 is coupled to the input voltage Vin, its drain is coupled to the drain of transistor T8, the source of transistor T8 is coupled to ground, and the gates of transistors T7 and T8 are coupled to the output terminal of inverter INV4. Transistor T7 is a P-type field-effect transistor, and transistor T8 is an N-type field-effect transistor. The common terminal of the drains of transistors T7 and T8 is used to output the second voltage V2.

[0034] The first auxiliary module 340 is coupled to the first drive module 320 and the boost module 310, and is used to provide an auxiliary channel for converting the input voltage Vin to a first voltage V1 when the input voltage Vin is low, and to pump the bias voltage Vbias to the intermediate node 1a of the boost module 310. The second auxiliary module 350 is coupled to the second drive module 330 and the boost module 310, and is used to provide an auxiliary channel for converting the input voltage Vin to a second voltage V2 when the input voltage Vin is low, and to pump the bias voltage Vbias to the intermediate node 1b of the boost module 310. This allows the input voltage Vin to be effectively transferred to the first voltage V1 and the second voltage V2 when transistors T5 and T7 cannot conduct properly due to a low input voltage Vin. At the same time, by pumping the bias voltage Vbias to intermediate nodes 1a and 1b, the potentials of intermediate nodes 1a and 1b are raised, ensuring that transistors T3 and T4 in the boost module 310 can also conduct normally. The entire circuit is no longer limited by the threshold voltage of the transistors and can work normally even when the input voltage Vin is very low, thus improving the efficiency of the circuit.

[0035] Specifically, the first auxiliary module 340 includes an auxiliary transistor T5b and an auxiliary capacitor C1b. The drain of the auxiliary transistor T5b is coupled to the input voltage Vin, the gate is coupled to the output terminal of the inverter INV1, and the source is coupled to the common terminal of the drains of transistors T5 and T6. The first terminal of the auxiliary capacitor C1b is coupled to the output terminal of the inverter INV1, and the second terminal is coupled to the intermediate node 1a. The auxiliary transistor T5b and the transistor T5 conduct complementaryly. When the input voltage Vin is low, the input voltage Vin is transferred to the first voltage V1 through the auxiliary transistor T5b. The auxiliary capacitor C1b is used to pump the bias voltage Vbias to the intermediate node 1a, so that the potential of the intermediate node 1a is: V1a = Vin + K(Vbias - Vin), where K is the proportional coefficient of the auxiliary capacitor C1b and the pumping capacitor C1. The proportional coefficient can be adjusted appropriately to increase the potential of the intermediate node 1a.

[0036] Similarly, the second auxiliary module 350 includes an auxiliary transistor T7b and an auxiliary capacitor C2b. The drain of the auxiliary transistor T7b is coupled to the input voltage Vin, the gate is coupled to the output of the inverter INV1, and the source is coupled to the common terminal of the drains of transistors T7 and T8. The first terminal of the auxiliary capacitor C2b is coupled to the output of the inverter INV1, and the second terminal is coupled to the intermediate node 1b. The auxiliary transistor T7b and the transistor T7 conduct complementaryly. When the input voltage Vin is low, the input voltage Vin is transferred to the second voltage V2 through the auxiliary transistor T7b. The auxiliary capacitor C2b is used to pump the bias voltage Vbias to the intermediate node 1b, so that the potential of the intermediate node 1b is: V1b = Vin + K(Vbias - Vin), where K is the proportional coefficient of the auxiliary capacitor C2b and the pumping capacitor C2b. The proportional coefficient can be adjusted appropriately to increase the potential of the intermediate node 1b.

[0037] In summary, the charge pump circuit for load switching in this embodiment of the invention further includes an auxiliary module. This auxiliary module provides an auxiliary channel for converting the input voltage into the voltage at the input terminal of the boost module when the input voltage is low. This allows for effective transfer of the input voltage to the boost module even when the low input voltage prevents the transistors in the drive module from conducting properly. Furthermore, the auxiliary module pumps a bias voltage to the intermediate node of the boost module, raising its potential and ensuring that the P-type field-effect transistors in the boost module can also conduct normally. The entire circuit is no longer limited by the threshold voltage of the transistors and can operate normally even with very low input voltages, thus improving circuit efficiency.

[0038] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0039] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A charge pump circuit for a load switch, the charge pump circuit being used to convert an input voltage into a gate drive voltage for the load switch, wherein, The charge pump circuit includes: The boost module has a first input terminal for receiving a first voltage, a second input terminal for receiving a second voltage, a third input terminal for receiving a reference voltage, and an output terminal for outputting the boosted gate drive voltage. A first driving module, coupled to the boost module, is used to provide the first voltage to the first input terminal according to the first clock signal and the input voltage. The first driving module includes: first and second inverters, the input terminal of the first inverter is used to receive the first clock signal, and the output terminal of the first inverter is coupled to the input terminal of the second inverter; and a fifth and a sixth transistor, the source of the fifth transistor is coupled to the input voltage, the drain of the fifth transistor is coupled to the drain of the sixth transistor, the source of the sixth transistor is coupled to ground, and the gate of the fifth and sixth transistors is coupled to the output terminal of the second inverter, wherein the common terminal of the drains of the fifth and sixth transistors serves as the output terminal of the first voltage. A second driving module, coupled to the boost module, is used to provide the second voltage to the second input terminal according to the second clock signal and the input voltage. The second driving module includes: a third and a fourth inverter, the input terminal of the third inverter is used to receive the second clock signal, and the output terminal of the third inverter is coupled to the input terminal of the fourth inverter; and a seventh and an eighth transistor, the source of the seventh transistor is coupled to the input voltage, the drain of the seventh transistor is coupled to the drain of the eighth transistor, the source of the eighth transistor is coupled to ground, and the gate of the seventh and eighth transistors is coupled to the output terminal of the fourth inverter, wherein the common terminal of the drains of the seventh and eighth transistors serves as the output terminal of the second voltage. The charge pump circuit further includes: A first auxiliary module, coupled to the first driving module and the boost module, is used to provide a first auxiliary channel to convert the input voltage to the first voltage when the input voltage is low. The first auxiliary module includes: a first auxiliary transistor, the drain of which is coupled to the input voltage, the gate of which is coupled to the output of the first inverter, and the source of which is coupled to the common terminal of the drains of the fifth and sixth transistors; and a first auxiliary capacitor, the first terminal of which is coupled to the output of the first inverter, and the second terminal of which is coupled to the first intermediate node of the boost module; and A second auxiliary module, coupled to the second driving module and the boost module, is used to provide a second auxiliary channel to convert the input voltage to the second voltage when the input voltage is low. The second auxiliary module includes: a second auxiliary transistor, the drain of which is coupled to the input voltage, the gate of which is coupled to the output terminal of the third inverter, and the source of which is coupled to the common terminal of the drains of the seventh and eighth transistors; and a second auxiliary capacitor, the first terminal of which is coupled to the output terminal of the third inverter, and the second terminal of which is coupled to the second intermediate node of the boost module. The first auxiliary module and the second auxiliary module are further configured to pump the bias voltage to the boost module.

2. The charge pump circuit according to claim 1, wherein, The boost module includes: a first pumping capacitor, a second pumping capacitor, and first to fourth transistors. Specifically, the first end of the first pumping capacitor is coupled to the first input terminal, and the second end is coupled to the first intermediate node. The first end of the second pumping capacitor is coupled to the second input terminal, and the second end is coupled to the second intermediate node. The sources of the first and second transistors are coupled to the third input terminal, and the sources of the third and fourth transistors are coupled to the output terminal. The drains of the first and third transistors, and the gates of the second and fourth transistors, are coupled to the first intermediate node. The drains of the second and fourth transistors, as well as the gates of the first and third transistors, are coupled to the second intermediate node.

3. The charge pump circuit according to claim 1, wherein, The power supply terminals of the first and second inverters, as well as the third and fourth inverters, are all used to receive the bias voltage.

4. The charge pump circuit according to claim 1, wherein, The first auxiliary transistor and the fifth transistor are complementary in conduction.

5. The charge pump circuit according to claim 1, wherein, The power supply terminals of the third and fourth inverters are used to receive the bias voltage.

6. The charge pump circuit according to claim 1, wherein, The first clock signal and the second clock signal are differential clock signals.

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