Charge pump circuit

Abstract

A charge pump circuit is provided. The charge pump circuit includes a dual-phase charge pump, a first load switch, a second load switch, and a control circuit. The dual-phase charge pump is responsive to a first clock and a second clock to perform voltage pumping operations on a power supply to generate a first pumped voltage at a first node and a second pumped voltage at a second node. The control circuit is responsive to a third clock to control the first load switch and responsive to a fourth clock to control the second load switch. During a period when the first load switch is open, the second load switch transfers the first pumped voltage to an output of the charge pump circuit. During a period when the second load switch is open, the first load switch transfers the second pumped voltage to the output.

Description

Technical Field

[0001] This invention relates to a charge pump circuit, and more particularly to a charge pump circuit with high efficiency. Background Technology

[0002] Figure 1 This is a schematic diagram of a common two-phase charge pump circuit 10. The two-phase charge pump circuit 10 includes a two-phase charge pump 11 and transfer transistors P1 and P2. The two-phase charge pump 11 includes power transistors M1 and M2 and capacitors C3 and C4. The first terminal of power transistor M1 is coupled to the power supply VDDA. The second terminal and control terminal of power transistor M1 are coupled to node ND1. The first terminal of power transistor M2 is coupled to the power supply VDDA. The second terminal and control terminal of power transistor M2 are coupled to node ND2. Capacitor C1 is coupled between node ND1 and clock CK1. Capacitor C2 is coupled between node ND2 and clock CK2. The first terminal and control terminal of transfer transistor P1 are coupled to node ND2. The second terminal of transfer transistor P1 is coupled to the output terminal. The first terminal and control terminal of transfer transistor P2 are coupled to node ND1. The second terminal of transfer transistor P2 is coupled to the output terminal.

[0003] During operation, when clock CK1 transitions from a low voltage level to a high voltage level, clock CK2 transitions from a high voltage level to a low voltage level. Transmission transistor P1 is turned off. Transmission transistor P2 is turned on. Therefore, transmission transistor P2 can provide the pumped voltage at node ND1 to the output. When clock CK1 transitions from a high voltage level to a low voltage level, clock CK2 transitions from a low voltage level to a high voltage level. Transmission transistor P2 is turned off. Transmission transistor P1 is turned on. Therefore, transmission transistor P1 can provide the pumped voltage at node ND2 to the output.

[0004] However, capacitors C3 and C4 delay the charging and discharging at nodes ND1 and ND2. This delay postpones the turn-off time of transfer transistors P1 and P2, resulting in a reverse leakage current Irev. For example, when clock CK1 transitions from a low voltage level to a high voltage level and clock CK2 transitions from a high voltage level to a low voltage level, transfer transistor P2 provides the pumped voltage at node ND1 to the output. The discharge at node ND2 is delayed. Transfer transistor P1 fails to turn off in time. Therefore, the energy pumped to the output will flow back to the power supply VDDA via transfer transistor P1 and the turned-on power transistor M2, generating a reverse leakage current Irev. Consequently, the efficiency of the dual-phase charge pump circuit 10 is lower. Summary of the Invention

[0005] This invention provides a charge pump circuit with high efficiency.

[0006] The charge pump circuit of this invention includes a two-phase charge pump, a first load switch, a second load switch, and a control circuit. The two-phase charge pump responds to a first clock and a second clock to perform voltage boosting operations on the power supply, thereby generating a first boosted voltage at a first node and a second boosted voltage at a second node. The first load switch is coupled between the second node and the output terminal of the two-phase charge pump circuit. The second load switch is coupled between the first node and the output terminal. The control circuit is coupled to the first load switch and the second load switch. The control circuit responds to a third clock to control the first load switch and responds to a fourth clock to control the second load switch. During the period when the first load switch is open, the second load switch transmits the first boosted voltage to the output terminal. During the period when the second load switch is open, the first load switch transmits the second boosted voltage to the output terminal.

[0007] Based on the above, the charge pump circuit of the present invention utilizes a control circuit to control a first load switch and a second load switch. Further, the control circuit responds to a third clock to control the first load switch and to a fourth clock to control the second load switch. During the period when the second load switch is open, the first load switch transmits a first pump-up voltage to the output terminal. During the period when the first load switch is open, the second load switch transmits a second pump-up voltage to the output terminal. The charge pump circuit of the present invention does not experience reverse leakage current. Therefore, the efficiency of the charge pump circuit can be improved.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of an existing and common two-phase charge pump circuit.

[0010] Figure 2 This is a schematic diagram of a charge pump circuit according to the first embodiment of the present invention.

[0011] Figure 3 This is a signal waveform diagram drawn according to an embodiment of the present invention.

[0012] Figure 4 This is a schematic diagram of a charge pump circuit according to a second embodiment of the present invention.

[0013] Figure 5 This is a schematic diagram of a charge pump circuit according to a third embodiment of the present invention.

[0014] Figure 6 This is a schematic diagram of a charge pump circuit according to the fourth embodiment of the present invention.

[0015] Explanation of reference numerals in the attached figures

[0016] 10, 100, 200, 300, 400: Charge pump circuit

[0017] 110, 410: Two-phase charge pumps

[0018] 120, 220: Control circuit

[0019] 230, 330: Adjustment circuit

[0020] 231, 331: Charge storage circuit

[0021] 340: Voltage divider circuit

[0022] C1, C2, Cx: Capacitors

[0023] C3, C4: Control capacitors

[0024] CK1~CK4: Clocks

[0025] I_VDDA: Current of the power supply

[0026] Ib: Current source

[0027] IOUT: Output current

[0028] Irev: Reverse leakage current

[0029] M1, M2: Power transistors

[0030] M3, M4: Control transistors

[0031] MA1, MA2: Adjusting transistors

[0032] ND1~ND4: Nodes

[0033] P1, P2: Transmission transistors

[0034] R1, R2: Resistors

[0035] SW1, SW2: Load switches

[0036] t: time

[0037] t1~t8: Time points

[0038] TO: Output terminal

[0039] V_VDDA: Voltage of the power supply

[0040] VDDA: Power supply

[0041] VOUT: Output voltage

[0042] VP1, VP2: Pump boost voltage

[0043] Vx: Auxiliary bias value

[0044] Vy: Base bias voltage

[0045] W1, W2: Trap Detailed Implementation

[0046] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.

[0047] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a charge pump circuit according to a first embodiment of the present invention. In this embodiment, the charge pump circuit 100 includes a two-phase charge pump 110, load switches SW1 and SW2, and a control circuit 120. The two-phase charge pump 110 responds to clocks CK1 and CK2 to perform voltage boosting operation on the power supply VDDA. Therefore, the two-phase charge pump 110 generates a boost voltage VP1 at node ND1 and a boost voltage VP2 at node ND2. The voltage values ​​of the boost voltages VP1 and VP2 are higher than the voltage value of the power supply VDDA.

[0048] In this embodiment, the dual-phase charge pump 110 includes power transistors M1 and M2 and capacitors C1 and C2. The first terminal of power transistor M1 is coupled to power supply VDDA. The second terminal and control terminal of power transistor M1 are coupled to node ND1. The first terminal of power transistor M2 is coupled to power supply VDDA. The second terminal and control terminal of power transistor M2 are coupled to node ND2. Capacitor C1 is coupled between node ND1 and clock CK1. Capacitor C2 is coupled between node ND2 and clock CK2. In this embodiment, when clock CK1 is at a high voltage level and clock CK2 is at a low voltage level, the voltage at node ND1 is pumped up to generate a pumped voltage VP1. The voltage at node ND2 returns to approximately equal to the voltage value of power supply VDDA. When clock CK2 is at a high voltage level and clock CK1 is at a low voltage level, the voltage at node ND2 is pumped up to generate a pumped voltage VP2. The voltage at node ND1 will recover to approximately equal to the voltage of the power supply VDDA.

[0049] In this embodiment, load switch SW1 is coupled between node ND2 and the output terminal TO of the dual-phase charge pump circuit 100. Load switch SW2 is coupled between node ND1 and the output terminal TO of the dual-phase charge pump circuit 100. Control circuit 120 is coupled to load switches SW1 and SW2. Control circuit 120 responds to clock CK3 to control load switch SW1 and responds to clock CK4 to control load switch SW2. During the period when load switch SW1 is open, load switch SW2 transmits the pumped voltage VP1 to the output terminal TO. Therefore, the pumped voltage VP1 transmitted to the output terminal TO is used as the output voltage VOUT. During the period when load switch SW2 is open, load switch SW1 transmits the pumped voltage VP2 to the output terminal TO. Therefore, the pumped voltage VP2 transmitted to the output terminal TO is used as the output voltage VOUT.

[0050] It is worth mentioning that the control circuit 120 controls the load switches SW1 and SW2 based on clocks CK3 and CK4. When load switch SW1 is open, load switch SW2 transfers the pumped voltage VP1 to the output terminal TO. The power of the output voltage VOUT is not fed back to the power supply VDDA via the open load switch SW1. When load switch SW2 is open, load switch SW1 transfers the pumped voltage VP2 to the output terminal TO. The power of the output voltage VOUT is not fed back to the power supply VDDA via the open load switch SW2. During operation, the dual-phase charge pump 110 does not have reverse leakage current. In this way, the efficiency of the charge pump circuit 100 can be improved.

[0051] Load switches SW1 and SW2 are implemented using transistors or transmission gates of any type. In this embodiment, load switches SW1 and SW2 are implemented using P-type metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0052] Please also refer to Figure 2 as well as Figure 3 , Figure 3 This is a signal waveform diagram illustrated according to an embodiment of the present invention. The signal waveform diagram shows the waveforms of the output voltage VOUT, the output current IOUT, the voltage V_VDDA of the power supply VDDA, the current I_VDDA of the power supply VDDA, and the clock waveforms CK1 to CK4. The horizontal axis of the signal waveform diagram is uniformly represented by time t. The unit of time t is microsecond (μs).

[0053] At time t1, clock CK3 transitions from a low voltage level to a high voltage level. Load switch SW1 is disconnected in response to the high voltage level of clock CK3. Immediately following time t1, clock CK2 transitions from a high voltage level to a low voltage level at time t2. Clock CK1 transitions from a low voltage level to a high voltage level at time t3. Therefore, the voltage at node ND1 will begin to be pumped up at time t3 to pump up voltage VP1. The voltage value at node ND2 will return to approximately equal to the voltage value of the power supply VDDA. In this embodiment, the transition time of clock CK1 from a low voltage level to a high voltage level (i.e., time t3) is later than time t1. That is, the start time of the generation of the pumped voltage VP1 (i.e., time t3) is later than the time when load switch SW1 is disconnected.

[0054] Next, at time t4, clock CK4 transitions from a high voltage level to a low voltage level. Load switch SW2 is turned on in response to the low voltage level of clock CK4. The time t4 when load switch SW2 is turned on is later than time t3. That is, control circuit 120 turns on load switch SW2 only after the pump-up voltage VP1 is generated.

[0055] At time t5, clock CK4 transitions from a low voltage level to a high voltage level. Load switch SW2 is disconnected in response to the high voltage level of clock CK4. Immediately following time t5, clock CK1 transitions from a high voltage level to a low voltage level at time t6. Clock CK2 transitions from a low voltage level to a high voltage level at time t7. Therefore, the voltage at node ND2 will begin to be pumped up at time t7 to pump up voltage VP2. The voltage value at node ND1 will return to approximately equal to the voltage value of the power supply VDDA. In this embodiment, the transition time of clock CK2 from a low voltage level to a high voltage level (i.e., time t7) is later than the time when load switch SW2 is disconnected (i.e., time t5). That is, the start time of the pumped voltage VP2 (i.e., time t7) is later than the time when load switch SW2 is disconnected.

[0056] Next, at time t8, clock CK3 transitions from a high voltage level to a low voltage level. Load switch SW1 is turned on in response to the low voltage level of clock CK3. The time t8 when load switch SW2 is turned on is later than time t7. That is, control circuit 120 turns on load switch SW1 only after the pump-up voltage VP2 is generated.

[0057] During the time interval from time t1 to time t8, load switch SW1 is in the open state. The boost voltage VP1 is generated only during the period when load switch SW1 is determined to be in the open state. Furthermore, during the period when boost voltage VP1 is generated (i.e., the time interval from time t3 to time t6), load switch SW2 is turned on during the time interval from time t4 to time t5. As a result, the reverse leakage current flowing through load switch SW1 is not generated.

[0058] Similarly, the boost voltage VP2 is generated only during the period when the load switch SW2 is determined to be in the off state. Furthermore, during the period when the boost voltage VP2 is generated, the load switch SW1 is turned on. As a result, the reverse leakage current flowing through the load switch SW2 is not generated.

[0059] In this embodiment, the voltage V_VDDA of the power supply VDDA is maintained at 1.1 volts. The absolute value of the average current I_VDDA of the power supply VDDA is approximately 4.0007 mA. The output voltage VOUT is approximately 1.8944 volts. The output current IOUT is approximately 2.0018 mA. Therefore, the efficiency of the charge pump circuit 100 is 86.2%. It should be noted that, as... Figure 1 The efficiency of the two-phase charge pump circuit 10 shown is approximately 56%. Therefore, the efficiency of the charge pump circuit 100 is significantly higher than that of the two-phase charge pump circuit 10.

[0060] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a charge pump circuit according to a second embodiment of the present invention. In this embodiment, the charge pump circuit 200 includes a two-phase charge pump 110, load switches SW1 and SW2, and a control circuit 220. The implementation of the two-phase charge pump 110 has been clearly described in the first embodiment and will not be repeated here. In this embodiment, the control circuit 220 includes control transistors M3 and M4, and control capacitors C3 and C4. The first terminal of control transistor M3 is coupled to a voltage source VDDA. The second terminal of control transistor M3 is coupled to node ND3. The control terminal of control transistor M3 is coupled to node ND2. The first terminal of control transistor M4 is coupled to a voltage source VDDA. The second terminal of control transistor M4 is coupled to node ND4. The control terminal of control transistor M4 is coupled to node ND1. Control capacitor C3 is coupled between node ND3 and clock CK3. Control capacitor C4 is coupled between node ND4 and clock CK4.

[0061] In this embodiment, the control terminal of load switch SW1 is coupled to node ND3. The control terminal of load switch SW2 is coupled to node ND4. Control circuit 220 responds to clock CK3 to provide a first control signal SC1. Control circuit 220 uses the first control signal SC1 to control load switch SW1. Furthermore, control circuit 220 also responds to clock CK4 to provide a second control signal SC2. Control circuit 220 uses the second control signal SC2 to control load switch SW2.

[0062] Please also refer to Figure 3 as well as Figure 4 In this embodiment, during the time interval during which the pump-up voltage VP1 is generated (i.e., the time interval from time point t3 to time point t6), the pump-up voltage VP2 will not be generated. Therefore, control transistor M3 is turned off. Control transistor M4 is turned on. The voltage level of node ND3 is pumped up based on clock CK3. The voltage level of node ND4 is approximately equal to the voltage level of power supply VDDA. Since time points t1 and t2 are very close, the state transition of clock CK3, based on the delay of control capacitor C3, can still pump up the voltage level of node ND3 to generate a first control signal SC1 with a first voltage level. The first voltage level is higher than the voltage level of power supply VDDA. Therefore, load switch SW1 is turned off in response to the first control signal SC1 with the first voltage level. Therefore, load switch SW2 is turned on in response to the second control signal SC2 with the voltage level of power supply VDDA.

[0063] During the time interval during which the pump-up voltage VP2 is generated, the pump-up voltage VP1 will not be generated. Therefore, control transistor M4 is turned off, while control transistor M3 is turned on. Since time points t5 and t6 are very close, the state transition of clock CK4, based on the delay of control capacitor C4, still allows the voltage level at node ND4 to be pumped up to generate a second control signal SC2 with a first voltage level. Therefore, load switch SW2 is turned off in response to the second control signal SC2 with a first voltage level. The voltage level at node ND3 is approximately equal to the voltage level of power supply VDDA. Therefore, load switch SW1 is turned on in response to the first control signal SC1 with a voltage level of power supply VDDA.

[0064] In this embodiment, the charge pump circuit 200 further includes an adjustment circuit 230. The adjustment circuit 230 is coupled to the control circuit 220 and the load switches SW1 and SW2. The adjustment circuit 230 adjusts the base bias values ​​of the load switches SW1 and SW2 in response to the pump boost voltages VP1 and VP2, the first control signal SC1, and the second control signal SC2.

[0065] In this embodiment, the adjustment circuit 230 includes adjustment transistors MA1 and MA2 and a charge storage circuit 231. The first terminal of adjustment transistor MA1 is coupled to node ND2. The second terminal and base of adjustment transistor MA1 are coupled to the base of load switch SW1. The control terminal of adjustment transistor MA1 is coupled to node ND3. The first terminal of adjustment transistor MA2 is coupled to node ND1. The second terminal and base of adjustment transistor MA2 are coupled to the base of load switch SW2. The control terminal of adjustment transistor MA2 is coupled to node ND4. The charge storage circuit 231 is coupled to the second terminals of adjustment transistors MA1 and MA2. The charge storage circuit 231 stores the charge of the pump-up voltages VP1 and VP2 to generate an auxiliary bias voltage Vx to determine the base bias voltage. In this embodiment, the base bias voltage is adjusted based on the auxiliary bias voltage Vx to be greater than the voltage value located at the output terminal TO. In this way, the adjustment circuit 230 can prevent the load switches SW1 and SW2 from experiencing a latch-up effect.

[0066] It should be noted that the second terminal of control transistor M3 is coupled to the control terminal of regulating transistor MA1 and the control terminal of load switch SW1. The second terminal of control transistor M4 is coupled to the control terminal of regulating transistor MA2 and the control terminal of load switch SW2. Control transistors M3 and M4 do not become paths for reverse leakage current. Furthermore, the second terminals of regulating transistors MA1 and MA2 are both coupled to the bases of load switches SW1 and SW2. Therefore, regulating transistors MA1 and MA2 do not become paths for reverse leakage current.

[0067] In this embodiment, the control circuit 220 does not perform the transmission of the pump-up voltages VP1 and VP2, but instead controls the load switches SW1 and SW2 and the regulating transistors MA1 and MA2. Therefore, the layout area of ​​the control transistors M3 and M4 can be allowed to be smaller than the layout area of ​​the power supply transistors M1 and M2. In some embodiments, the layout area of ​​the control capacitors C3 and C4 can be allowed to be smaller than the layout area of ​​the capacitors C1 and C2. For example, the layout area of ​​the control circuit 220 can be 5% of the layout area of ​​the dual-phase charge pump 110, but this invention is not limited thereto.

[0068] In this embodiment, the charge storage circuit 231 includes a capacitor Cx. The capacitor Cx is coupled between a reference low voltage (e.g., ground) and a second terminal of the regulating transistors MA1 and MA2. The capacitor Cx stores the charge of the pump-up voltages VP1 and VP2.

[0069] Please refer to Figure 5 , Figure 5This is a schematic diagram of a charge pump circuit according to a third embodiment of the present invention. The charge pump circuit 300 includes a dual-phase charge pump 110, load switches SW1 and SW2, a control circuit 220, an adjustment circuit 330, and a voltage divider circuit 340. The implementations of the dual-phase charge pump 110, load switches SW1 and SW2, and control circuit 220 have been clearly described in the first and second embodiments, and therefore will not be repeated. In this embodiment, the adjustment circuit 330 includes adjustment transistors MA1 and MA2 and a charge storage circuit 331. The first terminal of adjustment transistor MA1 is coupled to node ND2. The second terminal of adjustment transistor MA1 and the base of adjustment transistor MA1 are coupled to the base of load switch SW1. The control terminal of adjustment transistor MA1 is coupled to node ND3. The first terminal of adjustment transistor MA2 is coupled to node ND1. The second terminal of adjustment transistor MA2 and the base of adjustment transistor MA2 are coupled to the base of load switch SW2. The control terminal of adjustment transistor MA2 is coupled to node ND4. Charge storage circuit 331 is coupled to the second terminal of regulating transistor MA1 and the second terminal of regulating transistor MA2. Charge storage circuit 331 stores the charge of pump-up voltages VP1 and VP2 to generate auxiliary bias voltage Vx. Voltage divider circuit 340 is coupled to the base of charge storage circuit 331 and load switches SW1 and SW2.

[0070] In this embodiment, the charge storage circuit 331 stores the charge of the pump boost voltages VP1 and VP2 to generate an auxiliary bias voltage value Vx. The voltage divider circuit 340 receives the auxiliary bias voltage value Vx from the charge storage circuit 331 and divides it to generate a base bias voltage value Vy. Based on the voltage divider operation of the voltage divider circuit 340, the threshold voltages of the load switches SW1 and SW2 are reduced. The on-resistance values ​​of the load switches SW1 and SW2 are reduced. The load switches SW1 and SW2 can transfer larger current values, thereby improving the efficiency of the charge pump circuit 300.

[0071] In this embodiment, the voltage divider circuit 340 includes resistors R1 and R2 and a current source Ib. The first terminal of resistor R1 is coupled to the charge storage circuit 331 and receives an auxiliary bias voltage Vx. The second terminal of resistor R1 is coupled to the voltage divider node. The first terminal of resistor R2 is coupled to the voltage divider node. The current source Ib is coupled to the second terminal of resistor R2. The current source Ib is used to limit the operating current of the voltage divider circuit 340, thereby controlling the voltage difference across resistor R1 and the base bias voltage Vy.

[0072] Furthermore, the voltage difference across resistor R1 can be determined based on the operating current provided by current source Ib. The voltage difference across resistor R1 is defined as being less than the forward bias value of the parasitic diode. For example, the voltage difference across resistor R1 is 0.5 volts to 0.6 volts. Therefore, the voltage divider circuit 340 can prevent latch-up from occurring in the charge pump circuit 300.

[0073] In some embodiments, at least one of resistors R1 and R2 may be implemented by a variable resistor circuit.

[0074] Please refer to Figure 6 , Figure 6 This is a schematic diagram of a charge pump circuit according to a fourth embodiment of the present invention. In this embodiment, the charge pump circuit 400 is disposed on a substrate. The charge pump circuit 400 can be an on-chip circuit. The charge pump circuit 400 includes a dual-phase charge pump 410, load switches SW1 and SW2, a control circuit 220, an adjustment circuit 330, and a voltage divider circuit 340. The embodiments of the load switches SW1 and SW2, the control circuit 220, the adjustment circuit 330, and the voltage divider circuit 340 have been clearly described in the above embodiments and will not be repeated here. In this embodiment, the dual-phase charge pump 410 includes power transistors M1 and M2 and capacitors C1 and C2. The first terminal of the power transistor M1 is coupled to the power supply VDDA. The second terminal of the power transistor M1 and the control terminal of the power transistor M1 are coupled to node ND1. The first terminal of the power transistor M2 is coupled to the power supply VDDA. The second terminal of the power transistor M2 and the control terminal of the power transistor M2 are coupled to node ND2.

[0075] It should be noted that in this embodiment, the first end of capacitor C1 is coupled to node ND1. The second end of capacitor C1 is coupled to well W1 of the substrate. Capacitor C1 receives clock CK1 through well W1. The first end of capacitor C2 is coupled to node ND2. The second end of capacitor C2 is coupled to well W2 of the substrate. Capacitor C2 receives clock CK2 through well W2.

[0076] In this embodiment, when capacitor C1 receives clock CK1 through well W1, capacitor C1 and well W1 are considered to be connected in series. Capacitor C1 and well W1 together provide an equalization capacitance value. Since the well W1 of the substrate has a very low capacitance value (i.e., parasitic capacitance value), the equalization capacitance value will be significantly lower than the capacitance value of capacitor C1. As a result, node ND1 will have a faster response speed. The charging and discharging times of node ND1 can be shortened.

[0077] Similarly, when capacitor C2 receives clock CK2 through well W2, capacitor C2 and well W2 are considered to be connected in series. Capacitor C2 and well W2 together provide an equalization capacitance value. Since the well W2 of the substrate has a very low capacitance value, the equalization capacitance value will be significantly lower than the capacitance value of capacitor C2. As a result, node ND2 will have a faster response speed. The charging and discharging times of node ND2 can be shortened.

[0078] In this embodiment, wells W1 and W2 are both N-type wells. In some embodiments, wells W1 and W2 are both heavily doped N-type wells.

[0079] In summary, the control circuit of the charge pump circuit of the present invention responds to a third clock to control the first load switch and responds to a fourth clock to control the second load switch. During the period when the second load switch is open, the first load switch transmits a first pump-up voltage to the output terminal. During the period when the first load switch is open, the second load switch transmits a second pump-up voltage to the output terminal. The charge pump circuit of the present invention does not experience reverse leakage current. Therefore, the efficiency of the charge pump circuit can be improved. In some embodiments, the adjustment circuit of the charge pump circuit can adjust the base bias values ​​of the first and second load switches to be greater than the voltage value located at the output terminal. Therefore, the adjustment circuit can prevent latch-up effects in the first and second load switches. Furthermore, in some embodiments, the first capacitor of the biphase charge pump receives the first clock through a first well. The second capacitor of the biphase charge pump receives the second clock through a second well. Therefore, the first and second nodes will have faster response speeds. The charging and discharging times of the first and second nodes can be shortened.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A charge pump circuit, characterized in that, include: A dual-phase charge pump is configured to respond to a first clock and a second clock to perform voltage boosting operations on the power supply, thereby generating a first boosted voltage at a first node and a second boosted voltage at a second node. A first load switch is coupled between the second node and the output terminal of the dual-phase charge pump circuit; A second load switch is coupled between the first node and the output terminal; as well as A control circuit, coupled to the first load switch and the second load switch, is configured to respond to a third clock to control the first load switch and to respond to a fourth clock to control the second load switch. During the period when the first load switch is disconnected, the second load switch transmits the first pump-up voltage to the output terminal. During the period when the second load switch is disconnected, the first load switch transmits the second pump-up voltage to the output terminal, and The control circuit includes: A first control transistor, wherein a first terminal of the first control transistor is coupled to a voltage source, a second terminal of the first control transistor is coupled to a third node, and a control terminal of the first control transistor is coupled to a second node; The second control transistor has a first terminal coupled to a voltage source, a second terminal coupled to a fourth node, and a control terminal coupled to the first node. A first control capacitor is coupled between the third node and the third clock; and A second control capacitor is coupled between the fourth node and the fourth clock, wherein the control terminal of the first load switch is coupled to the third node, and wherein the control terminal of the second load switch is coupled to the fourth node.

2. The charge pump circuit according to claim 1, characterized in that, The dual-phase charge pump includes: A first power transistor, wherein a first terminal of the first power transistor is coupled to a power source, and a second terminal of the first power transistor and a control terminal of the first power transistor are coupled to the first node. The second power transistor has a first terminal coupled to a power source, and a second terminal and a control terminal coupled to the second node. A first capacitor is coupled between the first node and the first clock; and The second capacitor is coupled between the second node and the second clock.

3. The charge pump circuit according to claim 2, characterized in that: The charge pump circuit is mounted on the substrate. The first terminal of the first capacitor is coupled to the first node. The second terminal of the first capacitor is coupled to the first well of the substrate and receives the first clock through the first well. The first terminal of the second capacitor is coupled to the second node, and The second terminal of the second capacitor is coupled to the second well of the substrate and receives the second clock through the second well.

4. The charge pump circuit according to claim 1, characterized in that: The first transition point of the first clock from a low voltage level to a high voltage level is later than the transition point of the third clock from a low voltage level to a high voltage level. The time point at which the fourth clock transitions from the high voltage level to the low voltage level is later than the time point of the first transition. The second transition point from the high voltage level to the low voltage level of the first clock is later than the transition point from the low voltage level to the high voltage level of the fourth clock, and The time point at which the third clock transitions from the high voltage level to the low voltage level is later than the time point at which the second clock transitions.

5. The charge pump circuit according to claim 4, characterized in that: The third transition point from the low voltage level to the high voltage level of the second clock is later than the transition point from the high voltage level to the low voltage level of the first clock. The time point at which the third clock transitions from the high voltage level to the low voltage level is later than the time point of the third transition state. The fourth transition point of the second clock from the high voltage level to the low voltage level is later than the transition point of the third clock from the low voltage level to the high voltage level, and The time point at which the fourth clock transitions from the high voltage level to the low voltage level is later than the time point of the fourth transition state.

6. The charge pump circuit according to claim 1, characterized in that, The control circuit responds to the third clock to provide a first control signal for controlling the first load switch, and responds to the fourth clock to provide a second control signal for controlling the second load switch.

7. The charge pump circuit according to claim 6, characterized in that: The first load switch and the second load switch are both field-effect transistors, and The charge pump circuit also includes: An adjustment circuit, coupled to the control circuit, the first load switch, and the second load switch, is configured to adjust the base bias values ​​of the first load switch and the second load switch in response to the first pump-up voltage, the second pump-up voltage, the first control signal, and the second control signal.

8. The charge pump circuit according to claim 7, characterized in that, The adjustment circuit includes: A first regulating transistor, wherein a first terminal of the first regulating transistor is coupled to the second node, a second terminal of the first regulating transistor and the base of the first regulating transistor are coupled to the base of the first load switch, and a control terminal of the first regulating transistor is coupled to the third node; A second regulating transistor, wherein a first terminal of the second regulating transistor is coupled to the first node, a second terminal of the second regulating transistor and the base of the second regulating transistor are coupled to the base of the second load switch, and a control terminal of the second regulating transistor is coupled to the fourth node; and A charge storage circuit, coupled to the second terminal of the first adjustment transistor and the second terminal of the second adjustment transistor, is configured to store the charge of the first pump-up voltage and the second pump-up voltage to generate an auxiliary bias value for determining the base bias value.

9. The charge pump circuit according to claim 8, characterized in that, Also includes: A voltage divider circuit, coupled to the charge storage circuit, the base of the first load switch, and the base of the second load switch, is configured to receive the auxiliary bias value from the charge storage circuit and divide the auxiliary bias value to generate the base bias value.

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