Device with synchronized output

Abstract

Embodiments of the present disclosure relate to devices with synchronized outputs. The present description relates to an electronic device comprising a first input configured to receive a clock signal, coupled to a first circuit through a first input buffer; and at least one output coupled to the first circuit through an output buffer, the output buffer being synchronized on a first edge of the clock signal, wherein the first input buffer comprises a data input coupled to the first input and is configured to maintain a value on its output constant, regardless of a value on its data input, during a time duration following each first edge of the clock signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to French application number 2112398, filed on November 23, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to electronic devices, and in certain embodiments, to devices having synchronous output. Background Technology

[0004] In electronic devices, some devices are those with synchronous outputs. Synchronous outputs are used to indicate outputs that have values ​​modified only during the rising or falling edge of a clock signal. These devices are typically those that output binary values. Summary of the Invention

[0005] One embodiment overcomes all or part of the disadvantages of known electronic devices with synchronous output.

[0006] One embodiment provides an electronic device including: a first input configured to receive a clock signal coupled to a first circuit via a first input buffer; and at least one output coupled to the first circuit via an output buffer synchronized on a first edge of the clock signal, wherein the input buffer includes a data input coupled to the first input and is configured to maintain a constant value on its output for a duration following each first edge of the clock signal, regardless of the value on its data input.

[0007] Another embodiment provides a method for controlling an electronic device, the electronic device comprising: a first input configured to receive a clock signal coupled to a first circuit via a first input buffer; and at least one output coupled to the first circuit via an output buffer synchronized on a first edge of the clock signal, the input buffer including a data input coupled to the first input, wherein for a duration following each first edge of the clock signal, regardless of the value on the data input, the value on the output of the input buffer is maintained constant.

[0008] According to one embodiment, the device includes a second input coupled to a first circuit, the second input being configured to receive a power supply voltage, and a third input coupled to the first circuit, the third input being configured to receive a reference voltage.

[0009] According to one embodiment, the device includes a fourth input coupled to a first circuit via a second input buffer, the fourth input being configured to receive an authorized voltage.

[0010] According to one embodiment, the first circuit includes a memory, and at least one output has a binary value from the memory.

[0011] According to one embodiment, the device includes multiple outputs synchronized on the same clock signal, the outputs being configured to deliver different binary values.

[0012] According to one embodiment, the duration has a value that is less than the period of the clock signal.

[0013] According to one embodiment, the duration has a value less than half the period of the clock signal.

[0014] According to one embodiment, each input buffer includes a control input that receives a control signal that takes a first value during the duration and a second value for the remainder of each time period of the clock signal.

[0015] According to one embodiment, the device includes a logic AND gate configured to receive a control signal on one input and an output signal of a second input buffer on another input, the output of the logic gate being coupled to a control input of the second input buffer.

[0016] According to one embodiment, the device includes a second circuit for generating control signals, the input of which is coupled to the output of a first buffer.

[0017] According to one embodiment, the circuit for generating the control signal includes a delay circuit that introduces a delay equal to the duration T.

[0018] According to one embodiment, the circuit for generating control signals includes a logic gate having an input coupled to the output of a first buffer and another input coupled to the output of the first buffer via a delay circuit. The logic gate is an AND gate if the output buffer is synchronized on a rising edge, or a NOR gate if the output buffer is synchronized on a falling edge. Attached Figure Description

[0019] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 An example of a device to which the embodiments described below can be applied is illustrated schematically;

[0021] Figure 2 The diagram shows... Figure 1 The operation of the equipment;

[0022] Figure 3 An embodiment of a synchronous electronic device is shown;

[0023] Figure 4 The diagram shows... Figure 3 The operation of the embodiment;

[0024] Figure 5 It shows Figure 3 Part of the embodiments; and

[0025] Figure 6 The diagram shows... Figure 5 The operation of the circuit. Detailed Implementation

[0026] In the various figures, the same features have been indicated by the same reference numerals. Specifically, structural and / or functional features common to the various embodiments may have the same reference numerals and may be arranged with the same structure, dimensions, and material properties.

[0027] For clarity, only the steps and elements useful for understanding the embodiments described herein are illustrated and described in detail.

[0028] Unless otherwise indicated, when referring to two elements connected together, it means that there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0029] In the following disclosure, unless otherwise stated, when referring to absolute positional modifiers (such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc.) or relative positional modifiers (such as the terms “above,” “below,” “upper,” “lower,” etc.), or when referring to orientation modifiers (such as “horizontal,” “vertical,” etc.), the orientation shown in the figure is used.

[0030] Unless otherwise stated, the terms “about,” “approximately,” “basically,” and “about” indicate within 10%, and preferably within 5%.

[0031] Figure 1 An example of a device 10 to which the embodiments described below can be applied is schematically illustrated. The device is a device with synchronous output. In an embodiment, device 10 is a memory or a device including a memory. In an embodiment, device 10 is a sequential access memory. In an embodiment, device 10 is a synchronous memory. In an embodiment, device 10 is an integrated circuit.

[0032] Device 10 includes a chip 12. Device 10 includes pins 14 that couple the chip 12 to external circuitry or devices. Figure 1In the example, device 10 includes eight pins 14a, 14b, 14c, 14d, 14e, 14f, 14g, and 14h. Each pin 14 is represented by an inductor 16, a resistor 18, and a block 20 corresponding to the end of the pin.

[0033] Each pin enables the contact pad 22 of chip 12 to be electrically coupled to a voltage source (input pad) or an application node (output pad) for a voltage generated by the chip. In other words, each pin enables the chip 12 to supply voltage from external circuitry, or enables the chip to supply voltage to external circuitry.

[0034] Each end of the pin is coupled to the pad 22 via a series-coupled resistor 18 and inductor 16. Inductor 16 and resistor 18 are, for example, theoretical components and, for example, represent the characteristics of the pin. In practice, the pin is formed, for example, by conductive branches (e.g., metallic branches).

[0035] For example, device 10 includes four input pins 14a, 14b, 14c, and 14d. For example, device 10 includes four output pins 14e, 14f, 14g, and 14h.

[0036] Input pin 14a is coupled to an external node through its end 20a to which voltage SN is applied. End 20a is coupled to contact pad 22a of chip 12 through resistor 18a and inductor 16a (in other words, through a metal branch). Thus, voltage SN-P is applied to pad 22a through pin 14a.

[0037] The signal SN is, for example, a select signal or an authorization signal, and is preferably binary. In other words, the signal SN is, for example, a binary signal that uses a first value to issue an operation command to the device and a second value to issue a stop operation command to the device.

[0038] Input pin 14b is coupled via its end 20b to an external node where a reference voltage GND (e.g., ground) is applied. End 20b is coupled via resistor 18b and inductor 16b (in other words, via a metal branch) to contact pad 22b of chip 12. Thus, voltage GND-P is applied to pad 22b via pin 14b.

[0039] Input pin 14c is coupled to an external node through its end 20c to apply the power supply voltage VDD to chip 12. End 20c is coupled to the contact pad 22c of chip 12 through resistor 18c and inductor 16c (in other words, through a metal branch). Thus, voltage VDD-P is applied to pad 22c through pin 14c.

[0040] Input pin 14d is coupled to an external node through its end 20d to which the clock signal CLK is applied. End 20d is coupled to the contact pad 22d of chip 12 through resistor 18d and inductor 16d (in other words, through a metal branch). Thus, voltage CLK-P is applied to pad 22d through pin 14d.

[0041] Chip 12 includes a contact pad 22e having a voltage Q1-P applied to it by chip 12. The pad 22e is coupled to the end of pin 14e via a resistor 18e and an inductor 16e (in other words, via a metal branch). Thus, pin 14e delivers voltage Q1 at a node of circuitry external to the chip to which it is electrically coupled.

[0042] Chip 12 includes a contact pad 22f having a voltage Q2-P applied thereto by chip 12. The contact pad 22f is coupled to the end of pin 14f via a resistor 18f and an inductor 16f (in other words, via a metal branch). Therefore, pin 14f delivers voltage Q2 at a node of external circuitry electrically coupled to this end.

[0043] Chip 12 includes a contact pad 22g having a voltage Q3-P applied thereto by chip 12. The contact pad 22g is coupled to the end of pin 14g via a resistor 18g and an inductor 16g (in other words, via a metal branch). Therefore, pin 14g delivers voltage Q3 at a node of circuitry external to the chip to which it is electrically coupled.

[0044] Chip 12 includes a contact pad 22h having a voltage Q4-P applied thereto by chip 12. The pad 22h is coupled to the end of pin 14h via a resistor 18h and an inductor 16h (in other words, via a metal branch). Therefore, pin 14h delivers voltage Q4 at a node of circuitry external to the chip to which it is electrically coupled.

[0045] Output voltages Q1, Q2, Q3, and Q4 correspond to binary values, for example. For instance, output voltages Q1, Q2, Q3, and Q4 correspond to data read from the memory of chip 12. For example, device 10 operates using a parallel protocol, meaning different outputs can simultaneously output different data.

[0046] Chip 12 includes input buffer amplifiers or input buffers 24a and 24d coupled to input pads 22a and 22d. Chip 12 also includes output buffer amplifiers or output buffers 24e to 24h coupled to output pads 22e to 22h. Figure 1In this example, chip 10 therefore includes six buffers 24a, 24d, 24e, 24f, 24g, and 24h. Chip 12 also includes circuitry represented by block 26, which has various functions. For example, block 26 includes logic circuitry. For example, circuitry 26 includes memory. For example, circuitry 26 includes data processing circuitry.

[0047] Pads 22a and 22d to 22h are coupled to circuit 26 via buffers 24a and 24d to 24h. In other words, the input terminal of buffer 24a is coupled (preferably connected) to pad 22a, and the output terminal of buffer 24a is coupled (preferably connected) to circuit 26. The input terminal of buffer 24d is coupled (preferably connected) to pad 22d, and the output terminal of buffer 24d is coupled (preferably connected) to circuit 26. The output terminal of buffer 24e is coupled (preferably connected) to pad 22e, and the input terminal or data input of buffer 24e is coupled (preferably connected) to circuit 26. The output terminal of buffer 24f is coupled (preferably connected) to pad 22f, and the input terminal of buffer 24f is coupled (preferably connected) to circuit 26. The output terminal of buffer 24g is coupled (preferably connected) to pad 22g, and the input terminal of buffer 24g is coupled (preferably connected) to circuit 26. The output terminal of buffer 24h is coupled (preferably connected) to pad 22h, and the input terminal of buffer 24h is coupled (preferably connected) to circuit 26. Pads 22b and 22c are preferably not coupled to circuit 26 through the buffer; for example, pads 22b and 22c are connected to circuit 26.

[0048] Voltage SN1 is applied to the output of buffer 24a. Therefore, voltage SN1 is the voltage supplied to circuit 26. Voltage GND1 is supplied to circuit 26. Voltage VDD1 is supplied to circuit 26. Voltage CLK1 is applied to the output of buffer 24d. Therefore, voltage CLK1 is the voltage supplied to circuit 26.

[0049] Output buffers 24e, 24f, 24g, and 24h each include an input having a clock signal (preferably a voltage) CLK1 delivered thereon. For example, all inputs are coupled (preferably connected) to the output of buffer 24d. Therefore, at each edge of the same type, for example, at each falling edge of the clock signal CLK1, the binary values ​​on pads 22e, 22f, 22g, and 22h can be changed. In the absence of a clock signal edge or a clock edge, the binary values ​​on pads 22e, 22f, 22g, and 22h are not modified.

[0050] Figure 2 The diagram shows... Figure 1 The operation. Figure 2The timing diagram includes: Curve 30 illustrates the voltage Q4-P on one of the output pads (e.g., pad 22h) in output pad 22; Curve 32 illustrates the voltage Q4 at the end of the pin corresponding to the pad (e.g., pin 14h); Curve 34 illustrates the voltage at end 20c, i.e., the power supply voltage VDD; Curve 36 illustrates the voltage VDD-P on pad 22c, which is approximately equal to voltage VDD1 based on voltage GND; Curve 38 illustrates the voltage at end 20b, i.e., the reference voltage GND; and Curve 40 illustrates the voltage on pad 22b, which is approximately equal to voltage GND based on voltage GND. ND1 voltage GND-P; Curve 42 illustrates the voltage at end 20d, i.e., the clock signal CLK based on voltage GND; Curve 44 illustrates the voltage at pad 22d, i.e., the clock signal CLK-P based on voltage GND; Curve 46 illustrates the clock signal CLK based on reference voltage GND, i.e., the difference between curves 42 and 38; Curve 48 illustrates the clock signal CLK-P based on reference voltage GND-P, i.e., the difference between curves 44 and 40; Curve 50 illustrates the voltage SN based on reference voltage GND; Curve 48 illustrates the voltage SN-P based on voltage GND-P.

[0051] Figure 2 The diagram illustrates the falling and rising edges of the clock signal CLK. Therefore, curves 42 and 46 drop from a high value to a low value at time t00, and rise from a low value to a high value at time t01, which follows t00. The voltage SN remains low, indicating memory operation.

[0052] Following the falling edge, the binary output value, represented by curves 30 and 32, rises from a low value to a high value. More precisely, Figure 1 A capacitive element (e.g., a parasitic capacitive element coupled to the end 20 of the pin under consideration) is then charged to maintain a high value. The capacitive element charges as the binary value rises from a low value to a high value, and discharges as the binary value falls from a high value to a low value. Therefore, current flows through the resistor 16 and inductor 18 of the pin with each change in the binary value. The rapid transition from zero current to high absolute current in the component generates significant noise. In particular, this noise causes significant variations in the input pads 22a, 22b, 22c, and 22d, which are connected via… Figure 1 Parasitic capacitive elements, not shown, are coupled.

[0053] Therefore, it can be observed that voltages SN-P, CLK-P, VDD-P, and GND-P do not correspond to voltages SN, CLK, VDD, and GND. Consequently, voltages SN1, GND1, VDD1, and CLK1 obtained at the output of the input buffer exhibit the same changes. At the time t2 when the binary value on the output pad switches (i.e., when curve 32 increases to a high value), voltages SN-P, CLK-P, VDD-P, and GND-P change. Specifically, voltages GND-P and VDD-P decrease.

[0054] Voltages GND-P and VDD-P change by essentially the same amount. Therefore, the supply voltage received by circuit 26 (i.e., the difference between voltages GND-P and VDD-P) does not change significantly. However, the clock signal (curve 48, i.e., the difference between voltages CLK1 and GND1) visible through chip 26 and used by output buffers 24e, 24f, 24g, and 24h changes significantly relative to the supplied clock signal CLK.

[0055] At time t3 (after time t2 and before time t1), the value of voltage CLK-P is greater than the value of voltage CLK, and the value of voltage GND-P is less than the value of voltage GND. Therefore, the clock signal (curve 48) visible through chip 26 and used by output buffers 24e, 24f, 24g, and 24h has a value greater than the low value of clock signal CLK. This difference can have a value greater than the high value of clock signal CLK. Therefore, circuit 26 and the output buffers receive rising and falling edges of the clock signal that should not be present. Rising and falling edges can cause changes in the output value, which may then result in an erroneous output value.

[0056] Figure 3 An embodiment of a synchronous electronic device 54 is shown. Device 54 is, for example, a memory or a device including a memory. Device 54 is, for example, a sequential access memory. Device 54 is, for example, a synchronous memory.

[0057] Device 54 includes elements of device 10. In other words, device 54 includes a chip 12 and pins 14 as previously described. More precisely, device 54 includes circuitry 26, buffers 24a and 24d to 24h, and pads 22a to 22h in chip 12, and resistors 18a to 18h, inductors 16a to 16h, and terminals 20a to 20h in pins 14a to 14h. Voltages SN, GND, VDD, CLK, Q1, Q2, Q3, and Q4 are applied to terminals 20a to 20h, respectively. Similarly, voltages SN-P, GND-P, VDD-P, CLK-P, Q1-P, Q2-P, Q3-P, and Q4-P are present on pads 22a to 22h, respectively. Input buffers 24a and 24d provide signals SN1 and CLK1 at their outputs.

[0058] Input buffers 24a and 24d are, for example, Schmitt trigger buffers. In other words, the input buffers include, for example, Schmitt inverters. Input buffers (i.e., Figure 3 Buffers 24a and 24d are configured to maintain the output value at the start time of duration T at their output for each period of clock signal CLK, regardless of the value on the pad 22 coupled to the buffer. Duration T is shorter than the period of the clock signal. Duration T is preferably shorter than half the period of the clock signal. Duration T occurs after each edge of the edge type on which the output buffers 24e to 24h are synchronized. In other words, if the output buffers 24e to 24h are synchronized on a falling edge (i.e., when the clock signal has a low value), duration T is between each falling edge and the next rising edge. If the output buffers 24e to 24h are synchronized on a rising edge (i.e., when the clock signal CLK has a high value), duration T is between each rising edge and the next falling edge.

[0059] For input buffers 24a and 24d, the duration T is preferably the same. In other words, the length of duration T is the same for each input buffer. Furthermore, duration T occurs at the same time for all input buffers.

[0060] For example, input buffers 24a and 24d each include a control input configured to receive a voltage F representing a duration T. The voltage F is, for example, a binary value. For instance, the voltage F takes a high value for duration T and a low value outside of duration T. Therefore, when one of the input buffers receives a voltage F with a high value, the value of the input buffer's output is maintained at its value during the rising edge of voltage F.

[0061] Device 54, preferably chip 12, includes circuit 56 for generating voltage F. Circuit 56 includes an input coupled (preferably connected) to the output of buffer 24d, i.e., the buffer provides a clock signal CLK1 to the buffer of circuit 26. Therefore, circuit 56 receives the clock signal CLK1 as an input. Circuit 56 outputs voltage F.

[0062] exist Figure 3 In the example, chip 12 includes a single circuit 56. Circuit 56 then provides the same voltage F to all input buffers. Preferably, each input buffer 24a and 24d includes a control input coupled (preferably connected) to the output of circuit 56.

[0063] Device 54 also includes a logic gate (&) 57. Logic gate 57 receives complementary values ​​of signal F and signal SN1 as inputs. Logic gate 57 provides a signal for controlling buffer 24a. In other words, logic gate 57 includes an input coupled (preferably connected) to the output of circuit 56, the output of which has the signal F generated thereon. Logic gate 57 includes another inverting input coupled (preferably connected) to the output of buffer 24a. Logic gate 57 includes an output coupled (preferably connected) to a control input of buffer 24a.

[0064] An example of circuit 56 will combine Figure 5 and Figure 6 To provide a more detailed description.

[0065] Figure 4 The diagram shows... Figure 3 The operation of the embodiment. Figure 4 Including comparison Figure 1 Equipment 10 and Figure 3 Timing diagrams of multiple voltages in device 54. More precisely, Figure 4The timing diagram includes: Curve 60 illustrates the voltage CLK based on voltage GND-P; Curve 61 illustrates the voltage CLK-P of circuit 10 based on voltage GND; Curve 62 illustrates the voltage VDD-P of circuit 10 based on voltage GND, which is substantially equal to voltage VDD1; Curve 63 illustrates the voltage GND-P of circuit 10 based on voltage GND, which is substantially equal to voltage GND1; Curve 64 illustrates the voltage CLK1 of circuit 10 based on voltage GND-P, which is obtained at the output of buffer 24d and delivered to output buffers 24e to 24h; Curve 67 illustrates the voltage SN1 of circuit 10 based on voltage GND-P, obtained at the output of buffer 24a; and Curve 68 illustrates the output voltage on pad 22, for example, the voltage of circuit 10 based on voltage GND-P. Q1-P; Curve 70 illustrates the voltage F of circuit 54; Curve 71 illustrates the voltage CLK-P of circuit 54 based on voltage GND-P; Curve 72 illustrates the voltage VDD-P of circuit 54 based on voltage GND and substantially equal to voltage VDD1; Curve 73 illustrates the voltage GND-P of circuit 54 based on voltage GND and substantially equal to voltage GND1; Curve 74 illustrates the voltage CLK1 of circuit 54 based on voltage GND-P, which is obtained at the output of buffer 24d and delivered to output buffers 24e to 24h; Curve 77 illustrates the voltage SN1 of circuit 54 based on voltage GND-P, obtained at the output of buffer 24a; and Curve 78 illustrates the output voltage on pad 22, for example, the voltage Q1-P of circuit 54 based on voltage GND-P.

[0066] Figure 4 The diagram illustrates the falling and rising edges of the voltage CLK (i.e., curve 60). Therefore, Figure 4 The diagram illustrates the transition from a high value to a low value of voltage CLK at time t0. Figure 4 The diagram further illustrates half a cycle of the voltage CLK between time t0 and time t1 after time t0, during which the voltage CLK has a low value. Figure 4 The diagram also illustrates the transition of voltage CLK from a low value to a high value at time t1.

[0067] exist Figure 1In the case of device 10, at time t2 between times t0 and t1, the voltage CLK1 (curve 64) delivered to the output buffer drops from a high value to a low value. In this example, the output value provided by circuit 26 at the input of buffer 24e has already risen from a low value to a high value before time t2. Therefore, the falling edge of voltage CLK1 causes voltage Q1-P to rise from a low value to a high value at time t3.

[0068] As previously mentioned Figure 2 As described, a change in the current value at the output pin (e.g., pin 14e) allows for a change in the output value, causing variations in voltages CLK-P (curve 61), VDD-P (curve 62), and GND-P (curve 63). Therefore, it can be observed that voltages CLK-P, VDD-P, and GND-P change from time t2 to time t4, between time t3 and time t5. Specifically, between time t4 and time t5, after time t3, voltages VDD-P and GND-P decrease and then increase to restore their original values.

[0069] Therefore, as mentioned earlier, the voltage CLK-P (curve 61), based on voltage GND-P, varies, specifically, between times t4 and t5, during which time voltage CLK-P can take a value greater than the high value of the clock signal. Thus, between time t6 after time t4 and time t7 after time t5, the clock signal CLK1 (curve 64) delivered to buffer 24e takes a high value, caused by the high value of voltage CLK-P between times t4 and t5.

[0070] Therefore, buffer 24e receives the falling edge of a clock signal that it should not be receiving. Figure 4 In the example, the voltage value at the data input of buffer 24e is changed between time t0 and time t7. Therefore, the falling edge of curve 64 at time t7 causes a change in the value of the output voltage Q1-P. Indeed, it can be observed that at time t8 after time t7, the voltage Q1-P begins to decrease to reach a low value, instead of continuing to increase to reach a high value. Therefore, the value provided by pin 14e is a low value instead of a high value. Thus, the data delivered by pin 14e is incorrect.

[0071] The change in the output value at time t8 (i.e., the change in the current value at pin 14e) causes changes in voltages CLK-P (curve 61), VDD-P (curve 62), and GND-P (curve 63) between times t4 and t5. In this case, the changes occur in opposite directions. Therefore, from time t7 onwards at time t11, voltage CLK-P takes a lower value than its lower value, while voltages VDD-P and GND-P take higher values ​​than their higher values.

[0072] Similarly, the voltage SN-P, referenced to voltage GND-P (not shown), varies and can take a value greater than the high value of voltage SN. Therefore, between time t9 after time t4 and time t10 after time t5, the voltage SN1 (curve 67) supplied to circuit 26 takes a high value, which is caused by the high value of voltage CLK-P between time t4 and t5.

[0073] In the case of device 54, as in the case of device 10, the voltage CLK-P (curve 74) supplied to the output buffer drops from a high value to a low value at time t2. In this example, the output value provided by circuit 26 at the input of buffer 24e has already risen from a low value to a high value before time t2. Therefore, the falling edge of the voltage CLK1 (curve 74) delivered to buffer 24e causes an increase in voltage Q1-P (curve 78) at time t3, so that it rises from a low value to a high value.

[0074] As previously mentioned Figure 2 As described, the change in the current value at pin 14e allows for a change in the output value Q1-P, causing variations in voltages CLK-P (curve 71), VDD-P (curve 72), and GND-P (curve 73). Therefore, as in the case of device 10, changes in voltages CLK-P, VDD-P, and GND-P can be observed from time t4. Specifically, between time t4 and time t5, following time t3, voltages VDD-P and GND-P decrease and then increase to restore their original values.

[0075] Therefore, as mentioned earlier, the voltage CLK-P (curve 61) with reference to voltage GND-P varies, specifically between time t4 and t5, at which time voltage CLK-P can take a value greater than the high value of the clock signal.

[0076] The falling edge at time t2 also causes voltage F (curve 70) to rise from a low value to a high value. Voltage F remains high for a duration T. During this duration T, i.e., as long as voltage F is high, the outputs of input buffers 24a to 24d do not change value. Therefore, as long as voltage F is high, voltages CLK1 (curve 74) and SN1 (curve 77) remain low. More precisely, voltages CLK1 (curve 74) and SN1 (curve 77) do not exhibit a transition to a high value between times t6 and t7, and between times t9 and t10, respectively, a transition that exists in the case of device 10. The absence of a falling edge at time t7 ensures that the output value Q1-P remains at the correct value.

[0077] Figure 5 It shows Figure 3 This is part of an embodiment. More precisely, Figure 5 It shows Figure 3 The implementation mode of circuit 56.

[0078] Circuit 56 includes an input node 80 and an output node 82. Input node 80 is coupled (preferably connected) to the output of buffer 24d. The output node is coupled (preferably connected) to the input of at least one input buffer 24a to 24d, preferably coupled (preferably connected) to the input of each input buffer 24a to 24d. A voltage F is provided to output node 82.

[0079] Circuit 56 includes an inverter circuit 84. Circuit 84 is configured to introduce a delay equal to a duration T. Circuit 84 includes an input coupled (preferably connected) to node 80. Preferably, circuit 84 is configured such that the value of the delay introduced by circuit 84 is substantially constant during operation of circuit 56. Preferably, the value of the delay introduced by circuit 84 is independent of changes in supply voltage and temperature.

[0080] Circuit 56 includes a logic NOR gate 86. Gate 86 includes an input e1 coupled (preferably connected) to the output of circuit 84, and another input e2 coupled (preferably connected) to node 80. The output of gate 86 is coupled (preferably connected) to node 82. Preferably, gate 86 outputs a voltage F.

[0081] As a variant, gate 86 can be an XOR NOT gate.

[0082] Figure 6 The diagram shows... Figure 5 The operation of the circuit. Figure 6 The timing diagram includes a curve 88 illustrating the clock signal CLK1 of circuit 26 (i.e., the output voltage of buffer 24d) and a curve 90 illustrating the voltage F.

[0083] Figure 6 The diagram illustrates the falling edge of the clock signal CLK1. Before the falling edge, voltage CLK1 has a high value corresponding to a binary "1". Therefore, gate 86 of circuit 56 receives a "1" of voltage CLK1 at input e1 and a binary "0" provided by circuit 84 at input e2. Therefore, voltage F has a low value corresponding to a binary "0".

[0084] After the falling edge, voltage CLK1 takes a low value. Therefore, gate 86 receives a binary "0" on input e1, but continues to receive a binary "0" on input e2 for a duration T. During the duration T after the falling edge, voltage F therefore has a high value corresponding to a binary "1".

[0085] After a duration T, the output value of circuit 84 (i.e., the value on input e2) takes the binary value "1", and the voltage F therefore has a low value corresponding to the binary value "0".

[0086] Therefore, voltage F is set to instruct input buffers 24a to 24d to maintain their output values ​​at the levels prior to the start of duration T. Figure 6 In the example, the value is the binary value "1". In another embodiment, it could be a different value.

[0087] One advantage of the described embodiment is that noise generated by the switching of the output value does not affect the operation and output value of circuit 26.

[0088] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. Specifically, although in the different embodiments described, the output buffer is synchronized on the falling edge of its clock signal, the embodiments can be readily adapted to devices where the output buffer is synchronized on the rising edge. That is, the duration T is after each rising edge, i.e., between each rising edge and the next falling edge. That is, the circuitry used to generate the control voltages F, F1, F2 of the input buffer can be modified. For example, a NOR gate can be replaced by an AND gate.

[0089] Furthermore, the described device includes four outputs, namely four pins 14e to 14h with output values ​​generated thereon, and therefore includes four output buffers. More generally, the device according to the embodiment may include any number of outputs, i.e., at least one output. However, the embodiment is particularly advantageous for devices including multiple parallel outputs, because noise caused by changes in output values ​​is more significant at this point.

[0090] Similarly, the device according to the embodiments may include any number of inputs, i.e., any number of input pins 14 coupled to circuit 26 via buffers. In the described embodiments, as in conjunction with Figures 3 to 6 All input buffers described in buffers 24a to 24d are controlled by voltage F. More generally, some input buffers may not be controlled by voltage F.

[0091] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0092] Although the description has been detailed, it should be understood that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. In the various figures, the same elements are identified using the same reference numerals. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, as those skilled in the art will readily recognize from this disclosure that existing or future processes, machines, manufactures, compositions of matter, means, methods, or steps can perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

[0093] Therefore, the specification and drawings are to be regarded only as a description of this disclosure as defined by the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents that fall within the scope of this disclosure.

Claims

1. An electronic device, comprising: The first input is configured to receive a clock signal; A first input buffer has a data input, a control input, and a data output, the data input being coupled to the first input, and the control input being configured to receive a first control signal instructing the first input buffer to maintain a constant value of a first output voltage at the data output of the first input buffer for a first duration following each edge of the clock signal, the first duration being a portion of one cycle of the clock signal; A first circuit has a clock input coupled to the data output of a first input buffer, and the first circuit is configured to receive the first output voltage. as well as A first output buffer has a first input coupled to the output of the first circuit and a second input coupled to the data output of the first input buffer, wherein a second output voltage at the first output buffer changes based on the first output voltage and is synchronized on the first edge of the clock signal.

2. The electronic device according to claim 1, further comprising: The second input is configured to receive a power supply voltage and is coupled to the first circuit. as well as A third input is configured to receive a reference voltage and is coupled to the first circuit.

3. The electronic device of claim 2, further comprising a fourth input configured to receive an authorized voltage, the fourth input being coupled to the first circuit via a second input buffer having a data input and a control input, the control input being configured to receive a second control signal.

4. The electronic device of claim 3, wherein both the first control signal and the second control signal have a first value during the first duration and a second value during the remaining duration of the clock signal.

5. The electronic device of claim 4, further comprising a second circuit, the input of the second circuit being coupled to the data output of the first input buffer, the second circuit being configured to generate the first control signal and the second control signal.

6. The electronic device of claim 5, wherein the second circuit includes a delay circuit configured to generate a delay equal to the first duration.

7. The electronic device of claim 6, wherein the second circuit includes a logic gate having a first input and a second input, the first input being coupled to the data output of the first input buffer, the second input being coupled to the data output of the first input buffer via the delay circuit, the logic gate being an AND gate in response to synchronization of the first output buffer on a rising edge, or a NOR gate in response to synchronization of the first output buffer on a falling edge.

8. The electronic device of claim 5, further comprising an AND gate, the output of which is coupled to the control input of the second input buffer, the AND gate being configured to: Receive the first control signal at the first input; and The output signal of the second input buffer is received at the second input.

9. The electronic device of claim 1, further comprising a memory storage device configured to have a binary value output.

10. The electronic device of claim 1, further comprising a plurality of outputs, each output being synchronized on the same clock signal and configured to deliver different binary values.

11. The electronic device of claim 1, wherein the value of the first duration is less than half the period of the clock signal.

12. A method for controlling an electronic device, the method comprising: The electronic device receives a clock signal via a first input, which is coupled to a first circuit via a first input buffer. Based on the control signal received by the first input buffer, a constant output voltage of the first input buffer is maintained for a first duration after each edge of the clock signal, the first duration being a part of one cycle of the clock signal; as well as The first output of the electronic device is synchronized on the first edge of the clock signal, and the first output is coupled to the first circuit via a first output buffer.

13. The method of claim 12, further comprising: The electronic device receives a power supply voltage through a second input, which is coupled to the first circuit. A reference voltage is received through a third input of the electronic device, which is coupled to the first circuit; as well as The authorized voltage is received through a fourth input of the electronic device, which is coupled to the first circuit via a second input buffer.

14. The method of claim 13, wherein each of the first input buffer and the second input buffer includes a control input, the method further comprising: A corresponding control signal is received through each of the first and second input buffers, the corresponding control signal having a first value during the first duration and a second value during the remaining duration of the clock signal.

15. The method of claim 14, further comprising generating the corresponding control signal via a second circuit having an input coupled to the output of the first input buffer, the second circuit including a delay circuit configured to generate a delay equal to the first duration.

16. The method of claim 15, wherein the second circuit comprises a logic gate having a first input and a second input, the first input being coupled to the output of the first input buffer, the second input being coupled to the output of the first input buffer via the delay circuit, the logic gate being an AND gate in response to synchronization of the first output buffer on a rising edge, or a NOR gate in response to synchronization of the first output buffer on a falling edge.

17. An electronic device comprising: The first input is configured to receive a clock signal; A first input buffer, coupled to the first input, the first input buffer including a data input coupled to the first input and a control input, the first input buffer being configured to maintain a constant output voltage of the first input buffer for a first duration after each edge of the clock signal based on the value of a control signal at the control input, regardless of the value at the data input, the first duration being less than half the period of the clock signal; A first circuit, wherein the first input is coupled to the first circuit via the first input buffer; Multiple outputs, each configured to be synchronized on a first edge of the clock signal, and each output coupled to the first circuit via a first output buffer; The second input is configured to receive a power supply voltage and is coupled to the first circuit. as well as A third input is configured to receive a reference voltage and is coupled to the first circuit.

18. The electronic device of claim 17, further comprising a fourth input configured to receive an authorized voltage, the fourth input being coupled to the first circuit via a second input buffer having a data input and a control input.

19. The electronic device of claim 18, wherein each of the first input buffer and the second input buffer is configured to receive a corresponding control signal having a first value during the first duration and a second value during the remaining duration of the clock signal.

20. The electronic device of claim 19, further comprising a second circuit coupled to the output of the first input buffer, the second circuit being configured to generate a control signal for the first input buffer, the second circuit comprising: The delay circuit is configured to generate a delay equal to the first duration; as well as A logic gate having a first input and a second input, the first input being coupled to the output of a first input buffer, and the second input having the output being coupled to the first input buffer via the delay circuit, the logic gate being an AND gate in response to the first output buffer being synchronized on a rising edge, or an NOR gate in response to the first output buffer being synchronized on a falling edge.

Images