A method and apparatus for multi-frequency asynchronous clock domain data processing

Abstract

This application provides a multi-frequency asynchronous clock domain data processing method and apparatus. The multi-frequency asynchronous clock domain data processing method is applied to a programmable logic device (PLD) connected to a processor. The method includes: in response to receiving a first clock, dividing the first clock to generate a second clock; receiving command data and test data based on the second clock; selecting a fourth clock generated based on the first clock or a third clock of the processor as the output master clock according to the command data; and outputting the test data to the processor according to the output master clock. The multi-frequency asynchronous clock domain data processing method and apparatus provided in this application achieve clock domain conversion between multiple different clocks by outputting multiple output master clocks with different frequencies, and also realize data conversion and transmission between the PLD and the processor at different rates.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to a multi-frequency asynchronous clock domain data processing method and apparatus. Background Technology

[0002] In recent years, with the continuous advancement of China's new infrastructure construction, single ARM processors have become increasingly inadequate for the functional requirements of industrial environments. This is particularly true in industries such as energy and power, industrial control, and smart healthcare, which typically require processor platforms based on an ARM+programmable device (FPGA or CPLD) architecture to implement specific functions, such as multi-channel / high-speed AD acquisition, multi-channel Ethernet ports, multi-channel serial ports, multi-channel / high-speed parallel DI / DO, and high-speed parallel data processing. Furthermore, the demands on programmable logic devices and ARM processors to achieve data transmission at different rates have become very high. For example, to verify the processing capabilities of algorithms implemented by an ARM processor, programmable devices need to send test data to the ARM processor at different rates via interfaces (SPI, UART, etc.), thus verifying the algorithm's logical functionality and processing speed.

[0003] In conceiving and implementing this application, the inventors discovered at least the following problems: Existing FPGA-based devices for converting and transmitting data across different clock domains can only achieve a limited number of data conversions and transmissions across different clock domains, and suffer from frequent FPGA software version iterations and poor FPGA software program portability; Existing CPLD-based devices for converting and transmitting data across different clock domains cannot achieve data clock domain conversion and transmission at frequencies higher than the main clock frequency because the CPLD lacks internal clock resources (PLL, which can divide and multiply the main clock).

[0004] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the Invention

[0005] To alleviate the above problems, this application provides a multi-frequency asynchronous clock domain data processing method and apparatus.

[0006] In one aspect, this application provides a multi-frequency asynchronous clock domain data processing method, specifically applied to a programmable logic device connected to a processor, the method comprising:

[0007] In response to receiving the first clock, the first clock is divided to generate a second clock;

[0008] Command data and test data are received based on the second clock;

[0009] Based on the command data, select either the fourth clock generated based on the first clock or the third clock of the processor as the output master clock;

[0010] The test data is output to the processor according to the output master clock.

[0011] Optionally, the multi-frequency asynchronous clock domain data processing method includes the following steps in executing the step of receiving command data and test data based on the second clock:

[0012] The second clock is divided to obtain the receiving clock;

[0013] The test data is received and stored according to the receiving clock.

[0014] Optionally, the command data includes a clock chip select signal and a clock parameter signal; the multi-frequency asynchronous clock domain data processing method, in executing the step of selecting a fourth clock generated based on the first clock or a third clock of the processor as the output master clock according to the command data, includes:

[0015] Based on the clock parameter signal, the first clock is divided or multiplied to generate a fourth clock;

[0016] Based on the clock chip select signal, either the fourth clock or the processor's third clock is selected as the output master clock.

[0017] Optionally, the multi-frequency asynchronous clock domain data processing method includes the following steps in performing the step of outputting the test data to the processor according to the output master clock:

[0018] In response to configuring the processor as a master device and the programmable logic device as a slave device, the test data is read based on the output master clock, and the test data is sent to the processor based on the output master clock.

[0019] On the other hand, this application also provides a multi-frequency asynchronous clock domain data processing device, specifically, including a programmable logic device, a processor and a clock generation chip connected to the programmable logic device, wherein the programmable logic device includes a clock divider module, a serial port module, a clock selector, a data memory and a data transmission module;

[0020] The clock divider module receives a first clock and divides the first clock to generate a second clock.

[0021] The serial port module is connected to the clock divider module and receives command data and test data based on the second clock.

[0022] The clock generating chip receives the first clock and generates a fourth clock based on the first clock;

[0023] The clock selector is connected to the processor, the serial port module and the clock generation chip respectively, and is used to select the fourth clock or the third clock of the processor as the main output clock according to the command data.

[0024] The data storage is connected to the serial port module, the clock selector and the data transmission module respectively. The data storage reads the test data based on the output master clock and outputs it to the data transmission module.

[0025] The data transmission module is connected to the clock selector and the data memory respectively, and is used to output the test data to the processor according to the output master clock.

[0026] Optionally, the programmable logic device in the multi-frequency asynchronous clock domain data processing device further includes a clock configuration module, which is connected to the serial port module, the clock generation chip, and the clock divider module respectively.

[0027] The command data includes clock parameters and clock chip select;

[0028] The clock configuration module receives clock parameters sent by the serial port module to configure the clock generation chip to generate the fourth clock based on the second clock.

[0029] The clock selector is connected to the clock generating chip, the serial port module, and the processor respectively, so as to select the fourth clock or the third clock of the processor as the output master clock according to the clock chip select sent by the serial port module.

[0030] Optionally, the clock generation chip in the multi-frequency asynchronous clock domain data processing device is connected between the clock configuration module and the clock selector;

[0031] The clock configuration module configures the clock generation chip to divide or multiply the first clock to generate the fourth clock.

[0032] The clock generation chip sends the fourth clock to the clock selector.

[0033] Optionally, the multi-frequency asynchronous clock domain data processing device uses a clock crystal oscillator to output the first clock to the clock divider module and the clock generation chip.

[0034] Optionally, the multi-frequency asynchronous clock domain data processing device is connected to a host computer, and the serial port module receives test data and command data sent by the host computer based on the second clock.

[0035] As described above, the multi-frequency asynchronous clock domain data processing method and apparatus provided in this application realize clock domain conversion of multiple different clocks by outputting multiple different frequency output master clocks, and also realize data conversion and transmission between programmable logic devices and processors at different rates. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0037] Figure 1 This is a flowchart of a multi-frequency asynchronous clock domain data processing method according to an embodiment of this application.

[0038] Figure 2 This is a structural diagram of a multi-frequency asynchronous clock domain data processing apparatus according to an embodiment of this application.

[0039] Figure 3 This is a structural diagram of a processor according to an embodiment of this application.

[0040] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0041] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0042] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0043] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0044] First Embodiment

[0045] On one hand, this application provides a multi-frequency asynchronous clock domain data processing method. Figure 1 This is a flowchart of a multi-frequency asynchronous clock domain data processing method according to an embodiment of this application.

[0046] Please see Figure 1 In one embodiment, the multi-frequency asynchronous clock domain data processing method is applied to a programmable logic device, which is connected to a processor.

[0047] Alternatively, the programmable logic device may be a field-programmable gate array (FPGA) or a complex programmable logic device (CPLD). The processor may be an ARM (Advanced RISC Machine) processor.

[0048] Multi-frequency asynchronous clock domain data processing methods include:

[0049] S10: In response to receiving the first clock, divide the first clock to generate a second clock.

[0050] For example, the frequency of the first clock can be 10MHz, and the first clock is divided to generate a second clock, the frequency of which can be a fixed logic master clock of 2.5MHz.

[0051] S20: Receive command data and test data based on the second clock.

[0052] For example, a second clock is used as the logic master clock to receive command data and test data sent by the host computer software. The test data serves as input stimulus to the processor algorithm module to verify the correctness of the algorithm function.

[0053] S30: Based on the command data, select the fourth clock generated based on the first clock or the third clock of the processor as the output master clock.

[0054] For example, the clock generation chip generates a fourth clock based on the first clock, and the programmable logic device selects the output master clock that needs to be tested and verified according to the command data.

[0055] S40: Outputs test data to the processor based on the output master clock.

[0056] In this embodiment, the multi-frequency asynchronous clock domain data processing method outputs multiple master clocks with different frequencies and can conveniently select a third clock or a fourth clock output by the clock generation chip for data transmission. This enables clock domain conversion between multiple different clocks and also enables data conversion and transmission between programmable logic devices and processors at different rates.

[0057] In one embodiment, the multi-frequency asynchronous clock domain data processing method includes the following steps in performing S20: receiving command data and test data based on a second clock:

[0058] S21: Divide the second clock to obtain the receiving clock.

[0059] For example, the host computer software uses the serial port interface and sets the baud rate to 115200bps to send data; the second clock is divided to generate a receiving clock with a baud rate of 115200bps to receive the data sent by the host computer software, so as to achieve consistent data transmission and reception rates.

[0060] S22: Receive and store test data according to the receiving clock.

[0061] For example, the multi-frequency asynchronous clock domain data processing method receives and stores test data based on the receiving clock generated by dividing the second clock frequency, so as to facilitate subsequent reading of the test data for algorithm verification.

[0062] In one embodiment, the command data includes a clock chip select signal and a clock parameter signal;

[0063] The multi-frequency asynchronous clock domain data processing method, in executing S30: selecting a fourth clock generated based on the first clock or a third clock of the processor as the output master clock according to the command data, includes the following steps:

[0064] S31: Based on the clock parameter signal, divide or multiply the first clock to generate the fourth clock.

[0065] For example, based on the second clock configuration clock parameter signal, the first clock is divided or multiplied according to the clock parameter signal to output a fourth clock with the corresponding clock frequency.

[0066] S32: Select the fourth clock or the processor's third clock as the output master clock based on the clock chip select signal.

[0067] Optionally, if the clock chip select signal is 0, the fourth clock is selected; if the clock chip select signal is 1, the processor's third clock is selected.

[0068] In one embodiment, the multi-frequency asynchronous clock domain data processing method includes the following steps in executing S40: outputting test data to the processor according to the output master clock:

[0069] S41: In response to configuring the processor as a master device, configuring the programmable logic device as a slave device, reading test data based on the output master clock, and sending test data to the processor based on the output master clock.

[0070] For example, the processor generates a third clock based on its rich internal peripheral interfaces, such as an Ethernet controller or an SPI controller. Once the processor is determined to be the master device, it can output a communication clock signal for the slave device to use as the master clock. After outputting the master clock, test data is fed into the processor according to the SPI interface timing for algorithm verification. This achieves data conversion and transmission between programmable logic devices and the processor across different clock domains, while maintaining good software portability.

[0071] Second Embodiment

[0072] On the other hand, this application also provides a multi-frequency asynchronous clock domain data processing apparatus. Figure 2 This is a structural diagram of a multi-frequency asynchronous clock domain data processing apparatus according to an embodiment of this application.

[0073] Please see Figure 2 In one embodiment, the multi-frequency asynchronous clock domain data processing device includes a programmable logic device 10, a processor 20 and a clock generation chip 30 connected to the programmable logic device 10. The programmable logic device 10 includes a clock divider module 11, a serial port module 12, a clock selector 13, a data memory 16 and a data transmission module 14.

[0074] Processor 20 can be an ARM processor, primarily responsible for implementing algorithms. For example, it receives test data sent by programmable logic device 10 to verify the correctness of the algorithm's function. Since algorithms can be of various types, such as image algorithms, it is necessary not only to verify the correctness of the algorithm's function but also to verify whether the algorithm can maintain its correctness when receiving test data at different rates. In other words, it is necessary to ensure not only the correctness of the logical function but also the strength of the algorithm's processing power or its processing performance.

[0075] The clock divider module 11 receives the first clock and divides the first clock to generate the second clock.

[0076] For example, the frequency of the first clock can be 10MHz, and the first clock is divided to generate a second clock CLK1, the frequency of which can be 2.5MHz.

[0077] The serial port module 12 is connected to the clock divider module 11 and receives command data and test data based on the second clock.

[0078] For example, the serial port module 12 uses a second clock as its master clock to receive test data UART_DATA and command data sent by the host computer software. The test data is sent to the processor 20 for processing, serving as input stimulus for the processor 20's algorithm module to verify the algorithm's correctness. The command data includes clock parameters and a clock chip select. The clock parameters configure the clock generation chip 30 to generate clocks of different frequencies, and the clock chip select is used by the clock selector 13 to select the clock input source.

[0079] The clock generation chip 30 receives the first clock and generates a fourth clock based on the first clock.

[0080] Optionally, the clock generation chip 30 is implemented using a hardware chip. The clock chip model can be AD9551. The AD9551 clock chip uses a fractional-N divider or multiplier PLL to accurately convert the reference frequency of the first clock into the required output frequency of the fourth clock, DDS_CLK. Understandably, this application does not limit the type of clock generation chip 30. Any DDS chip capable of outputting different clock frequencies and with accurate output can be used in the design, and is not limited to the AD9951 chip.

[0081] The clock selector 13 is connected to the processor 20, the serial port module 12 and the clock generation chip 30 respectively, and is used to select the fourth clock or the third clock of the processor 20 as the output master clock according to the command data.

[0082] For example, the command data is divided into clock parameters and clock chip select. The clock parameters are used to configure the clock generation chip 30 to generate a fourth clock, and the clock chip select is used to select the output master clock SPI_CLK.

[0083] The data storage 16 is connected to the serial port module 12, the clock selector 13 and the data transmission module 14 respectively. The data storage 16 reads the test data based on the output master clock and outputs it to the data transmission module 14.

[0084] For example, the serial port module 12 buffers the test data received and transmitted in the data storage 16, facilitating the subsequent reading of the test data DATA based on the output master clock and outputting it to the data transmission module 14. Optionally, the data storage 16 can be an asynchronous FIFO (First-In-First-Out) module. The test data sent by the host computer is written into the asynchronous FIFO module using the UART interface's receive clock UART_CLK, and the test data is read out from the asynchronous FIFO module using the output master clock SPI_CLK, thereby realizing the conversion of the test data from the serial port clock domain to the SPI clock domain.

[0085] The data transmission module 14 is connected to the clock selector 13 and the data memory 16 respectively, and is used to output test data to the processor 20 according to the output master clock.

[0086] For example, the data transmission module 14 can be an SPI transmission module, which uses the output master clock of different frequencies to send test data to the processor 20 according to the SPI interface timing, thereby realizing data communication between the programmable logic device 10 and the processor 20, while also having good software portability.

[0087] In this embodiment, the multi-frequency asynchronous clock domain data processing device realizes clock domain conversion of multiple different clocks by outputting multiple different frequency output master clocks, and also realizes data conversion and transmission between the programmable logic device 10 and the processor 20 at different rates.

[0088] Please continue reading. Figure 2 In one embodiment, the programmable logic device 10 in the multi-frequency asynchronous clock domain data processing device further includes a clock configuration module 15, which is connected to the serial port module 12, the clock generation chip 30 and the clock divider module 11 respectively.

[0089] For example, the clock divider module 11 divides the first clock to generate a second clock. The second clock is divided into two paths: one path provides a logical master clock for the serial port module 12, and the other path provides a logical master clock for the clock configuration module 15.

[0090] The clock configuration module 15 receives clock parameters sent by the serial port module 12 to configure the clock generation chip 30 to generate a fourth clock based on the second clock. The clock selector 13 is connected to the clock generation chip 30, the serial port module 12 and the processor 20 respectively, to select either the fourth clock or the third clock of the processor 20 as the output master clock according to the clock chip select CLK_SEL sent by the serial port module 12.

[0091] For example, a clock chip select is sent to a clock selector 13. If the clock chip select is 0, the clock selector 13 selects a fourth clock. If the clock chip select is 1, the clock selector 13 selects a third clock provided by the processor 20.

[0092] Figure 3 This is a structural diagram of a processor according to an embodiment of this application.

[0093] Please see Figure 3 For example, ARM processors have a rich set of internal peripheral interfaces, such as SPI controller 21 and Ethernet controller 22, which are not limited in this application. Processor 20 generates a third clock ARM_CLK based on the above interfaces.

[0094] Optionally, if the ARM processor is configured with the SPI controller 21 as a master device, then the programmable logic device 10 is a slave device. The SPI controller 21, as a master device, consists of three lines: a clock line (SPI_CLK), a chip select line (SPI_CSN), and a transmit data line (SPI_SDO). By setting different clock frequencies for the ARM processor's clock lines, the programmable logic device receives clock signals of different frequencies.

[0095] Optionally, if the ARM processor is configured with Ethernet controller 22 as the master device, then the programmable logic device 10 is the slave device. Since Ethernet controller 22 can be implemented using different Ethernet interfaces, taking the RGMII interface as an example, RGMII (Reduced Gigabit Media Independent Interface) is a type of Reduced GMII. RGMII uses a 4-bit data interface and supports transmission rates of 10M / 100M / 1000Mb / s, with corresponding clock signals of 2.5MHz / 25MHz / 125MHz respectively. The RGMII data structure conforms to the IEEE Ethernet standard; the interface definition can be found in IEEE 802.3-2000, and will not be elaborated here. As a master device, RGMII consists of three lines: a clock line (GTX_CLK), a control line (TX_CTL), and a transmit data line (TXD). By setting different clock frequencies for the ARM processor's clock lines, the programmable logic device receives clock signals of different frequencies.

[0096] It should be noted that for both the SPI controller 21 and the Ethernet controller 22, the ARM processor side acts as the master device. The programmable logic device 10 only needs the clock signal (SPI_CLK or GTX_CLK). Other signals (data lines, chip select lines, control lines) are not used. The programmable logic device 10 only needs to ignore them.

[0097] Please continue reading. Figure 2 In one embodiment, the clock generation chip 30 in the multi-frequency asynchronous clock domain data processing device is connected between the clock configuration module 15 and the clock selector 13.

[0098] The clock configuration module 15 configures the clock generation chip 30 to divide or multiply the first clock to generate a fourth clock, and the clock generation chip 30 sends the fourth clock to the clock selector 13.

[0099] For example, clock parameters are sent to clock configuration module 15, which receives the clock parameters and uses the SPI_BUS bus to configure clock generation chip 30 to output a fourth clock at a corresponding clock frequency. Different fourth clock frequencies result in different communication rates between programmable logic device 10 and processor 20, enabling data transmission between various clock frequencies.

[0100] Please continue reading. Figure 2 In one embodiment, the multi-frequency asynchronous clock domain data processing device uses a clock crystal to output a first clock to the clock divider module 11 and the clock generation chip 30.

[0101] For example, a clock crystal provides a clock source for the programmable logic device 10, and the first clock frequency can be 10MHz. The clock crystal provides a clock source for the clock generation chip 30, so that the clock generation chip 30 divides or multiplies the frequency according to the first clock.

[0102] Please continue reading. Figure 2 In one embodiment, the multi-frequency asynchronous clock domain data processing device is connected to a host computer, and the serial port module 12 receives test data and command data sent by the host computer based on a second clock.

[0103] For example, the host computer reads test data from the file, and the serial port module 12 uses the second clock frequency division to generate a receiving clock UART_CLK with a baud rate of 115200bps. Then, the host computer software sends the test data and command data to the serial port module 12 of the programmable logic device 10 through the UART bus of the UART interface at a baud rate of 115200bps.

[0104] As described above, the multi-frequency asynchronous clock domain data processing method and apparatus provided in this application control the DDS chip to output different clock frequencies through programmable logic devices, and utilize interfaces (SPI interface, MIPI interface, Ethernet interface, etc.) based on the ARM processor to output different clock frequencies, thereby realizing the conversion and transmission of data in different clock domains; this application uses an asynchronous FIFO to realize the conversion of different clock domains. Under the write clock, data is written to the FIFO, and under the read clock, data is read from the FIFO. The asynchronous FIFO is implemented using the hardware description language Verilog HDL, thereby realizing the asynchronous clock domain data conversion; this application changes the frequency of the interface transmission clock based on the interface's different rate transmission mechanism, thereby changing the interface data transmission rate.

[0105] It should be noted that step designations such as S10 and S20 are used in this application for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S20 first and then S10, etc., but these should all be within the protection scope of this application.

[0106] In the embodiments of the multi-frequency asynchronous clock domain data processing apparatus provided in this application, all the technical features of any of the above-described method embodiments may be included. The extended and explanatory content of the specification is basically the same as that of the embodiments of the above methods, and will not be repeated here.

[0107] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the computer to perform the methods described in the various possible implementations above.

[0108] This application also provides a chip, including a memory and a processor. The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device with the chip installed performs the methods described in the various possible implementations above.

[0109] It is understood that the above scenarios are merely examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of this application. The technical solutions of this application can also be applied to other scenarios. For example, as those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0110] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0111] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.

[0112] The units in the device of this application embodiment can be merged, divided, and deleted according to actual needs.

[0113] In this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions are generally described in detail only when they appear for the first time. When they appear again, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions that are not described in detail later can be referred to their previous relevant detailed descriptions.

[0114] In this application, the descriptions of the various embodiments have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0115] The technical features of the present application can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0116] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for processing multi-frequency asynchronous clock domain data, characterized in that, Applied to a programmable logic device connected to a processor, the method includes: In response to receiving the first clock, the first clock is divided to generate a second clock; Command data and test data are received based on the second clock; Based on the command data, a fourth clock generated by dividing or multiplying the first clock or the third clock of the processor is selected as the main output clock; The test data is output to the processor according to the output master clock.

2. The multi-frequency asynchronous clock domain data processing method as described in claim 1, characterized in that, The step of receiving command data and test data based on the second clock includes: The second clock is divided to obtain the receiving clock; The test data is received and stored according to the receiving clock.

3. The multi-frequency asynchronous clock domain data processing method as described in claim 1, characterized in that, The command data includes clock chip select signals and clock parameter signals; The step of selecting either a fourth clock generated based on the first clock or a third clock of the processor as the output master clock according to the command data includes: Based on the clock parameter signal, the first clock is divided or multiplied to generate a fourth clock; Based on the clock chip select signal, either the fourth clock or the processor's third clock is selected as the output master clock.

4. The multiple frequency asynchronous clock domain data processing method of any of claims 1-3, wherein, The step of outputting the test data to the processor according to the output master clock includes: In response to configuring the processor as a master device and the programmable logic device as a slave device, the test data is read based on the output master clock and the test data is sent to the processor based on the output master clock.

5. A multiple frequency asynchronous clock domain data processing apparatus, characterized by, It includes a programmable logic device, a processor and a clock generating chip connected to the programmable logic device, wherein the programmable logic device includes a clock divider module, a serial port module, a clock selector, a data memory and a data transmission module; The clock divider module receives a first clock and divides the first clock to generate a second clock. The serial port module is connected to the clock divider module and receives command data and test data based on the second clock. The clock generation chip receives the first clock and generates a fourth clock by dividing or multiplying the first clock. The clock selector is connected to the processor, the serial port module and the clock generation chip respectively, and is used to select the fourth clock or the third clock of the processor as the main output clock according to the command data. The data storage is connected to the serial port module, the clock selector and the data transmission module respectively. The data storage reads the test data based on the output master clock and outputs it to the data transmission module. The data transmission module is connected to the clock selector and the data memory respectively, and is used to output the test data to the processor according to the output master clock.

6. The multiple frequency asynchronous clock domain data processing apparatus of claim 5, wherein, The programmable logic device further includes a clock configuration module, which is connected to the serial port module, the clock generation chip and the clock divider module respectively. The command data includes clock parameters and clock chip select; The clock configuration module receives clock parameters sent by the serial port module to configure the clock generation chip to generate the fourth clock based on the second clock. The clock selector is connected to the clock generating chip, the serial port module, and the processor respectively, so as to select the fourth clock or the third clock of the processor as the output master clock according to the clock chip select sent by the serial port module.

7. The multiple frequency asynchronous clock domain data processing apparatus of claim 6, wherein, The clock generation chip is connected between the clock configuration module and the clock selector; The clock configuration module configures the clock generation chip to divide or multiply the first clock to generate the fourth clock. The clock generation chip sends the fourth clock to the clock selector.

8. The multiple frequency asynchronous clock domain data processing apparatus of claim 6, wherein, The first clock is output to the clock divider module and the clock generation chip using a clock crystal oscillator.

9. The multiple frequency asynchronous clock domain data processing apparatus of claim 6, wherein, The multi-frequency asynchronous clock domain data processing device is connected to the host computer, and the serial port module receives test data and command data sent by the host computer based on the second clock.

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