FPGA-based low-speed source synchronous data bit alignment correction method

Abstract

The embodiment of the application discloses a low-speed source synchronous data bit alignment correction method based on FPGA, which comprises the following steps: setting clock line delay order and data line delay order of a first channel; receiving an external input serial training sequence, and performing serial-parallel conversion to obtain parallel data; obtaining rising edges of the parallel data variation and calculating parallel data at the time of the following two data edge variations; adjusting total delay order to trigger first data edge jitter, recording total delay order d1 at the time of triggering the first data edge jitter; adjusting total delay order to trigger second data edge jitter, recording total delay order d2 at the time of triggering the second data edge jitter; calculating optimal total delay order D1 of the current channel, D1=(d1+d2) / 2; repeating the above steps to complete alignment correction of other three channels and obtaining corresponding optimal total delay orders; and adjusting clock line delay order and data line delay order of each channel according to the corresponding optimal total delay orders of each channel.

Description

Technical Field

[0001] This invention relates to the field of data transmission. More specifically, it relates to a low-speed source-synchronous data bit alignment correction method based on FPGA. Background Technology

[0002] Source-synchronous transmission is a data transmission method in which the transmitter simultaneously sends data and clock signals, and the receiver samples the data window at specific clock edges according to an agreed-upon timing. Because the signal transmission paths are inconsistent, the arrival times of the data signal line and the sampling clock line at the receiver cannot be synchronized. This causes a positional offset during sampling at the receiver, preventing accurate sampling at the center of the data window and potentially generating erroneous sampled data. Therefore, phase adjustment of the received data is necessary based on the actual situation. Summary of the Invention

[0003] The purpose of this invention is to provide a low-speed source-synchronous data bit alignment correction method based on FPGA, so as to solve at least one of the problems existing in related technologies.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] The first aspect of this invention provides a low-speed source-synchronous data bit alignment correction method based on FPGA, the method comprising:

[0006] S10: Set the clock line delay order and data line delay order of the first channel;

[0007] S20: Receives the serial training sequence from external input and performs serial-to-parallel conversion to obtain parallel data;

[0008] S30: Obtain the rising edge of the parallel data change and calculate the parallel data at the next two data edge changes;

[0009] S40: Adjust the total delay order to trigger the first data edge bounce, and record the total delay order d1 when the first data edge bounce is triggered;

[0010] Adjust the total delay order to trigger the second data edge bounce, and record the total delay order d2 when the second data edge bounce is triggered;

[0011] Calculate the optimal total delay order D1 for the current channel, D1 = (d1 + d2) / 2;

[0012] S50: Follow steps S10-S40 to complete the alignment correction of the second, third, and fourth channels and obtain the corresponding optimal total delay orders D2, D3, and D4;

[0013] S60: Adjust the current delay order and data line delay order of each channel according to the optimal total delay order corresponding to each channel to complete the bit alignment correction.

[0014] Optionally, adjusting the current latency order and data line latency order of each channel according to the optimal total latency order corresponding to each channel includes:

[0015] Find the minimum value D of the optimal total delay order for each channel. min Determine D min If the value is greater than 31, then set the clock line delay order of each channel to 0, and the data line delay order to its corresponding optimal delay order and minimum value D. min The difference; if it is less than, then set the clock line delay order of each channel to 62-D. min The data line latency order is its corresponding optimal latency order and minimum value D. min The difference.

[0016] Optionally, adjusting the total delay order includes: determining whether the current total delay order plus 1 is greater than 31; if it is greater than 31, then incrementing the data line delay order by 1 to complete one delay order adjustment; if it is less than or equal to 31, then decrementing the clock line delay order by 1 to complete one delay order adjustment.

[0017] Optionally, step S10 further includes: setting the clock line delay order of the first channel to 31; and setting the data line delay order of the first channel to 0.

[0018] Optionally, step S20 further includes: receiving an externally transmitted 8-bit serial training sequence 0000_1111;

[0019] The received 8-bit serial training sequence is converted from serial to parallel to obtain parallel data.

[0020] Optionally, step S30 further includes: performing a pairwise XOR operation on the parallel data; if there is a result of 1 after the XOR operation, then the rising edge of the parallel data is found, and the current parallel data dat0 containing the rising edge is recorded.

[0021] The least significant bit of the current parallel data dat0 containing a rising edge is used as the most significant bit of the parallel data result dat1 when the data edge changes for the first time. All bits of the current parallel data dat0 containing a rising edge are shifted right by 1 bit to obtain the remaining bits of the parallel data result dat1 when the data edge changes for the first time.

[0022] The least significant bit of the parallel data result dat1 at the first data edge change is taken as the most significant bit of the parallel data result dat2 at the second data edge change. All bits of the parallel data result dat1 at the first data edge change are shifted right by 1 bit to obtain the remaining bits of the parallel data result dat2 at the second data edge change.

[0023] Optionally, step S40 further includes:

[0024] S401: Adjust the total delay order until the serial-to-parallel conversion result is the same as dat1, then the first edge skipping is considered to have been triggered, and the current total delay order d1 is recorded;

[0025] S402: Adjust the total delay order until the serial-to-parallel conversion result is the same as dat2. This is considered to have triggered the second edge skipping. Record the current total delay order d2.

[0026] The beneficial effects of this invention are as follows:

[0027] The FPGA-based low-speed source-synchronous data bit alignment correction method provided in this embodiment does not require knowledge of the source-synchronous data rate. It can automatically calculate the optimal delay value and perform dynamic phase adjustment when the source-synchronous data rate is unknown. It also does not require modification of internal parameters in source-synchronous transmission application scenarios with multiple data rates, thus enhancing the system's versatility. Attached Figure Description

[0028] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0029] Figure 1 The flowchart illustrates a low-speed source-synchronous data bit alignment correction method based on FPGA according to an embodiment of this application.

[0030] Figure 2 This document illustrates a flowchart of an embodiment of the present application, showing the adjustment of clock line delay order and data line delay order for each channel.

[0031] Figure 3 A flowchart illustrating a single delay order adjustment proposed in one embodiment of this application is shown. Detailed Implementation

[0032] To more clearly illustrate the present invention, the following description, in conjunction with embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.

[0033] In related technologies, traditional dynamic phase adjustment schemes based on FPGAs (Programmable Logic Processors) include bit alignment correction and word alignment correction. Bit alignment correction adjusts the line delay of received data through the internal IDELAY (delay) hard core of the Xilinx FPGA, measuring the corresponding delay orders d1 and d2 when two data edge transitions occur. After completing the two measurements, the delay order is set to (d1+d2) / 2, at which point the center of the received data window is aligned with the sampling clock edge.

[0034] The inventors discovered that when using this method for measurement, it is necessary to ensure that the data signal can generate two edge jumps within the adjustable delay order range of the IDELAY hard core. Therefore, this method requires the data transmission rate of the input data to be higher than 400M for dual edges. Below this rate, the method cannot be used for correct bit alignment correction.

[0035] To lower the lower limit of data transmission rate, a bit alignment correction scheme is included in related technologies. This scheme performs bit alignment correction given the source synchronization data rate. First, the delay order p1 corresponding to one data change cycle is calculated. Then, only the delay value d1 corresponding to the data edge transition needs to be measured once. The optimal delay order is then d1 ± (p1 / 2), at which the center of the received data window is aligned with the sampling clock edge. This scheme can reduce the lower limit of data transmission rate from 400MHz to 203MHz. However, this method requires knowledge of the source synchronization data transmission rate, and the parameter p1 needs to be recalculated and set according to different transmission rates, making it less universally applicable.

[0036] To address at least one of the aforementioned problems and eliminate the need for data transmission rate requirements for bit alignment correction, this invention proposes a low-speed source-synchronous data bit alignment correction method based on FPGA. The bit alignment correction method of this invention is illustrated below through several specific embodiments.

[0037] One embodiment of the present invention provides a low-speed source-synchronous data bit alignment correction method based on FPGA.

[0038] like Figure 1 As shown, the method includes

[0039] S10: Set the clock line delay order and data line delay order of the first channel;

[0040] S20: Receives the serial training sequence from external input and performs serial-to-parallel conversion to obtain parallel data;

[0041] S30: Obtain the rising edge of the parallel data change and calculate the parallel data at the next two data edge changes;

[0042] S40: Adjust the total delay order to trigger the first data edge bounce, and record the total delay order d1 when the first data edge bounce is triggered;

[0043] Adjust the total delay order to trigger the second data edge bounce, and record the total delay order d2 when the second data edge bounce is triggered;

[0044] Calculate the optimal total delay order D1 for the current channel, D1 = (d1 + d2) / 2;

[0045] S50: Follow steps S10-S40 to complete the alignment correction of the second, third, and fourth channels and obtain the corresponding optimal total delay orders D2, D3, and D4;

[0046] S60: Adjust the clock line delay order and data line delay order of each channel according to the optimal total delay order corresponding to each channel to complete bit alignment correction.

[0047] This embodiment does not require knowledge of the source synchronization data rate. It can automatically calculate the optimal delay value and perform dynamic phase adjustment when the source synchronization data rate is unknown. Furthermore, it does not require modification of internal parameters in source synchronization transmission application scenarios with multiple data rates, thus having broad versatility.

[0048] Compared to traditional bit alignment correction methods, this embodiment simultaneously adjusts the clock signal line and the data signal line, expanding the maximum delay adjustment order to twice that of the traditional method, and correspondingly reducing the lower limit of the transmission rate from 400M for both edges to 203M for both edges.

[0049] In a specific embodiment, such as Figure 2 As shown, adjusting the clock line delay order and data line delay order of each channel according to the optimal total delay order corresponding to each channel includes:

[0050] Find the minimum value D of the optimal total delay order for each channel. min Determine D min If the value is greater than 31, then set the clock line delay order of each channel to 0, and the data line delay order to its corresponding optimal delay order and minimum value D. min The difference; if it is less than, then set the clock line delay order of each channel to 62-D. min The data line latency order is its corresponding optimal latency order and minimum value D. min The difference.

[0051] In a specific embodiment, the steps for adjusting the total delay order are as follows: Figure 3The process includes: determining whether the current total delay order plus 1 is greater than 31; if it is greater than 31, then incrementing the data line delay order by 1 to complete one delay order adjustment; if it is less than or equal to 31, then decrementing the clock line delay order by 1 to complete one delay order adjustment.

[0052] In one specific embodiment, step S10 further includes: setting the clock line delay order of the first channel to 31; and setting the data line delay order of the first channel to 0.

[0053] Step S20 further includes: receiving an externally transmitted 8-bit serial training sequence 0000_1111;

[0054] The received 8-bit serial training sequence is converted from serial to parallel to obtain parallel data.

[0055] Step S30 further includes: performing a pairwise XOR operation on the parallel data; if there is a result of 1 after the XOR operation, then the rising edge of the parallel data is found, and the current parallel data dat0 containing the rising edge is recorded.

[0056] The least significant bit of the current parallel data dat0 containing a rising edge is used as the most significant bit of the parallel data result dat1 when the data edge changes for the first time. All bits of the current parallel data dat0 containing a rising edge are shifted right by 1 bit to obtain the remaining bits of the parallel data result dat1 when the data edge changes for the first time. For example, if the data dat0 is 001_0001, the corresponding data dat1 is 010_0010.

[0057] The least significant bit of the parallel data result dat1 at the first data edge change is taken as the most significant bit of the parallel data result dat2 at the second data edge change. All bits of the parallel data result dat1 at the first data edge change are shifted right by 1 bit to take the remaining bits of the parallel data result dat2 at the second data edge change. For example, if dat1 is 010_0010, the corresponding dat2 is 100_0100.

[0058] Step S40 further includes:

[0059] S401: Adjust the total delay order until the serial-to-parallel conversion result is the same as dat1, then the first edge skipping is considered to have been triggered, and the current total delay order d1 is recorded;

[0060] Specifically, the total delay order is adjusted to trigger the first data edge skipping. This is done by gradually increasing the delay difference between the data line and the clock line by first decreasing the clock line delay order and then increasing the data line delay order. The adjustment range is 31 + 31 = 62.

[0061] The total delay order is adjusted by changing the delay order of both the data line and the clock line. Depending on the total delay order, different delay orders are adjusted for the data line or the clock line.

[0062] First, increment the total delay order by 1. Then, check the current total delay order. If the total delay order is less than or equal to 31, decrement the current clock line IDELAY delay order by 1. If it is greater than 31, increment the current data line IDELAY delay order by 1. If the serial-to-parallel conversion result is different from dat1, perform another delay order adjustment. If the serial-to-parallel conversion result is the same as dat1, it is considered that the first edge jump has been triggered, and the current total delay order d1 is recorded.

[0063] It should be noted that IDELAY can set the delay order from 0 to 31. Under the premise of a 200M reference clock, each additional order corresponds to an actual delay time of 78.125ps.

[0064] S402: Adjust the total delay order until the serial-to-parallel conversion result is the same as dat2. This is considered to have triggered the second edge skipping. Record the current total delay order d2.

[0065] Specifically, step S402 includes: first, incrementing the total delay order by 1; then, judging the current total delay order; if the total delay order is less than or equal to 31, decrementing the current clock line IDELAY delay order by 1; if it is greater than 31, incrementing the current data line IDELAY delay order by 1; if the serial-to-parallel conversion result is different from dat2, perform another delay order adjustment; if the serial-to-parallel conversion result is the same as dat2, it is considered that the second edge jump has been triggered, and the current total delay order d2 is recorded.

[0066] The FPGA used in this invention is a Xilinx Kintex-7 series FPGA. In practice, this invention also needs to be implemented on an FPGA with IDELAY hard core resources.

[0067] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A low-speed source-synchronous data bit alignment correction method based on FPGA, characterized in that, include: S10: Set the clock line delay order and data line delay order of the first channel; S20: Receives the serial training sequence from external input and performs serial-to-parallel conversion to obtain parallel data; S30: Obtain the rising edge of the parallel data change and calculate the parallel data at the next two data edge changes; S40: Adjust the total delay order to trigger the first data edge bounce, and record the total delay order d1 when the first data edge bounce is triggered; Adjust the total delay order to trigger the second data edge bounce, and record the total delay order d2 when the second data edge bounce is triggered; Calculate the optimal total delay order D1 for the current channel, D1 = (d1 + d2) / 2; S50: Follow steps S10-S40 to complete the alignment correction of the second, third, and fourth channels and obtain the corresponding optimal total delay orders D2, D3, and D4; S60: Adjust the clock line delay order and data line delay order of each channel according to the optimal total delay order corresponding to each channel to complete bit alignment correction; Adjusting the total delay order involves: determining whether the current total delay order plus 1 is greater than 31. If it is greater than 31, the data line delay order is incremented by 1 to complete one delay order adjustment; if it is less than or equal to 31, the clock line delay order is decremented by 1 to complete one delay order adjustment. Step S30 further includes: performing a pairwise XOR operation on the parallel data; if there is a result of 1 after the XOR operation, then the rising edge of the parallel data is found, and the current parallel data dat0 containing the rising edge is recorded. The least significant bit of the current parallel data dat0 containing a rising edge is used as the most significant bit of the parallel data result dat1 when the data edge changes for the first time. All bits of the current parallel data dat0 containing a rising edge are shifted right by 1 bit to obtain the remaining bits of the parallel data result dat1 when the data edge changes for the first time. The least significant bit of the parallel data result dat1 at the first data edge change is taken as the most significant bit of the parallel data result dat2 at the second data edge change. All bits of the parallel data result dat1 at the first data edge change are shifted right by 1 bit to obtain the remaining bits of the parallel data result dat2 at the second data edge change.

2. The bit alignment correction method according to claim 1, characterized in that, Step S10 further includes: setting the clock line delay order of the first channel to 31; setting the data line delay order of the first channel to 0.

3. The bit alignment correction method according to claim 1, characterized in that, Step S20 further includes: receiving an externally transmitted 8-bit serial training sequence 0000_1111; The received 8-bit serial training sequence is converted from serial to parallel to obtain parallel data.

4. The bit alignment correction method according to claim 1, characterized in that, Step S40 further includes: S401: Adjust the total delay order until the serial-to-parallel conversion result is the same as dat1, then the first edge skipping is considered to have been triggered, and the current total delay order d1 is recorded; S402: Adjust the total delay order until the serial-to-parallel conversion result is the same as dat2. This is considered to have triggered the second edge skipping. Record the current total delay order d2.

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