Data processing methods applied to SOC chips
By introducing a hardware data processing module into the SOC chip, the raw data is preprocessed and cached, solving the problems of slow data processing speed and poor security of the SOC chip, and achieving more efficient, flexible and secure data processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG LEAPFIVE TECH CO LTD
- Filing Date
- 2021-11-23
- Publication Date
- 2026-07-17
Smart Images
Figure CN116150079B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuits, and more particularly to a data processing method applied to SOC chips. Background Technology
[0002] The Internet of Things (IoT) is a network that connects all ordinary physical objects that can be independently addressed, based on information carriers such as the internet and traditional telecommunications networks. In the IoT era, the number of connections between people, between people and things, and between things is growing explosively. To accommodate this explosive growth in data volume, the number of IoT devices must be continuously increased. However, with the rapid development of the IoT, the number of devices is rising sharply, the demand for services is constantly increasing, and the number of cyberattacks is also growing. Against this backdrop, the data processing capabilities and security performance of IoT devices have become increasingly important concerns.
[0003] In current IoT terminal node devices, the core is "SOC (System on Chip) chip + sensor". As the core of IoT terminal node devices, the SOC chip's data processing capabilities and security performance fundamentally determine the data processing capabilities and security performance of IoT devices. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a data processing method for SOC chips, which ensures the stability and reliability of data processing.
[0005] To address the aforementioned problems, this invention provides a data processing method applied to a SOC chip, comprising: receiving raw data; performing hardware processing on the raw data using a hardware data processing module, the hardware processing including: preprocessing the raw data to obtain first processed data, the preprocessing being used to add interactive identification information to the raw data, the interactive identification information including hardware processing instruction information and hardware processing information; identifying the interactive identification information and determining whether the hardware processing instruction information is valid; if the hardware processing instruction information is valid, caching the first processed data; extracting the cached first processed data, performing hardware data processing according to the hardware processing information to obtain second processed data; caching the second processed data; extracting the cached second processed data, using the second processed data as output data of the hardware data processing module and outputting it from the hardware data processing module; if the hardware processing instruction information is invalid, using the first processed data as output data of the hardware data processing module and outputting it from the hardware data processing module.
[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0007] The data processing method for SOC chips provided in this invention, compared with the traditional SOC chip data processing method which uses a single transmission path to process raw data (i.e., transmits raw data to the processor for data processing), performs data processing in a hardware data processing module. This improves the data processing speed and reduces data processing latency. Furthermore, based on the actual data requirements, if the hardware processing instruction is valid, hardware data processing continues, and the second processed data obtained after hardware data processing is output. If the hardware processing instruction is invalid, the first processed data is directly output. This overcomes the limitations of directly transmitting raw data to the processor for data processing in traditional SOC chips, resulting in greater flexibility in data processing operations. In addition, the original... Data can bypass the processor and enter the hardware data processing module first, avoiding the possibility of data leakage or tampering due to data passing through the processor first. At the same time, when the hardware processing instruction information is valid, the first processed data is cached first, and then the cached first processed data is retrieved for hardware data processing. This helps to prevent data loss caused by the difference between the output rate of the preprocessed data and the data receiving rate during hardware data processing. Similarly, after obtaining the second processed data, the second processed data is cached first, and then the cached second processed data is retrieved and output. This helps to prevent data loss caused by the difference between the output rate of the hardware data processed data and the output rate when the hardware data processing module outputs the output data. This helps to ensure the stability and reliability of data processing. Attached Figure Description
[0008] Figure 1 This is a schematic diagram of the structure of a SOC chip;
[0009] Figure 2 This is a schematic diagram of the composition structure of an embodiment of the SOC chip in the data processing method of the present invention applied to the SOC chip;
[0010] Figure 3 This is a flowchart illustrating an embodiment of the data processing method of the present invention applied to a SOC chip. Detailed Implementation
[0011] As the background technology shows, the core of current IoT terminal node devices is "SOC (System on Chip) chip + sensor". Among them, the SOC chip typically integrates a processor, a data processing module, and memory (or an external memory control interface).
[0012] Figure 1 This is a schematic diagram of the structure of a SOC chip.
[0013] refer to Figure 1 The SOC chip 10 includes: a peripheral interface 11, an interconnect bus 12, a processor 13, and an external memory control interface 15; wherein, the peripheral interface 11 is used to couple with peripheral devices, and the interconnect bus 12 is coupled to the peripheral interface 11, the processor 13, and the external memory control interface 15 respectively.
[0014] Data from peripheral interface 11, processor 13 and external memory control interface 15 are all transmitted through interconnect bus 12, and data processing scheduling is all done through processor 13.
[0015] However, when using the current SOC chip 10 to perform data processing, the following problems exist: 1) The data processing speed using the processor 13 is relatively slow, which easily leads to data processing delays; 2) When peripheral devices interact with each other, the data needs to be forwarded and processed by the processor 13. The data interaction between peripheral devices must be scheduled by the processor 13 to complete the data interaction, resulting in a relatively simple transmission path for the raw data sent by the peripheral devices, which leads to poor flexibility in data processing operations; 3) Since all data interaction must be scheduled by the processor 13, and the processor 13 can also obtain the user's raw data, once the processor 13 is compromised, the raw data is at risk of being leaked or tampered with, thus failing to meet the requirements for data privacy and exhibiting poor protection performance for raw data.
[0016] To address the technical problem, this invention provides a data processing method applied to a SOC chip, comprising: receiving raw data; performing hardware processing on the raw data using a hardware data processing module, the hardware processing including: preprocessing the raw data to obtain first processed data, the preprocessing being used to add interactive identification information to the raw data, the interactive identification information including hardware processing instruction information and hardware processing information; identifying the interactive identification information and determining whether the hardware processing instruction information is valid; if the hardware processing instruction information is valid, caching the first processed data; extracting the cached first processed data, performing hardware data processing according to the hardware processing information to obtain second processed data; caching the second processed data; extracting the cached second processed data, using the second processed data as output data of the hardware data processing module, and outputting it from the hardware data processing module; if the hardware processing instruction information is invalid, using the first processed data as output data of the hardware data processing module, and outputting it from the hardware data processing module.
[0017] Compared to traditional SOC chip data processing methods that use a single transmission path to process raw data (i.e., transmitting raw data to the processor for processing), this invention performs data processing in a hardware data processing module. This improves the data processing speed and reduces latency. Furthermore, when the hardware processing instruction is valid, hardware data processing continues, and the second processed data is output. When the hardware processing instruction is invalid, the first processed data is directly output. This overcomes the limitations of traditional SOC chips that directly transmit raw data to the processor for processing, resulting in greater flexibility in data processing. Additionally, raw data can be bypassed according to actual data requirements. The data first enters the hardware data processing module to prevent leakage or tampering of data that has passed through the processor first. Simultaneously, when the hardware processing instruction is valid, the first processed data is cached before being retrieved for hardware data processing. This helps prevent data loss caused by the difference between the output rate of the pre-processed data and the data reception rate during hardware data processing. Similarly, after obtaining the second processed data, it is cached before being retrieved and output. This helps prevent data loss caused by the difference between the output rate of the processed data and the output rate of the hardware data processing module, thus ensuring the stability and reliability of data processing.
[0018] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0019] Figure 2 This is a schematic diagram of the composition structure of an embodiment of the SOC chip in the data processing method of the present invention applied to the SOC chip; Figure 3 This is a flowchart illustrating an embodiment of the data processing method of the present invention applied to a SOC chip.
[0020] refer to Figure 3 The data processing method applied to SOC chips in this embodiment includes the following basic steps:
[0021] Step S1: Receive raw data;
[0022] Step S2: Use the hardware data processing module to perform hardware processing on the raw data. The hardware processing includes:
[0023] Step S21: Preprocess the raw data to obtain the first processed data. The preprocessing is used to add interactive identification information to the raw data. The interactive identification information includes hardware processing instruction information and hardware processing information.
[0024] Step S22: Identify the interactive identification information and determine whether the hardware processing instruction information is valid;
[0025] Step S23: If the hardware processing instruction information is valid, cache the first processed data;
[0026] Step S24: Extract the first processed data from the cache, perform hardware data processing according to the hardware processing information, and obtain the second processed data;
[0027] Step S25: Cache the second processed data;
[0028] Step S26: Extract the second processed data from the cache, use the second processed data as the output data of the hardware data processing module, and output it from the hardware data processing module;
[0029] Step S27: If the hardware processing instruction information is invalid, the first processed data is used as the output data of the hardware data processing module and output to the hardware data processing module.
[0030] In this embodiment, the data processing method further includes: performing step S3 to reprocess the output data output by the hardware data processing module.
[0031] The following combination Figure 2 The SOC chip 20 shown provides a detailed description of the data processing method in this embodiment.
[0032] In this embodiment, the SOC chip 20 includes a processor 23, an interconnect matrix 22, a peripheral module 21, a hardware data processing module 24, and a configuration module 25. The processor 23, the peripheral module 21, and the data processing module 24 are coupled together through the interconnect matrix 22. The configuration module 25 is coupled together with the processor 23, the interconnect matrix 22, the peripheral module 21, and the hardware data processing module 24.
[0033] Specifically, the peripheral module includes a peripheral interface 211 and a memory 221; the hardware data processing module 24 includes a preprocessing module 241, a data forwarding module 242, a cache module 243 and a post-processing module 244, and the post-processing module 244 includes a security processing module 2441.
[0034] Perform step S1 to receive the raw data.
[0035] The raw data serves as input to the SOC chip 20, enabling subsequent data processing within the SOC chip 20. Specifically, the raw data from peripheral devices is received through the data receiving port of the SOC chip 20.
[0036] It should be noted that the peripheral device can be an on-chip peripheral device set on the SOC chip 20, or it can be an off-chip peripheral device set independently of the SOC chip 20. Those skilled in the art can set it according to actual needs, and there is no limitation here.
[0037] In this embodiment, the raw data includes a first type of raw data and a second type of raw data.
[0038] Depending on the application scenario, the transmission paths for the first type of raw data and the second type of raw data are different, each with its own corresponding transmission path. Specifically, the first type of raw data is first transmitted to the hardware data processing module 24, while the second type of raw data is first transmitted to the processor 23.
[0039] As an example, the security level of the first type of raw data is higher than that of the second type of raw data. Therefore, by transmitting the first type of raw data to the hardware data processing module 24 first, and then using the hardware data processing module 24 to perform hardware processing on the first type of raw data, the situation where the raw data is leaked or tampered with after passing through the processor 23 can be avoided, which is beneficial to improving the security of data processing.
[0040] In this embodiment, the step of acquiring the raw data sent by the peripheral device utilizes the peripheral module 21 in the SOC chip 20 to acquire the raw data sent by the peripheral device. That is, the peripheral device sends the raw data to be processed to the SOC chip 20 through the peripheral module 21.
[0041] Specifically, the peripheral module 21 includes several peripheral interfaces 211, which are the peripheral interfaces of the SOC chip 20. Accordingly, the SOC chip 20 obtains the raw data sent by the peripheral device through the peripheral interfaces 211 in the peripheral module 21.
[0042] In this embodiment, the peripheral interface 211 is used as a data receiving port or a data output port.
[0043] The interface type of peripheral interface 211 is configured according to actual needs. As an example, peripheral interface 211 may include one or more of the following: Universal Asynchronous Receiver / Transmitter (UART) interface, Inter Integrated Circuit (I2C) interface, Serial Peripheral Interface (SPI), General-Purpose Input / Output (GPIO) interface, Inter Integrated Circuit Sound (I2S) interface, Serial Audio Interface (SAI), Universal Serial Bus (USB) interface, Ethernet port, and Controller Area Network (CAN).
[0044] The number of peripheral interfaces 211 can be one or more, and the number of peripheral interfaces 211 can be determined by the specifications of the SOC chip 20. For example, such as Figure 2 As shown, taking the peripheral module 21 as an example, which includes N peripheral interfaces 211, the multiple peripheral interfaces 211 are peripheral interface 1, ..., peripheral interface N.
[0045] In this embodiment, the data processing method further includes: determining the transmission path corresponding to the raw data within the SOC chip 20. By determining the transmission path corresponding to the raw data within the SOC chip 20, the SOC chip 20 can process the received raw data using the corresponding transmission path according to the transmission path configuration information when it receives raw data sent by a peripheral device.
[0046] In this embodiment, after the raw data is input to the SOC chip 20 via a specific data receiving port, the transmission path of the raw data has been determined, and the interactive identification information to be added subsequently has also been determined.
[0047] As an example, in the step of determining the transmission path of the raw data within the SOC chip 20, the transmission path is related to the security level information of the raw data. For instance, the security level of the first type of raw data is higher than that of the second type of raw data. The first type of raw data is first transmitted to the hardware data processing module 24, and the second type of raw data is first transmitted to the processor 23. That is, the transmission path of the first type of raw data includes from the peripheral interface 211 to the hardware data processing module 24, and the transmission path of the second type of raw data includes from the peripheral interface 211 to the processor 23.
[0048] In this embodiment, the configuration module 25 is used to determine the transmission path of the original data within the SOC chip 20, as well as the interactive identification information to be added. Specifically, the configuration module 25 contains configuration information, including configuration information corresponding to the transmission path and configuration information corresponding to the interactive identification information.
[0049] In this embodiment, the configuration module 25 is used to configure and determine the correspondence between the transmission path of the raw data within the SOC chip 20 and the peripheral interface 211. Specifically, when the corresponding peripheral interface 211 receives raw data sent by the corresponding peripheral device, the SOC chip 20 processes the raw data using the transmission path corresponding to the peripheral interface 211; in other words, once the peripheral interface 211 receives the raw data, the transmission path of the raw data within the SOC chip 20 is determined. Similarly, the configuration module 25 is used to configure and determine the interaction identification information of the raw data received by the peripheral interface 211 during subsequent preprocessing.
[0050] The configuration module 25 contains configuration information for determining the interactive identification information of the original data. Accordingly, the preprocessing module 241 adds the corresponding interactive identification information to the original data according to the configuration information of the configuration module 25, so as to add the required interactive identification information to the original data according to different application scenarios.
[0051] In this embodiment, the configuration module 25 includes a One-Time Programmable (OTP) module. The storage unit in the OTP module can only be programmed once, and the data after programming cannot be changed or erased again. It has good anti-reverse characteristics, which helps to reduce the risk of the configuration information in the configuration module 25 being changed or erased, and further improves the security and reliability of the data. In addition, the OTP module also has excellent characteristics such as non-volatility, high reliability, strong stability, and strong anti-interference ability.
[0052] In other embodiments, the configuration module may also be other types of storage modules.
[0053] Continue to refer to Figure 2and Figure 3 Step S2 is executed, where the raw data is processed using the hardware data processing module 24.
[0054] Compared with software modules, the use of hardware modules 24 can improve the efficiency and speed of data processing, thereby improving the data processing latency.
[0055] Moreover, compared with software modules, using hardware module 24 for hardware processing first helps avoid the problem of the original data being accessed by processor 23 first, thus playing a role in data isolation and protection, resisting intrusion by external programs, preventing data from being tampered with and leaked, and improving data security.
[0056] Furthermore, by using the hardware data processing module 24 to process the raw data, the processor 23 can be bypassed by directly forwarding the output data of the hardware data processing module 24 to the data output port, thus avoiding the leakage or tampering of the data after passing through the processor 23.
[0057] In this embodiment, the hardware data processing module 24 is used to perform hardware processing on the first type of raw data.
[0058] In this embodiment, the first type of raw data has a higher security level. By first inputting the first type of raw data into the hardware data processing module 24 for hardware processing, the security of the data processing of the first type of raw data is improved.
[0059] Specifically, the hardware processing includes: performing step S21 to preprocess the raw data to obtain the first processed data. The preprocessing is used to add interactive identification information to the raw data. The interactive identification information includes hardware processing instruction information and hardware processing information.
[0060] The raw data is preprocessed to carry interactive identification information, so that the hardware data processing module 24 can complete the hardware processing of the raw data based on the interactive identification information without being scheduled by the processor 23.
[0061] The hardware processing instruction information is used to identify whether the original data needs to be processed by hardware (e.g., whether it needs to be encrypted). The hardware processing information is used to identify one or more of the types, paths, and methods (e.g., encryption methods) that the original data needs to be processed in subsequent hardware processing.
[0062] Specifically, the hardware data processing module 24 is used to perform hardware processing on the first type of raw data, and correspondingly, the first type of raw data is preprocessed.
[0063] In this embodiment, the hardware data processing module 24 is coupled to the peripheral module 21. The hardware data processing module 24 includes a preprocessing module 241. The peripheral module 21 and the preprocessing module 241 are coupled to realize data interaction, and then the original data is preprocessed by the preprocessing module 241.
[0064] In this embodiment, the SOC chip 20 is suitable for blockchain technology. Therefore, the hardware data processing module 24 is a blockchain processing module. Blockchain technology has high requirements for data security. Therefore, in this embodiment, data processing is achieved through the preprocessing module 241, without the need for the processor 23 to forward the data first. This avoids the risk of data being tampered with and leaked due to the processor 23 obtaining the original data first, thereby improving the security of data processing and meeting the data security requirements of blockchain technology.
[0065] Specifically, the SOC chip 20 is suitable for the Internet of Things (IoT). For the IoT SOC chip 20, there are high requirements for the privacy and security of the raw data. Therefore, this embodiment uses the hardware data processing module 26 to perform hardware processing on the raw data and performs preprocessing first so that subsequent data reprocessing can be performed after the hardware processing is completed. This reduces the dependence on the processor 23, thereby effectively reducing the risk of the raw data of the SOC chip 20 being leaked and tampered with, and correspondingly effectively ensuring the security and reliability of the raw data of the SOC chip 20.
[0066] Specifically, peripheral module 21 is coupled to hardware data processing module 24 via first internal bus IB1. Correspondingly, raw data can be transmitted sequentially to preprocessing module 241 via peripheral module 21 and first internal bus IB1. In this embodiment, first internal bus IB1 can be a data transmission bus based on different standards, which can be selected according to actual needs.
[0067] Specifically, the preprocessing module 241 receives raw data configured to transmit raw data to the peripheral interface 211 of the preprocessing module 241.
[0068] In this embodiment, the preprocessing module 241 is a tagging module. Preprocessing is used to add tag information to the original data. Correspondingly, the interactive identification information includes tag information with multiple tag fields. The tag fields are used to represent hardware processing instruction information and hardware processing information.
[0069] During subsequent data transmission, the tag information and the original data will be sent together to other modules.
[0070] Specifically, the hardware processing instruction information includes security instruction information, which in turn includes security processing information corresponding to the security instruction information.
[0071] Accordingly, the processed data is then subjected to security processing based on the hardware processing information. Specifically, the subsequent processing module 244 includes a security processing module 2441 for performing security processing.
[0072] In one embodiment, the security indication information is related to encryption processing; that is, if the security indication information is encryption indication information, then the subsequent security processing will be encryption processing accordingly. In another embodiment, the security indication information is related to decryption processing; that is, if the security indication information is decryption indication information, then the subsequent security processing will be decryption processing accordingly.
[0073] In this embodiment, taking security indication information and encryption processing as examples, the tag field corresponding to the security indication information includes an encryption enable field, and the tag field corresponding to the security processing information includes an encryption algorithm type field and an encryption key field.
[0074] The encryption enable field determines whether the original data needs to be encrypted. The encryption algorithm type field represents the encryption algorithm, and the encryption key field represents the encryption key. The encryption algorithm type field and the encryption key field represent the encryption algorithm parameters used to encrypt the original data. Accordingly, when the encryption enable field indicates that the original data needs to be encrypted, the security processing module 2441 can encrypt the original data according to these algorithm parameters.
[0075] In this embodiment, the hardware processing information also includes priority processing information. Specifically, the interactive identification information includes tag information with multiple tag fields; therefore, the priority processing information is correspondingly a priority field.
[0076] Priority processing information indicates the priority level of the raw data during the data processing process. The higher the priority level of the data, the more priority it needs to be processed. For example, when data congestion may occur due to bandwidth processing, high-priority data will be sent to other modules for further processing when congestion occurs, while other low-priority data can be cached in cache module 243.
[0077] It should be noted that in other embodiments, the tag field corresponding to the hardware processing information can also be other types of tag fields. For example, a routing control field, used to determine the forwarding direction of the preprocessed data. The routing control field is used to determine the forwarding direction of the first processed data. For example, after hardware processing, whether the data is forwarded to the processor for further business processing, or directly forwarded to other peripheral devices (e.g., external chips) through peripheral module 21, or uploaded to the blockchain cloud through peripheral interface 221, which is the network communication interface of SOC chip 20. Accordingly, the subsequent data forwarding module 242 forwards the data according to the forwarding direction.
[0078] The hardware processing also includes: performing step S22, identifying the interactive identification information, and determining whether the hardware processing instruction information is valid.
[0079] Subsequently, the original data is processed accordingly based on the interaction recognition information, such as data forwarding and data encryption.
[0080] In this embodiment, the identification of interactive identification information includes: parsing tag information to obtain hardware processing instruction information and the domain value of hardware processing information. The domain value of hardware processing instruction information is used to indicate whether the hardware processing instruction information is valid, and the domain value of hardware processing information is used to indicate the hardware processing method.
[0081] In this embodiment, the data forwarding module 242 parses the tag information and determines the subsequent data transmission path of the first processed data based on the tag information.
[0082] In this embodiment, the tag field corresponding to the hardware processing instruction information is an enable field. Therefore, the validity of the hardware processing instruction information is determined based on the field value. For example, when the field value is "1", it indicates that the hardware processing instruction information is valid; when the field value is "0", it indicates that the hardware processing instruction information is invalid.
[0083] As an example, when the hardware processing instruction is invalid, after preprocessing the raw data, the data can be directly forwarded to the peripheral device, or the data can be forwarded to the processor for further processing via the data forwarding module 242. As another example, when the hardware processing instruction is valid, after preprocessing the raw data, the data can be forwarded to the subsequent processing module 244 via the data forwarding module 242 for hardware data processing, thus completing the hardware data processing within the hardware data processing module 24.
[0084] The hardware processing also includes: executing step S23, whereby, if the hardware processing instruction information is valid, the first processed data is cached.
[0085] When the hardware processing instruction information is valid, the first processed data is cached first, and then the cached first processed data is retrieved for hardware data processing. This helps to prevent data loss caused by the difference between the output rate of the preprocessed data and the data receiving rate during hardware data processing, thereby helping to ensure the stability and reliability of data processing.
[0086] Accordingly, in subsequent data processing, the cached first processed data is extracted according to the priority information in the interaction recognition information.
[0087] In this embodiment, the first processed data is cached by the cache module 243, which is the internal memory of the hardware data processing module 24.
[0088] In this embodiment, the first processed data is cached in the internal memory of the hardware data processing module 24, so that the hardware processing of the original data is completed inside the hardware processing module 24. Compared with caching in the external memory, this helps to save data transmission time and improve data processing efficiency.
[0089] Specifically, the processed data is forwarded to the cache module 243 via the data forwarding module 242.
[0090] In this embodiment, the internal memory includes First-In-First-Out (FIFO) memory or Static Random-Access Memory (SRAM).
[0091] The hardware processing also includes: executing step S24, extracting the first processed data from the cache, performing hardware data processing based on the hardware processing information, and obtaining the second processed data.
[0092] Specifically, when the data forwarding module 242 forwards the first processed data to the caching module 243 for caching, it simultaneously transmits the interaction identification information of the first processed data to the subsequent processing module 244. The subsequent processing module 244 extracts the cached first processed data based on the interaction identification information and performs corresponding hardware data processing.
[0093] If the hardware processing instruction is valid, it means that the data after the first processing needs to undergo hardware data processing.
[0094] As an example, if the hardware processing instruction information includes security instruction information, then the security instruction information is valid, indicating that the data after the first processing needs to undergo security processing to obtain the data after the second processing. This improves the security performance of the data to prevent the data from being tampered with or verified.
[0095] Accordingly, the hardware data processing includes security processing. In this embodiment, the security processing module 2441 performs security processing on the first processed data.
[0096] In this embodiment, corresponding security processing is performed based on the field value of the security processing information. The field value of the security processing information identifies the method of security processing required (e.g., the encryption key and algorithm parameters).
[0097] In this embodiment, taking security indication information and encryption processing as examples, the steps for security processing of the first processed data include: encrypting the first processed data. When the tag field of the security indication information indicates that the original data needs to be encrypted, the security processing module 2441 receives the first processed data and encrypts it. It uses an encryption algorithm and encryption key to convert plaintext into ciphertext, achieving information concealment and thus protecting information security.
[0098] In other embodiments, when security indication information is related to decryption, the security processing is decryption processing. Accordingly, the subsequent processing module also includes a decryption module, which is used to decrypt the first processed data.
[0099] It should be noted that after obtaining the second processed data, the data forwarding module 242 identifies the hardware processing information in the second processed data and forwards the second processed data using the corresponding transmission path.
[0100] It should also be noted that in other embodiments, the post-processing module may include other types of functional modules for performing corresponding hardware data processing.
[0101] The hardware processing also includes: executing step S25 to cache the second processed data.
[0102] After obtaining the second processed data, the second processed data is first cached, and then the cached second processed data is extracted. The second processed data is used as the output data of the hardware data processing module 24 and output from the hardware data processing module 24. This helps to prevent data loss caused by the difference between the output rate of the hardware data processed data and the output rate of the hardware data processing module 24 when outputting the output data, thereby helping to ensure the stability and reliability of data processing.
[0103] In this embodiment, the second processed data is cached by the cache module 243 in the hardware data processing module 24, so that the hardware processing of the original data is completed inside the hardware processing module 24.
[0104] The hardware processing also includes: executing step S26, extracting the cached second processed data, using the second processed data as the output data of the hardware data processing module 24, and outputting it from the hardware data processing module 24.
[0105] In this embodiment, according to the priority processing information in the interactive identification information, the cached second processed data is extracted as the output data of the hardware data processing module 24 and output from the hardware data processing module 24 so that the output data can be further processed.
[0106] In this embodiment, before extracting the cached second processed data and using the second processed data as the output data of the hardware data processing module and outputting it from the hardware data processing module, the method further includes: performing de-labeling processing on the second processed data to remove the used label fields.
[0107] During hardware processing, the data processing method is determined by the tag field. Therefore, after the data processing related to the tag field is completed, the used tag field is no longer needed. For example, taking encryption processing as an example, after encryption processing is completed, the encryption enable field, encryption algorithm type field, and encryption key field in the tag field are no longer needed. Therefore, the second-processed data can be de-tagged to remove the encryption enable field, encryption algorithm type field, and encryption key field.
[0108] Remove used label fields to avoid excessive label fields interfering with subsequent reprocessing of the output data, thereby reducing the probability of reprocessing errors.
[0109] In this embodiment, the data after hardware data processing is forwarded to the preprocessing module 241 through the data forwarding module 242, and the preprocessing module 241 is used to de-label the second processed data.
[0110] The hardware processing also includes: executing step S27, in the case that the hardware processing instruction information is invalid, using the first processed data as the output data of the hardware data processing module 24 and outputting it into the hardware data processing module 24.
[0111] When the hardware processing instruction information is invalid, the data forwarding module 242 identifies the hardware processing information in the first processed data and forwards the first processed data using the corresponding transmission path so that the output data can be reprocessed subsequently.
[0112] In this embodiment, before the first processed data is used as the output data of the hardware data processing module and output to the hardware data processing module when the hardware processing instruction information is invalid, the method further includes: performing de-labeling processing on the first processed data to remove the used label fields.
[0113] During hardware processing, it is necessary to identify label fields and determine the data processing method based on the label fields. Therefore, after completing the data processing related to the label fields, the used label fields are no longer needed. For example, if the hardware processing instruction information is invalid, the label field of the hardware processing information of the first processed data can also include a routing control field to determine the forwarding direction of the first processed data. After forwarding the first processed data to the data forwarding module 242, the data forwarding module 242 configures the forwarding direction of the first processed data. Correspondingly, the data processing corresponding to the routing control field of the first processed data has been completed, so the first processed data can be delabeled by removing the label from the routing control field.
[0114] Remove used label fields to avoid excessive label fields interfering with information during subsequent reprocessing of the output data, thereby reducing the probability of reprocessing errors.
[0115] In this embodiment, the data after hardware processing is forwarded to the preprocessing module 241 through the data forwarding module 242, and the preprocessing module 241 is used to de-label the first processed data.
[0116] In this embodiment, after outputting the output data from the hardware data processing module 24, the method further includes: executing step S3 to reprocess the output data output by the hardware data processing module 24.
[0117] In one embodiment, data reprocessing includes forwarding the data to a data output port and outputting the data through the data output port. In this embodiment, after the raw data undergoes hardware processing in the hardware data processing module 24, it is directly output through the data output port. That is, after the raw data is input to the SOC chip 20, it is only processed in the hardware data processing module 24 and does not pass through the processor 23.
[0118] Compared to the traditional SOC chip data processing method that uses a single transmission path to process raw data (i.e., transmits raw data to the processor for data processing), this solution preprocesses the raw data, adds interactive identification information, and then uses this information to complete the hardware processing within the hardware data processing module 24. This improves upon the limitations of directly transmitting raw data to the processor 23 for data processing in traditional SOC chips, reduces the probability of raw data being tampered with, and thus enhances the flexibility and security of data processing.
[0119] As an example, the output data is forwarded to the peripheral module 21 via the data forwarding module 242 to achieve a data transmission path that directly forwards data to the peripheral device. Specifically, the preprocessing module 241 is coupled to the peripheral interface 211. The data forwarding module 242 forwards the output data to the preprocessing module 241, and then forwards the output data to the peripheral module 21 via the preprocessing module 241. Specifically, the output data is transmitted to the external device via the peripheral interface 211, or the output data is uploaded to the cloud database.
[0120] In another embodiment, data reprocessing further includes forwarding the output data to processor 23 for business processing to obtain third processed data.
[0121] Specifically, in this embodiment, the data reprocessing further includes: outputting third processed data through a data output port.
[0122] The output data is forwarded to processor 23 for business processing, realizing the functional processing of the data.
[0123] In this embodiment, processor 23 is responsible for data processing and control scheduling. As an example, processor 23 can be a CPU (central processing unit).
[0124] Since processor 23 is a software module, forwarding data to processor 23 for business processing is a data processing performed by the software module. Accordingly, this embodiment can realize a processing method that combines hardware and software.
[0125] In summary, compared to the traditional SOC chip data processing method that uses a single transmission path to process raw data (i.e., directly transmitting raw data to the processor for data processing), this solution preprocesses the raw data by adding interactive identification information. It then determines whether the raw data requires hardware data processing by identifying the hardware processing instruction information within this information. If the hardware processing instruction is valid, hardware data processing is performed first to obtain the second processed data. This second processed data serves as the output data of the hardware data processing module. Based on the actual data requirements, the output data is forwarded to the processor 23 for business processing to obtain the third processed data, which is then output through the data output port. Alternatively, if the hardware processing instruction is invalid, the first processed data is used as the output data of the hardware data processing module. Based on the actual data requirements, the output data is forwarded to the processor 23 for business processing to obtain the third processed data, which is then output through the data output port. This improves upon the limitations of directly transmitting raw data to the processor for data processing in traditional SOC chips, reduces the probability of raw data tampering, and thus enhances the flexibility and security of data processing.
[0126] In other embodiments, if the raw data also includes a second type of raw data, the data processing method further includes sending the second type of raw data to a processor for corresponding business processing.
[0127] In this embodiment, taking the example that the security level of the first type of raw data is higher than that of the second type of raw data, the security level of the second type of raw data is lower and can be forwarded to the processor 23 as plaintext. Therefore, no hardware processing is performed on the second type of raw data.
[0128] In this embodiment, the second type of raw data is sent directly to the processor 23 via the interconnect matrix 22 without going through the hardware data processing module 24, and then the corresponding business processing is performed. After the business processing is completed, the third processed data is output through the data output port via the interconnect matrix 22.
[0129] Therefore, this embodiment is also compatible with the data processing methods of traditional SOC chips, which helps to improve the flexibility of data processing, meet different data processing needs, and improve the compatibility of data processing.
[0130] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A data processing method applied to a SOC chip, characterized in that, include: Receive raw data; The raw data is processed using a hardware data processing module, the hardware processing including: The raw data is preprocessed to obtain first processed data. This preprocessing adds interactive identification information to the raw data. The interactive identification information includes hardware processing instruction information and hardware processing information. A configuration module is used to determine the interactive identification information to be added to the raw data. The configuration module includes a one-time programmable module, where the storage unit can only be programmed once, and the programmed data cannot be changed or erased again. The interactive identification information includes tag information with multiple tag fields. During subsequent data transmission, the tag information is sent along with the raw data. Identify the interaction identification information and determine whether the hardware processing instruction information is valid; If the hardware processing instruction is valid, the first processed data is cached; Extract the first processed data from the cache, perform hardware data processing according to the hardware processing information, and obtain the second processed data; The second processed data is cached; Extract the second processed data from the cache, use the second processed data as the output data of the hardware data processing module, and output it from the hardware data processing module; If the hardware processing instruction information is invalid, the first processed data is used as the output data of the hardware data processing module and output to the hardware data processing module.
2. The data processing method applied to a SOC chip as described in claim 1, characterized in that, The raw data includes a first type of raw data and a second type of raw data, and the transmission paths of the first type of raw data and the second type of raw data are different; The first type of raw data is processed using a hardware data processing module. The data processing method further includes: sending the second type of raw data to the processor for business processing.
3. The data processing method applied to a SOC chip as described in claim 1, characterized in that, The label field is used to represent the hardware processing instruction information and hardware processing information; Before extracting the second processed data from the cache and using the second processed data as the output data of the hardware data processing module and outputting it from the hardware data processing module, the method further includes: performing de-labeling processing on the second processed data to remove the used label fields. In the event that the hardware processing instruction information is invalid, before the first processed data is used as the output data of the hardware data processing module and output to the hardware data processing module, the method further includes: performing detagging processing on the first processed data to remove the used tag fields.
4. The data processing method applied to a SOC chip as described in claim 1, characterized in that, The interactive identification information includes tag information with multiple tag fields, the tag fields being used to represent the hardware processing instruction information and the hardware processing information; Identifying the interactive identification information includes: parsing the tag information to obtain the hardware processing instruction information and the domain value of the hardware processing information; Based on the field value of the hardware processing instruction information, determine whether the hardware processing instruction information is valid; The hardware data processing is performed based on the domain value of the hardware processing information.
5. The data processing method applied to a SOC chip as described in claim 1, characterized in that, The hardware processing instruction information includes security instruction information, and the hardware processing information includes security processing information corresponding to the security instruction information; The hardware data processing step, which involves processing hardware data based on the hardware processing information, includes security processing.
6. The data processing method applied to a SOC chip as described in claim 5, characterized in that, The security indication information is encrypted; The security process is encryption. or, The security instruction information is a decryption instruction information; The security process described is a decryption process.
7. The data processing method applied to a SOC chip as described in claim 1, characterized in that, The hardware processing information includes priority processing information; According to the priority processing information in the interaction recognition information, the cached first processed data is extracted; According to the priority processing information in the interaction recognition information, the cached second processed data is extracted.
8. The data processing method applied to a SOC chip as described in claim 1, characterized in that, The internal memory of the hardware data processing module is used for caching.
9. The data processing method applied to a SOC chip as described in claim 8, characterized in that, The internal memory includes static random access memory or first-in-first-out memory.
10. The data processing method applied to a SOC chip as described in claim 1, characterized in that, After outputting the output data from the hardware data processing module, the method further includes: performing data reprocessing on the output data output by the hardware data processing module; The data reprocessing includes: forwarding the output data to the data output port and outputting it through the data output port; Alternatively, the data reprocessing may include: forwarding the output data to a processor for business processing to obtain third processed data.