A flash memory grain life prediction method, device, equipment and readable storage medium

Abstract

The application discloses a flash memory particle life prediction method, device and equipment and a readable storage medium, and belongs to the technical field of storage. The method comprises the following steps: performing a read interference resistance test on each storage block of a to-be-tested flash memory particle, and obtaining the read interference resistance capability of each storage block; determining the residual erase times of each storage block according to a pre-established corresponding relationship between the read interference resistance capability and the residual erase times of the flash memory particle; and taking the average value of the residual erase times of all the storage blocks as the life of the to-be-tested flash memory particle. Compared with the verification method in the prior art, the application reduces the damage to the flash memory particle, does not cause additional loss, and the detected flash memory particle can still be used in formal products. The application can be applied to flash memory particle quality detection, flash memory quality grade classification, full play of the value of different flash memories, and screening of flash memory particles meeting requirements in high-quality demand fields.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a method, apparatus, device, and computer-readable storage medium for predicting the lifetime of flash memory chips. Background Technology

[0002] Flash memory chips, also known as flash storage, are a type of non-volatile memory widely used in storage products such as solid-state drives (SSDs) and USB flash drives. Data reliability and product lifespan have always been two important quality indicators for these storage products. The lifespan of flash memory chips is generally checked by verifying whether the number of erase cycles meets the nominal value. Existing technologies for testing erase cycles typically require actual erase tests, which is a verification method. However, flash memory chips cannot be used after the experiment, so the more samples tested, the higher the cost. Therefore, this application provides a flash memory chip lifespan prediction method to solve the problems of sample damage and high cost caused by the verification methods used in existing technologies. Summary of the Invention

[0003] The purpose of this application is to provide a method, apparatus, device, and computer-readable storage medium for predicting the lifetime of flash memory chips, thereby reducing damage to flash memory chips and avoiding additional losses.

[0004] To achieve the above objectives, this application provides a method for predicting the lifetime of flash memory chips, comprising:

[0005] Each memory block of the flash memory chip under test is subjected to read interference resistance test to obtain the read interference resistance capability of each memory block;

[0006] Based on the pre-established correspondence between the read interference resistance of flash memory chips and the remaining erase count, the remaining erase count of each storage block is determined, and the average of the remaining erase counts of all storage blocks is taken as the lifetime of the flash memory chip under test.

[0007] Optionally, the read interference immunity test is performed on each storage block of the flash memory chip under test to obtain the read interference immunity capability of each storage block, including:

[0008] S201: Perform multiple consecutive read operations on a storage page in each storage block of the flash memory chip under test, with a preset read operation step size; each storage block includes multiple storage pages;

[0009] S202: Read the data of the other storage pages in each storage block, excluding the storage page itself;

[0010] S203: Determine whether the number of bit errors in the data of the other storage pages exceeds a preset threshold; if not, execute steps S201 to S202 until the number of bit errors in the data of the other storage pages exceeds the preset threshold; if yes, execute step S204.

[0011] S204: Record the total number of read operations performed on the storage page; the total number of read operations is the read interference resistance of each storage block.

[0012] Optionally, before determining the remaining erase count of each storage block based on a pre-established correspondence between the read interference resistance of flash memory chips and the remaining erase count, and taking the average of the remaining erase counts of all storage blocks as the lifetime of the flash memory chip under test, the method further includes:

[0013] S301: Fill each storage block in the flash memory chip sample with data; the flash memory chip sample includes multiple storage blocks; the storage blocks are valid storage blocks.

[0014] S302: Perform a read interference resistance test on each of the storage blocks and record the read interference resistance of each of the storage blocks; wherein, the first recorded read interference resistance is the read interference resistance in the initial state;

[0015] S303: Each storage block is erased multiple times consecutively with a preset erase count step size;

[0016] S304: Determine whether each of the storage blocks has failed; if not, execute steps S301 to S303 until the storage block fails; if yes, execute step S305.

[0017] S305: Record the total number of times each of the storage blocks is erased and the remaining number of erases after erasing each of the preset erase count steps; the total number of erases is the remaining number of erases in the initial state;

[0018] S306: Based on the read interference resistance capability in the initial state and the read interference resistance capability after erasing each preset erase count step, as well as the remaining erase count in the initial state and the remaining erase count after erasing each preset erase count step, establish the correspondence between the read interference resistance capability and the remaining erase count of the flash memory chip.

[0019] Optionally, step S304 includes:

[0020] Determine whether the write or erase operation performed on each of the storage blocks was successful; if so, execute steps S301 to S303 until the write or erase operation fails; if not, execute step S305.

[0021] Optionally, step S306 includes:

[0022] Based on the read interference resistance capability in the initial state and the read interference resistance capability after erasing each preset erase count step, as well as the remaining erase count in the initial state and the remaining erase count after erasing each preset erase count step, the relationship curve between the read interference resistance capability and the remaining erase count of the flash memory chip is obtained.

[0023] The relationship curves are fitted to establish the correspondence between the read interference resistance of flash memory chips and the remaining number of erase cycles.

[0024] To achieve the above objectives, this application also provides a flash memory chip lifetime prediction device, comprising:

[0025] The data acquisition module is used to perform read interference resistance tests on each storage block of the flash memory chip under test, and to acquire the read interference resistance capability of each storage block;

[0026] The lifetime prediction module is used to determine the remaining erase count of each storage block based on a pre-established correspondence between the read interference resistance capability and the remaining erase count of the flash memory chip, and to take the average of the remaining erase counts of all storage blocks as the lifetime of the flash memory chip under test.

[0027] Optionally, the data acquisition module includes:

[0028] A read operation unit is used to perform multiple consecutive read operations on a storage page in each storage block of the flash memory chip under test, with a preset read operation number step size; each storage block includes multiple storage pages.

[0029] A data read unit is used to read data from other storage pages within each storage block, excluding the storage page itself.

[0030] The error quantity judgment unit is used to determine whether the bit error quantity of the data in the other storage pages exceeds a preset threshold; if not, the read operation unit to the read data unit is executed until the bit error quantity of the data in the other storage pages exceeds the preset threshold; if so, the record anti-read interference capability unit is executed.

[0031] A read interference resistance recording unit is used to record the total number of read operations performed on the storage page; the total number of read interference resistance is the capability of each storage block.

[0032] Optionally, before the lifetime prediction module, there is also:

[0033] A write operation module is used to fill each storage block in the flash memory chip sample with data; the flash memory chip sample includes multiple storage blocks; each storage block is a valid storage block.

[0034] A read interference resistance module is used to test the read interference resistance of each storage block and record the read interference resistance of each storage block; wherein, the first recorded read interference resistance is the read interference resistance in the initial state.

[0035] The erase operation module is used to erase each of the storage blocks multiple times consecutively at a preset erase count step;

[0036] The status determination module is used to determine whether each of the storage blocks has failed; if not, the write operation module to the erase operation module is executed until the storage block fails; if yes, the module for recording the remaining number of erases is executed.

[0037] The module for recording the remaining erase counts is used to record the total number of times each of the storage blocks is erased and the remaining erase counts after erasing each of the preset erase count steps; the total number of times is the remaining erase counts in the initial state;

[0038] The relationship establishment module is used to establish a correspondence between the anti-read interference capability and the remaining erase count of the flash memory chip based on the anti-read interference capability in the initial state and the anti-read interference capability after erasing each preset erase count step, as well as the remaining erase count in the initial state and the remaining erase count after erasing each preset erase count step.

[0039] To achieve the above objectives, this application also provides a flash memory chip lifetime prediction device, comprising:

[0040] Memory, used to store computer programs;

[0041] A processor is configured to implement the steps of the flash memory chip lifetime prediction method as described above when executing the computer program.

[0042] To achieve the above objectives, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the flash memory chip lifetime prediction method described above.

[0043] This application provides a method for predicting the lifetime of a flash memory chip, comprising: performing a read interference resistance test on each storage block of the flash memory chip under test to obtain the read interference resistance capability of each storage block; determining the remaining erase count of each storage block according to a pre-established correspondence between the read interference resistance capability of the flash memory chip and the remaining erase count; and taking the average of the remaining erase counts of all storage blocks as the lifetime of the flash memory chip under test.

[0044] Obviously, this application pre-establishes a correspondence between the read interference resistance of flash memory chips and the remaining erase cycles. By obtaining the read interference resistance of flash memory chips and determining the remaining erase cycles based on the correspondence, the lifespan of flash memory chips can be predicted. Compared with the verification methods in the prior art, this reduces damage to flash memory chips, does not generate additional losses, and the tested flash memory chips can still be used in formal products, and the tested products can still be used in formal products. It can be applied to flash memory chip quality testing; it can be applied to flash memory quality grade classification to fully utilize the value of different flash memory chips; and it can be applied to screening in high-quality demand areas to select flash memory chips that meet the requirements. This application also provides a flash memory chip lifespan prediction device, equipment, and computer-readable storage medium, which have the above-mentioned beneficial effects. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0046] Figure 1 A flowchart illustrating a flash memory chip lifetime prediction method provided in this application embodiment;

[0047] Figure 2 A flowchart illustrating a flash memory chip lifetime prediction method provided in this application embodiment;

[0048] Figure 3 A structural diagram of a flash memory chip storage cell provided in an embodiment of this application;

[0049] Figure 4 A flowchart illustrating the relationship between the remaining erase cycles and read interference resistance of a flash memory chip, provided as an embodiment of this application;

[0050] Figure 5 A schematic diagram of a process for detecting the read interference resistance of a storage block, provided in an embodiment of this application;

[0051] Figure 6 A graph showing the relationship between the remaining erase cycles and read interference immunity of a flash memory chip, provided in an embodiment of this application;

[0052] Figure 7 This is a structural block diagram of a flash memory chip lifetime prediction device provided in an embodiment of this application. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] Flash memory chips have a limited number of erase cycles per block. For example, a block in a certain MLC (Multi-Level Cell) NAND flash memory chip might be erasable n times. If a block is erased more than n times, read / write errors or inability to erase will occur. However, not all blocks have exactly n erase cycles; some blocks have more than n, and some have less. This leads to a risk of data errors when operating on blocks with a maximum erase cycle of less than n, while operating on blocks with a maximum erase cycle of more than n results in wasted lifespan. NAND flash memory is a superior storage device compared to hard disk drives.

[0055] When inspecting the quality of NAND flash memory chips, lifetime testing is quite difficult. The only method is to sample from a batch and perform an erase test to verify if the nominal number of erase cycles has been reached. This method is destructive; the samples after the test have exhausted their lifetime and cannot be used again. Therefore, this method limits the number of samples, otherwise the cost would be too high. Furthermore, for flash memory chips with inconsistent performance, the effectiveness of this method is greatly reduced, or even more samples are needed. Therefore, this application provides a flash memory chip lifetime prediction method that pre-establishes a correlation between the read interference resistance of flash memory chips and the remaining erase cycles. By obtaining the read interference resistance of the flash memory chips and determining the remaining erase cycles based on the correlation, the lifetime of the flash memory chips can be predicted, thereby reducing damage to the flash memory chips and avoiding additional losses.

[0056] Please refer to Figure 1 , Figure 1 A flowchart illustrating a flash memory chip lifetime prediction method provided in this application embodiment, the method may include:

[0057] S101: Perform an anti-read interference test on each storage block of the flash memory chip under test to obtain the anti-read interference capability of each storage block.

[0058] This embodiment does not limit the specific method for obtaining the read interference resistance capability of the flash memory chip under test, as long as the read interference resistance capability can be obtained. For example, it can be S201: Perform multiple consecutive read operations on a storage page in each storage block of the flash memory chip under test with a preset read operation number step size; each storage block includes multiple storage pages; S202: Read the data of other storage pages in each storage block except for the storage page; S203: Determine whether the bit error rate of the data of the other storage pages exceeds a preset threshold; if not, execute steps S201 to S202 until the bit error rate of the data of the other storage pages exceeds the preset threshold; if yes, execute step S204; S204: Record the total number of read operations performed on the storage pages; the total number of read operations is the read interference resistance capability of each storage block. Here, bit error refers to bit error in data transmission.

[0059] This embodiment does not limit the specific value of the preset read operation step size; the specific value can be determined according to actual needs. It should be noted that a smaller read operation step size results in higher accuracy but longer processing time. Similarly, this embodiment does not limit the specific value of the preset threshold; the specific value can be determined according to actual needs.

[0060] S102: Based on the pre-established correspondence between the anti-read interference capability and the remaining erase count of the flash memory chip, determine the remaining erase count of each storage block, and take the average of the remaining erase counts of all storage blocks as the lifetime of the flash memory chip under test.

[0061] This embodiment does not limit the specific method of establishing the correspondence between the read interference resistance of flash memory chips and the remaining erase counts, as long as the correspondence between the read interference resistance of flash memory chips and the remaining erase counts can be obtained. For example, it could be S301: fill each storage block in the flash memory chip sample with data; the flash memory chip sample includes multiple storage blocks; the storage blocks are valid storage blocks; S302: perform read interference resistance test on each storage block and record the read interference resistance of each storage block; wherein, the first recorded read interference resistance is the read interference resistance in the initial state; S303: perform continuous multiple erase count tests on each storage block with a preset erase count step size. S304: Determine if each storage block is invalid; if not, execute steps S301 to S303 until the storage block is invalid; if yes, execute step S305; S305: Record the total number of times each storage block is erased and the remaining number of erases after erasing each preset erase step; the total number is the remaining number of erases in the initial state; S306: Based on the read interference resistance in the initial state and the read interference resistance after erasing each preset erase step, as well as the remaining number of erases in the initial state and the remaining number of erases after erasing each preset erase step, establish the correspondence between the read interference resistance of the flash memory chip and the remaining number of erases. It should be noted that the read interference resistance in the initial state corresponds to the remaining number of erases in the initial state; the read interference resistance after erasing each preset erase step corresponds to the remaining number of erases after erasing each preset erase step.

[0062] This embodiment does not limit the specific value of the preset erase count step size; the specific value of the preset erase count step size can be determined according to actual needs. It should be noted that the smaller the preset erase count step size, the higher the accuracy, but the longer the time consumed.

[0063] This embodiment does not limit the specific method for obtaining the read interference resistance of flash memory chip samples, as long as the read interference resistance can be obtained. For example, it can be the same as the method for obtaining the read interference resistance of the flash memory chip under test, that is, S401: Perform multiple consecutive read operations on a storage page in each storage block of the flash memory chip sample with a preset read operation number step size; each storage block includes multiple storage pages; S402: Read the data of other storage pages in each storage block except the storage page; S403: Determine whether the bit error rate of the data of the other storage pages exceeds a preset threshold; if not, execute steps S401 to S402 until the bit error rate of the data of the other storage pages exceeds the preset threshold; if yes, execute step S404; S404: Record the total number of read operations performed on the storage pages; the total number of read operations is the read interference resistance of each storage block.

[0064] This embodiment does not limit the specific method for determining whether each of the storage blocks is invalid. For example, it can determine whether the write operation or erase operation performed on each of the storage blocks is successful. If yes, then steps S301 to S303 are executed until the write operation or the erase operation fails. If no, then step S305 is executed.

[0065] This embodiment does not limit the specific method of establishing the correspondence between the read interference resistance capability and the remaining erase count of the flash memory chip based on the read interference resistance capability in the initial state and the read interference resistance capability after erasing each preset erase count step, as well as the remaining erase count in the initial state and the remaining erase count after erasing each preset erase count step. The specific method of the above steps can be determined according to the actual situation. For example, it can be to obtain the relationship curve between the read interference resistance capability and the remaining erase count of the flash memory chip based on the read interference resistance capability in the initial state and the read interference resistance capability after erasing each preset erase count step, as well as the remaining erase count in the initial state and the remaining erase count after erasing each preset erase count step; and fit the relationship curve to establish the correspondence between the read interference resistance capability and the remaining erase count of the flash memory chip.

[0066] It should be noted that the above method can be used to classify flash memory chips by quality, so as to apply them to products used in different scenarios. Flash memory chips with a high limit of erasure cycles are used in fields with high reliability requirements, such as aerospace; flash memory chips with a high limit of erasure cycles are used in fields with low reliability requirements, such as USB flash drives and other products with low read / write frequency.

[0067] Based on the above embodiments, this application pre-establishes a correspondence between the read interference resistance of flash memory chips and the remaining erase count; by obtaining the read interference resistance of flash memory chips, the remaining erase count is determined according to the correspondence, thereby achieving prediction of the lifespan of flash memory chips. Compared with the verification methods in the prior art, this reduces damage to flash memory chips, does not generate additional losses, and the tested flash memory chips can still be used in formal products; it can be applied to flash memory chip quality testing; it can be applied to flash memory quality grade classification to fully utilize the value of different flash memory chips; it can be applied to screening in high-quality demand fields to select flash memory chips that meet the requirements.

[0068] The following example illustrates the flash memory chip lifetime prediction process. Please refer to [link / reference]. Figure 2 , Figure 2 The following is a flowchart illustrating a flash memory chip lifetime prediction method provided in an embodiment of this application. The process is as follows:

[0069] 1. Obtain the relationship curve between the remaining erase cycles and read interference resistance of a certain type of flash memory chip storage block through experimental testing.

[0070] See Figure 3 , Figure 3 This application provides a schematic diagram of a flash memory cell structure, which is a double-layer floating-gate MOS (Metal-Oxide-Semiconductor Field-Effect Transistor). A floating gate layer for storing electrons is formed on the semiconductor where current conducts unidirectionally between the source and drain. The floating gate layer is surrounded by insulating layers on top and bottom, thus locking electrons within the floating gate layer to achieve the purpose of storing information. However, erasing the memory cell causes the tunnel oxide film to age, eventually preventing the electrons from being locked in the floating gate layer and thus hindering the correct storage of information.

[0071] In a flash memory chip, multiple memory cells form a memory page; multiple memory pages form a memory block. Due to the structure of flash memory chips, when a memory page is read, a voltage is applied to the control electrode of other memory pages within the same memory block, creating a strong electric field between the floating gate and the substrate. This field may attract some electrons to the floating gate. As the number of reads of a memory page increases, more electrons from other memory pages within the same block enter the floating gate layer, eventually causing changes in the data state, which means data errors—this is read interference. As the number of erase cycles of a memory block increases, the tunnel oxide film of the memory cells in that block ages, weakening its ability to block electrons from entering the floating gate layer, thus reducing its read interference immunity. Therefore, there is a certain correlation between the remaining erase cycles of a memory block and its read interference immunity.

[0072] For the specific implementation process, please refer to Figure 4 , Figure 4 This application provides a flowchart illustrating the relationship between the remaining erase cycles and read interference immunity of a flash memory chip. The flash memory chip used in this process is a sample of flash memory chips for obtaining this relationship.

[0073] (1) Fill the flash memory chip with data to completely fill the valid storage block (including each storage page).

[0074] (2) Test the read interference resistance capability of each valid storage block and record the results. The read interference resistance capability recorded here includes the read interference resistance capability before erasure (the first read interference resistance capability recorded), that is, the read interference resistance capability in the initial state, and the read interference resistance capability after each k erasures.

[0075] The relationship between the remaining erase cycles and read interference resistance is not identical for every type of flash memory chip. However, flash memory chips of the same type have largely the same design, manufacturing process, and raw materials, so the relationship between the remaining erase cycles and read interference resistance is generally consistent. To predict the remaining erase cycles and quantify read interference resistance, a page within a block is repeatedly read until other pages in the same block experience an additional m bits of error. The total number of read operations, n, performed on that page at this point represents the read interference resistance of the block. Note: Here, m is a pre-set value based on experience.

[0076] For the test process of the read interference resistance capability of a certain storage block, please refer to Figure 5 , Figure 5 A flowchart illustrating the process of detecting the read interference resistance of a storage block, as provided in this application embodiment:

[0077] 1) Read a specified memory page p times consecutively. The number of consecutive reads p is preset, usually from several hundred to several thousand times. The smaller the number of reads, the higher the precision, but the longer the time taken.

[0078] 2) Read data from other pages in the same memory block.

[0079] 3) Check if the number of bit errors in the read data exceeds m. The value m is also preset, usually set to tens to hundreds, and the value m is fixed throughout the entire testing, verification and prediction process.

[0080] 4) Record the total number of read operations on the specified storage page, which is the read interference resistance of the storage block.

[0081] (3) Erase each valid storage block k times. The number of erasures k is also preset. Generally, this value is in the tens to hundreds. The smaller the value of k, the higher the precision and the longer the time.

[0082] (4) Determine whether each storage block is invalid. If not, continue to repeat the previous test process. If yes, end the test.

[0083] (5) Record the faulty storage block and its erase count. This storage block is considered invalid and will not participate in subsequent tests. The erase count recorded here includes the maximum number of erases for this storage block, i.e., the remaining number of erases in the initial state, and the remaining number of erases after every k erases.

[0084] (6) Based on the above test results, we can obtain... Figure 6 , Figure 6This application provides a graph showing the relationship between the remaining erase cycles and read interference immunity of a flash memory chip. Based on the obtained relationship between read interference immunity and remaining erase cycles, tests and predictions can be made for this type of flash memory chip.

[0085] 2. Perform read interference immunity testing on each block of the flash memory chip under test. For the read interference immunity testing process for a single block, please refer to [link to relevant documentation]. Figure 5 The flash memory chip used in this process is the flash memory chip being tested.

[0086] (1) Read a specified memory page p times consecutively. The number of consecutive reads p is preset, usually from several hundred to several thousand times. The smaller the number of reads, the higher the precision, but the longer the time.

[0087] (2) Read data from other storage pages in the same storage block.

[0088] (3) Check whether the number of bit errors in the read data exceeds m. The value m is also preset, usually set to tens to hundreds, and the value m is fixed throughout the test verification and prediction process.

[0089] (4) Record the total number of read operations on the specified storage page, which is the read interference resistance of the storage block.

[0090] 3. After obtaining the read interference resistance of each memory block, compare the relationship curves (see...). Figure 4 Determine the remaining number of erases for each storage block.

[0091] 4. Take the average of the remaining erase counts of all storage blocks as the lifespan of the tested flash memory chip.

[0092] The following describes a flash memory chip lifetime prediction device, apparatus, and computer-readable storage medium provided in the embodiments of this application. The flash memory chip lifetime prediction device, apparatus, and computer-readable storage medium described below can be referred to in correspondence with the flash memory chip lifetime prediction method described above.

[0093] Please refer to Figure 7 , Figure 7 This application provides a structural block diagram of a flash memory chip lifetime prediction device, which may include:

[0094] The data acquisition module 100 is used to perform read interference resistance test on each storage block of the flash memory chip under test, and to acquire the read interference resistance capability of each storage block;

[0095] The lifetime prediction module 200 is used to determine the remaining number of erases for each storage block based on a pre-established correspondence between the read interference resistance capability and the remaining number of erases of the flash memory chip, and to take the average of the remaining number of erases of all storage blocks as the lifetime of the flash memory chip under test.

[0096] Based on the above embodiments, this application pre-establishes a correspondence between the read interference resistance of flash memory chips and the remaining erase count; by obtaining the read interference resistance of flash memory chips, the remaining erase count is determined according to the correspondence, thereby achieving prediction of the lifespan of flash memory chips. Compared with the verification methods in the prior art, this reduces damage to flash memory chips, does not generate additional losses, and the tested flash memory chips can still be used in formal products; it can be applied to flash memory chip quality testing; it can be applied to flash memory quality grade classification to fully utilize the value of different flash memory chips; it can be applied to screening in high-quality demand fields to select flash memory chips that meet the requirements.

[0097] Based on the above embodiments, the data acquisition module may include:

[0098] A read operation unit is used to perform multiple consecutive read operations on a storage page in each storage block of the flash memory chip under test, with a preset read operation number step size; each storage block includes multiple storage pages.

[0099] A data read unit is used to read data from other storage pages within each storage block, excluding the storage page itself.

[0100] The error quantity judgment unit is used to determine whether the bit error quantity of the data in the other storage pages exceeds a preset threshold; if not, the read operation unit to the read data unit is executed until the bit error quantity of the data in the other storage pages exceeds the preset threshold; if so, the record anti-read interference capability unit is executed.

[0101] A read interference resistance recording unit is used to record the total number of read operations performed on the storage page; the total number of read interference resistance is the capability of each storage block.

[0102] Based on the above embodiments, the lifetime prediction module may further include:

[0103] A write operation module is used to fill each storage block in the flash memory chip sample with data; the flash memory chip sample includes multiple storage blocks; each storage block is a valid storage block.

[0104] A read interference resistance module is used to test the read interference resistance of each storage block and record the read interference resistance of each storage block; wherein, the first read interference resistance recorded is the read interference resistance in the initial state.

[0105] The erase operation module is used to erase each of the storage blocks multiple times consecutively at a preset erase count step;

[0106] The status determination module is used to determine whether each of the storage blocks has failed; if not, the write operation module to the erase operation module is executed until the storage block fails; if yes, the module for recording the remaining number of erases is executed.

[0107] The module for recording the remaining erase counts is used to record the total number of times each of the storage blocks is erased and the remaining erase counts after erasing each preset erase count step; the total number of erase counts is the remaining erase counts in the initial state;

[0108] The relationship establishment module is used to establish the correspondence between the read interference resistance capability and the remaining erase count of the flash memory chip based on the read interference resistance capability in the initial state and the read interference resistance capability after erasing each preset erase count step, as well as the remaining erase count in the initial state and the remaining erase count after erasing each preset erase count step.

[0109] Based on the above embodiments, the status judgment module is specifically used to determine whether the write operation or erase operation performed on each of the storage blocks is successful; if so, the write operation module is executed to the erase operation module until the write operation or the erase operation fails; if not, the module for recording the remaining erase count is executed.

[0110] Based on the above embodiments, the relationship establishment module may include:

[0111] The relationship curve acquisition unit is used to obtain the relationship curve between the read interference resistance capability and the remaining erase count of the flash memory chip based on the read interference resistance capability in the initial state and the read interference resistance capability after erasing each preset erase count step, as well as the remaining erase count in the initial state and the remaining erase count after erasing each preset erase count step.

[0112] The relationship curve fitting unit is used to fit the relationship curve and establish the correspondence between the read interference resistance of the flash memory chip and the remaining number of erase cycles.

[0113] Based on the above embodiments, this application also provides a flash memory chip lifetime prediction device, including: a memory and a processor, wherein the memory is used to store a computer program; the processor is used to execute the computer program to implement the steps of the flash memory chip lifetime prediction method described in the above embodiments. Of course, the flash memory chip lifetime prediction device may also include various necessary network interfaces, power supplies, and other components.

[0114] This application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the steps of the flash memory chip lifetime prediction method described in the above embodiments. The storage medium may include various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0115] This document uses specific examples to illustrate the principles and implementation methods of this application, and the various embodiments are progressively related. Each embodiment focuses on the differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, please refer to the corresponding method section description. The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. For those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0116] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A method for predicting the lifetime of flash memory chips, characterized in that, include: Each memory block of the flash memory chip under test is subjected to read interference resistance test to obtain the read interference resistance capability of each memory block; Based on the pre-established correspondence between the read interference resistance of flash memory chips and the remaining erase count, the remaining erase count of each storage block is determined, and the average of the remaining erase counts of all storage blocks is taken as the lifetime of the flash memory chip under test. Before determining the remaining erase count of each storage block based on a pre-established correspondence between the read interference resistance of flash memory chips and the remaining erase count, and taking the average of the remaining erase counts of all storage blocks as the lifetime of the flash memory chip under test, the method further includes: S301: Fill each storage block in the flash memory chip sample with data; the flash memory chip sample includes multiple storage blocks; the storage blocks are valid storage blocks. S302: Perform a read interference resistance test on each of the storage blocks and record the read interference resistance of each of the storage blocks; wherein, the first recorded read interference resistance is the read interference resistance in the initial state; S303: Each storage block is erased multiple times consecutively with a preset erase count step size; S304: Determine whether each of the storage blocks has failed; if not, execute steps S301 to S303 until the storage block fails; if yes, execute step S305. S305: Record the total number of times each of the storage blocks is erased and the remaining number of erases after erasing each of the preset erase count steps; the total number of erases is the remaining number of erases in the initial state; S306: Based on the read interference resistance capability in the initial state and the read interference resistance capability after erasing each preset erase count step, as well as the remaining erase count in the initial state and the remaining erase count after erasing each preset erase count step, establish the correspondence between the read interference resistance capability and the remaining erase count of the flash memory chip.

2. The flash memory chip lifetime prediction method according to claim 1, characterized in that, The process of performing read interference resistance tests on each memory block of the flash memory chip under test to obtain the read interference resistance capability of each memory block includes: S201: Perform multiple consecutive read operations on a storage page in each storage block of the flash memory chip under test, with a preset read operation step size; each storage block includes multiple storage pages; S202: Read the data of the other storage pages in each storage block, excluding the storage page itself; S203: Determine whether the number of bit errors in the data of the other storage pages exceeds a preset threshold; if not, execute steps S201 to S202 until the number of bit errors in the data of the other storage pages exceeds the preset threshold; if yes, execute step S204. S204: Record the total number of read operations performed on the storage page; the total number of read operations is the read interference resistance of each storage block.

3. The flash memory chip lifetime prediction method according to claim 1, characterized in that, Step S304 includes: Determine whether the write or erase operation performed on each of the storage blocks was successful; if so, execute steps S301 to S303 until the write or erase operation fails; if not, execute step S305.

4. The flash memory chip lifetime prediction method according to claim 1, characterized in that, Step S306 includes: Based on the read interference resistance capability in the initial state and the read interference resistance capability after erasing each preset erase count step, as well as the remaining erase count in the initial state and the remaining erase count after erasing each preset erase count step, the relationship curve between the read interference resistance capability and the remaining erase count of the flash memory chip is obtained. The relationship curves are fitted to establish the correspondence between the read interference resistance of flash memory chips and the remaining number of erase cycles.

5. A flash memory chip lifetime prediction device, characterized in that, include: The data acquisition module is used to perform read interference resistance tests on each storage block of the flash memory chip under test, and to acquire the read interference resistance capability of each storage block; The lifetime prediction module is used to determine the remaining erase count of each storage block based on a pre-established correspondence between the read interference resistance capability and the remaining erase count of the flash memory chip, and to take the average of the remaining erase counts of all storage blocks as the lifetime of the flash memory chip under test. Before the lifetime prediction module, it also includes: A write operation module is used to fill each storage block in the flash memory chip sample with data; the flash memory chip sample includes multiple storage blocks; each storage block is a valid storage block. A read interference resistance module is used to test the read interference resistance of each storage block and record the read interference resistance of each storage block; wherein, the first recorded read interference resistance is the read interference resistance in the initial state. The erase operation module is used to erase each of the storage blocks multiple times consecutively at a preset erase count step; The status determination module is used to determine whether each of the storage blocks has failed; if not, the write operation module to the erase operation module is executed until the storage block fails; if yes, the module for recording the remaining number of erases is executed. The module for recording the remaining erase counts is used to record the total number of times each of the storage blocks is erased and the remaining erase counts after erasing each of the preset erase count steps; the total number of times is the remaining erase counts in the initial state; The relationship establishment module is used to establish a correspondence between the anti-read interference capability and the remaining erase count of the flash memory chip based on the anti-read interference capability in the initial state and the anti-read interference capability after erasing each preset erase count step, as well as the remaining erase count in the initial state and the remaining erase count after erasing each preset erase count step.

6. The flash memory chip lifetime prediction device according to claim 5, characterized in that, The data acquisition module includes: A read operation unit is used to perform multiple consecutive read operations on a storage page in each storage block of the flash memory chip under test, with a preset read operation number step size; each storage block includes multiple storage pages. A data read unit is used to read data from other storage pages within each storage block, excluding the storage page itself. The error quantity judgment unit is used to determine whether the bit error quantity of the data in the other storage pages exceeds a preset threshold; if not, the read operation unit to the read data unit is executed until the bit error quantity of the data in the other storage pages exceeds the preset threshold; if so, the record anti-read interference capability unit is executed. A read interference resistance recording unit is used to record the total number of read operations performed on the storage page; the total number of read interference resistance is the capability of each storage block.

7. A flash memory chip lifetime prediction device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the flash memory chip lifetime prediction method as described in any one of claims 1 to 4 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the flash memory chip lifetime prediction method as described in any one of claims 1 to 4.

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