Wafer defect positioning method

Abstract

This disclosure provides a wafer defect localization method, which includes: obtaining the initial inspection coordinates of grain markers and defects in the initial inspection coordinate system from the initial inspection result file of the wafer defect detection; dividing the wafer into multiple partitions according to the coordinate distribution of the initial inspection coordinates, each partition including a specified number of key points, the key points including grain markers and / or defects; calculating the transformation matrix of the key points of each partition, the transformation matrix being used for coordinate transformation between the initial inspection coordinate system and the re-inspection coordinate system; for any partition, obtaining the transformation matrix of any point in that partition other than the key points based on the transformation matrix of the key points of that partition; and converting the initial inspection coordinates of the defect into re-inspection coordinates in the re-inspection coordinate system using the defect transformation matrix. This wafer defect localization method can reduce the impact of nonlinear errors in the initial inspection equipment and the re-inspection equipment on wafer defect localization, achieving accurate defect localization.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a method for locating wafer defects. Background Technology

[0002] In semiconductor manufacturing, wafer defect detection is required. Typically, a preliminary inspection device is used for initial defect detection, followed by a secondary inspection device. These devices can be optical inspection equipment or electron beam inspection equipment. After the preliminary inspection, the device provides a preliminary inspection result file. When the secondary inspection device performs a secondary defect inspection, it needs to parse the preliminary inspection result file to obtain the defect coordinates in the preliminary inspection coordinate system. This defect coordinates are then converted to the secondary inspection coordinate system using a coordinate transformation algorithm. Based on these coordinates, the motion stage within the secondary inspection device moves to locate the defect within its field of view. Summary of the Invention

[0003] The purpose of this disclosure is to provide a wafer defect localization method, which involves dividing the wafer into partitions, obtaining the transformation matrix of key points in each partition, and then obtaining the transformation matrix of any point within the partition, thereby achieving precise localization of wafer defects.

[0004] At least one embodiment of this disclosure provides a wafer defect localization method, the method comprising: obtaining initial inspection coordinates of grain markers and defects in an initial inspection coordinate system from an initial inspection result file of wafer defect detection; dividing the wafer into multiple partitions according to the coordinate distribution of the initial inspection coordinates, wherein each partition includes a specified number of key points, the key points including grain markers and / or defects; calculating a transformation matrix of key points for each partition, wherein the transformation matrix is ​​used for coordinate transformation between the initial inspection coordinate system and the re-inspection coordinate system; for any partition, obtaining a transformation matrix of any point in the partition other than the key points based on the transformation matrix of the key points of the partition; and converting the initial inspection coordinates of the defects into re-inspection coordinates in the re-inspection coordinate system using the defect transformation matrix.

[0005] For example, in the wafer defect location method provided in at least one embodiment of this disclosure, the key points are located on the edge of the partition, the number of key points is at least three, and the at least three key points are not located on the same straight line.

[0006] For example, in the wafer defect localization method provided in at least one embodiment of this disclosure, the wafer is divided into multiple partitions according to the coordinate distribution of the initial inspection coordinates, including: determining multiple polygonal units according to the initial inspection coordinates of the grain markers and defects, such that any vertex of the polygonal unit is a grain marker or a defect, so as to divide the wafer into partitions with vertices as key points, wherein the number of vertices in each partition is a specified number.

[0007] For example, in the wafer defect localization method provided in at least one embodiment of this disclosure, the transformation matrix of key points of each partition is calculated, including: for any vertex, selecting at least two grain markers and / or defects adjacent to the vertex; obtaining the re-inspection coordinates of the vertex and the selected grain markers and / or defects in the re-inspection coordinate system; and calculating the transformation matrix of the vertex using the initial inspection coordinates and re-inspection coordinates of the vertex and the selected grain markers and / or defects.

[0008] For example, in the wafer defect localization method provided in at least one embodiment of this disclosure, selecting at least two grain markers and / or defects adjacent to the vertex includes: when selecting at least two grain markers adjacent to the vertex, selecting grain markers in at least two grains adjacent to the grain where the vertex is located; when selecting at least two defects adjacent to the vertex, selecting at least two defects close to the vertex; when selecting at least two grain markers and defects adjacent to the vertex, selecting grain markers in at least one grain adjacent to the grain where the vertex is located, and selecting defects in at least one defect close to the vertex.

[0009] For example, in the wafer defect localization method provided in at least one embodiment of this disclosure, obtaining the vertex and the selected grain marker and / or defect in the re-inspection coordinate system includes: moving the vertex and the selected grain marker and / or defect to the center of the field of view of the re-inspection device to obtain the vertex and the selected grain marker and / or defect in the re-inspection coordinate system; calculating the transformation matrix of the vertex using the initial inspection coordinates and the re-inspection coordinates of the vertex and the selected grain marker and / or defect includes: calculating the transformation matrix of the vertex based on a linear transformation algorithm using the initial inspection coordinates and the re-inspection coordinates of the vertex and the selected grain marker and / or defect.

[0010] For example, in the wafer defect location method provided in at least one embodiment of this disclosure, the polygonal unit is a rectangular unit.

[0011] For example, in the wafer defect localization method provided in at least one embodiment of this disclosure, the transformation matrix of any point in the partition other than the key points is obtained by a linear interpolation algorithm based on the transformation matrix of the key points of the partition.

[0012] For example, in the wafer defect location method provided in at least one embodiment of this disclosure, the linear interpolation algorithm is a two-dimensional linear interpolation algorithm; each partition has a common edge with adjacent partitions, and the overall region formed by multiple partitions contains all the grains.

[0013] At least one embodiment of this disclosure also provides another wafer defect location method, comprising: obtaining a first transformation matrix corresponding to a defect on a first wafer using the above-described wafer defect location method; selecting a first marker point on the first wafer and obtaining the first coordinates of the first marker point in a re-inspection coordinate system, wherein the first marker point is at least three die marker points; obtaining the second coordinates of a second marker point on a second wafer at the same position as the first marker point on the first wafer in a re-inspection coordinate system, wherein the second wafer and the first wafer undergo initial inspection using the same initial inspection equipment and the second wafer is a wafer of the same type as the first wafer; obtaining the coordinate deviation between the first wafer and the second wafer after wafer mounting based on the first coordinates and the second coordinates; obtaining the transformation matrix of the defect on the second wafer based on the coordinate deviation and the first transformation matrix; and obtaining the corresponding re-inspection coordinates based on the transformation matrix of the defect on the second wafer.

[0014] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure.

[0015] The wafer defect localization method disclosed herein has the following beneficial effects:

[0016] This wafer defect location method can reduce the impact of nonlinear errors in the initial inspection and re-inspection equipment on wafer defect location, and achieve accurate wafer defect location. Attached Figure Description

[0017] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0018] Figure 1 A schematic flowchart illustrating a wafer defect location method provided for at least one embodiment of this disclosure;

[0019] Figure 2 A schematic flowchart of step S103 provided for at least one embodiment of this disclosure;

[0020] Figure 3 An exemplary schematic diagram of wafer dicing provided for at least one embodiment of this disclosure;

[0021] Figure 4 This is an exemplary schematic diagram for calculating the transformation matrix using a two-dimensional linear interpolation algorithm;

[0022] Figure 5 A schematic block diagram of a wafer defect location device provided in at least one embodiment of this disclosure;

[0023] Figure 6 This is a schematic block diagram of an electronic device provided for some embodiments of this disclosure. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0025] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0026] Existing defect location algorithms suffer from the following technical problems: Firstly, the nonlinearity of wafer defect distribution due to wafer process errors and the nonlinearity of inspection equipment due to mechanical installation errors make it difficult to accurately locate each defect using a unified coordinate transformation matrix. Secondly, inspection equipment introduces measurement errors, including noise from the measurement system and nonlinear errors caused by the system's nonlinearity. While the noise amplitude is relatively small, the presence of nonlinear errors makes it difficult for re-inspection equipment to accurately locate defects. For example, when inspection equipment uses a measurement system to measure the stage position, such systems often employ laser interferometers or grating encoders. The inherent nonlinearity of these systems leads to errors in the calculated defect coordinates. Therefore, existing defect location algorithms struggle to achieve accurate positioning between the initial inspection and re-inspection equipment.

[0027] To address the aforementioned technical problems, at least one embodiment of this disclosure provides a wafer defect localization method. The method includes: obtaining initial inspection coordinates of grain markers and defects in an initial inspection coordinate system from an initial inspection result file of the wafer defect detection; dividing the wafer into multiple partitions based on the coordinate distribution of the initial inspection coordinates, wherein each partition includes a specified number of key points, and the key points include grain markers and / or defects; calculating a transformation matrix for the key points of each partition, wherein the transformation matrix is ​​used for coordinate transformation between the initial inspection coordinate system and the re-inspection coordinate system; for any partition, obtaining a transformation matrix for any point in that partition other than the key points based on the transformation matrix of the key points of that partition; and converting the initial inspection coordinates of the defects into re-inspection coordinates in the re-inspection coordinate system using the defect transformation matrix.

[0028] The wafer defect localization method provided in this embodiment divides the wafer into partitions and obtains the transformation matrix of key points in each partition. This allows for the acquisition of the transformation matrix of any point within a partition, reducing the impact of nonlinear errors in the initial inspection and re-inspection equipment on wafer defect localization and thus achieving accurate wafer defect localization.

[0029] At least one embodiment of this disclosure also provides a wafer defect location device corresponding to the above-described wafer defect location method.

[0030] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0031] Figure 1 This is a schematic flowchart illustrating a wafer defect location method provided for at least one embodiment of the present disclosure.

[0032] like Figure 1 As shown, the wafer defect location method includes the following steps S101 to S105.

[0033] Step S101: Obtain the initial inspection coordinates of the grain markers and defects in the initial inspection coordinate system through the initial inspection result file of the wafer defect detection.

[0034] Grain markers are typically the vertices of the grain, but can also be alignment points on the grain, and may also contain defects.

[0035] In one embodiment, the initial inspection result file provides the coordinates of the grain. These coordinates are equivalent coordinates with a selected grain marker point as the origin and do not include the length and width dimensions of the grain. By multiplying the x-component (the x-component corresponds to the component in the length direction of the grain) and y-component (the y-component corresponds to the component in the width direction of the grain) of the grain coordinates by the length and width of the grain, respectively, the initial inspection coordinates of the grain marker point in the initial inspection coordinate system can be obtained. By adding the initial inspection coordinates of the grain marker point to the local coordinates of the defect in the initial inspection result file, the initial inspection coordinates of the defect (i.e., the coordinates in the wafer coordinate system) can be obtained.

[0036] Step S102: Divide the wafer into multiple partitions according to the coordinate distribution of the initial inspection coordinates.

[0037] For example, the partition can be a polygonal unit or a circular unit. Preferably, the partition is a rectangular unit because the grains in the patterned wafer are rectangular in shape. The rectangular unit matches the shape of the grain, which helps to cover more grains and reduce the possibility of missing grains.

[0038] For example, each partition includes a specified number of key points, which include grain markers and / or defects.

[0039] For example, in some embodiments of this disclosure, the key points are located on the edges of the partitions, the number of key points is at least three, and at least three key points are not located on the same straight line. For example, when the number of key points is four, three or four key points are not located on the same straight line.

[0040] For example, in the case of partitioning into polygonal cells, any vertex of the polygonal cell is a grain marker or defect, so that the wafer is divided into partitions with vertices as key points.

[0041] For example, in some embodiments of this disclosure, each partition has a common edge with adjacent partitions, and the overall region formed by multiple partitions contains all the grains.

[0042] Step S103: Calculate the transformation matrix of the key points of each partition.

[0043] The transformation matrix is ​​used for coordinate transformation between the initial inspection coordinate system and the re-inspection coordinate system.

[0044] For example, when the partition is divided into rectangular units, calculate the transformation matrix for each of the four vertices.

[0045] Step S104: For any partition, obtain the transformation matrix of any point in the partition other than the key points based on the transformation matrix of the key points of the partition.

[0046] Therefore, it can be seen that the transformation matrix of any point in the partition can be obtained through the above steps S101-S104, that is, a series of transformation matrices are generated. This is different from the defect location algorithm that uses a single transformation matrix, so it can reduce the impact of nonlinear error in the detection equipment on defect location.

[0047] For example, in some embodiments of this disclosure, the transformation matrix of any point in the partition other than the key points is obtained by a linear interpolation algorithm based on the transformation matrix of the key points of the partition.

[0048] For example, in some embodiments of this disclosure, the linear interpolation algorithm is a two-dimensional linear interpolation algorithm.

[0049] It should be noted that the linear interpolation algorithm is merely an example, and this disclosure does not impose any limitations on it.

[0050] Step S105: Transform the initial inspection coordinates of the defect into the re-inspection coordinates in the re-inspection coordinate system using the defect transformation matrix.

[0051] For example, based on the positional relationship between the defect and each partition, the transformation matrix of the defect in the partition where the defect is located is obtained, and the re-inspection coordinates of the defect are obtained through the transformation matrix of the defect and the initial inspection coordinates of the defect.

[0052] Figure 2 A schematic flowchart of step S103 provided for at least one embodiment of this disclosure.

[0053] like Figure 2 As shown, step S103 includes the following steps S201 to S203.

[0054] Step S201: For any vertex, select at least two grain markers and / or defects adjacent to that vertex.

[0055] For example, select a grain marker point in at least two grains adjacent to the grain containing the vertex. For example, select at least two grain marker points in at least two adjacent grains, and select only one grain marker point in an adjacent grain.

[0056] For example, select at least two defects that are close to the vertex.

[0057] For example, select a grain marker point in at least one grain adjacent to the grain containing the vertex and at least one defect close to the vertex.

[0058] It should be noted that when selecting defects, they are selected in order of distance from the vertex, from closest to farthest, until a preset number is reached. For example, the two closest and second-closest defects can be selected.

[0059] Step S202: Obtain the re-inspection coordinates of the vertex and the selected grain marker and / or defect in the re-inspection coordinate system.

[0060] For example, in some embodiments of this disclosure, step S202 may include: moving the vertex and the selected grain marker and / or defect to the center of the field of view of the re-inspection device, and obtaining the re-inspection coordinates of the vertex and the selected grain marker and / or defect in the re-inspection coordinate system.

[0061] Step S203: Calculate the transformation matrix of the vertex using the initial and re-inspection coordinates of the selected grain marker and / or defect.

[0062] For example, in some embodiments of this disclosure, step S203 may include: calculating the transformation matrix of the vertex based on a linear transformation algorithm using the vertex and the initial and re-inspection coordinates of the selected grain markers and / or defects.

[0063] Using a linear transformation algorithm to calculate the transformation matrix of a vertex helps to reduce nonlinear errors.

[0064] The following example illustrates the wafer defect location method provided in this disclosure.

[0065] First, the initial inspection coordinates of the grain markers and defects in the initial inspection coordinate system are obtained from the initial inspection result file of the wafer defect detection. The method for obtaining the initial inspection coordinates of the grain markers and defects has already been described above and will not be repeated here.

[0066] Then, based on the coordinate distribution of the initial inspection coordinates, the wafer is divided into multiple rectangular units. The wafer division method is as follows: Figure 3 As shown in the image. Figure 3 As shown, the bolded box represents a rectangular unit (only one rectangular unit is shown; other rectangular units are not illustrated), and this rectangular unit contains 12 grains. For example, the number of grains contained in a polygonal unit depends on the specific coordinate distribution and the final transformation accuracy. The vertices of the rectangular unit are grain markers. Taking the top-left vertex of the rectangular unit as an example, the top-left vertex of the rectangular unit is grain 2 (in...). Figure 3 The grain markers of the rectangle marked with the number 2 are used in the calculation of the transformation matrix of the top left vertex. Two grain markers marked with solid dots are used, namely grain 3 (in the rectangle marked with the number 2). Figure 3 The grain markers (rectangles marked with the number 3) and grain 7 (in) Figure 3 The grain markers are located within the rectangle (marked with the number 7). It should be noted that when selecting a grain marker adjacent to a vertex, the grain corresponding to the selected grain marker does not necessarily need to be within the same rectangular cell.

[0067] In this embodiment, grain markers are used as vertices of the rectangular element, and two adjacent grain markers are selected. For example, in another embodiment, defects can be used as vertices of the rectangular element, and when calculating the transformation matrix of the vertex, the two defects closest to that vertex are selected. For example, in yet another embodiment, grain markers can be used as vertices of the rectangular element, and when calculating the transformation matrix of the vertex, the two defects closest to that vertex are selected. When using rectangular elements, it is preferable to use grain markers as vertices because the analytical defect coordinates have nonlinear errors due to errors in the initial inspection process.

[0068] Then, calculate the transformation matrix of each of the four vertices of the rectangular unit.

[0069] The initial inspection coordinates of the vertices of each rectangular unit have been obtained from the initial inspection result file. By moving the motion table of the re-inspection equipment, the four vertices of the rectangular unit are moved to the center of the re-inspection equipment's field of view to obtain the re-inspection coordinates of the vertices.

[0070] by Figure 3 Taking the top left vertex of the rectangular unit as an example, move this vertex and the two adjacent grain markers to the center of the field of view of the re-inspection equipment to obtain the re-inspection coordinates of these three points. In this way, the initial inspection coordinates and re-inspection coordinates of these three points are obtained. The transformation matrix of the vertex is calculated by establishing equation (1):

[0071]

[0072] The x and y coordinates on the left side of the equal sign are the re-inspection coordinates, and the x′ and y′ coordinates on the right side of the equal sign are the initial inspection coordinates. The 3×3 matrix is ​​the transformation matrix between the initial inspection coordinate system and the re-inspection coordinate system.

[0073] The above steps yield the transformation matrices of all rectangular elements' vertices. Performing two-dimensional linear interpolation on the corresponding elements of the transformation matrices of the four vertices of each rectangular element allows us to obtain the transformation matrix for any point in all rectangular elements except the vertices. When using the two-dimensional linear interpolation algorithm, each element in the transformation matrix is ​​continuous and linearly changes with respect to adjacent positions, and is continuous but generally not differentiable along the common boundary between two adjacent rectangular elements. The transformation matrix for any point in a rectangular element except the vertices is calculated using the two-dimensional linear interpolation algorithm. Figure 4 As shown in the image.

[0074] like Figure 4As shown, the transformation matrices of the four vertices of any rectangular unit have been calculated. During interpolation, interpolation is performed on the elements at corresponding positions. Taking element 'a' in the transformation matrix as an example, the values ​​of a1, a2, a3, and a4 can be obtained from the transformation matrices of the four vertices. Combining these values ​​with the positions of the four vertices of the rectangular unit, the value of element 'a' in the transformation matrix of any point within that rectangular unit can be obtained. Similarly, the values ​​of elements b, c, d, e, and f in the transformation matrix of any point within that rectangular unit can be obtained, thus yielding the transformation matrix for that point.

[0075] For any point within the rectangular cell, the initial coordinates (x, y) can be determined by the four vertices of the rectangular cell (Q, Q). 11 Q 21 Q 12 Q 22 The coordinates of the four vertices are calculated as follows: (x1, y1), (x2, y1), (x1, y2), and (x2, y2).

[0076]

[0077] Finally, the initial inspection coordinates of the defect are transformed into the re-inspection coordinates in the re-inspection coordinate system using the defect transformation matrix.

[0078] In summary, the wafer defect localization method provided in this disclosure can reduce the impact of nonlinear errors in the initial inspection equipment and re-inspection equipment on wafer defect localization by dividing the wafer into partitions and obtaining the transformation matrix of key points in each partition, thereby obtaining the transformation matrix of any point within the partition. This enables precise defect localization.

[0079] At least one embodiment of this disclosure also provides another wafer defect location method, comprising: obtaining a first transformation matrix corresponding to a defect on a first wafer using the above-described wafer defect location method; selecting a first marker point on the first wafer and obtaining the first coordinates of the first marker point in a re-inspection coordinate system, wherein the first marker point is at least three die marker points; obtaining the second coordinates of a second marker point on a second wafer at the same position as the first marker point on the first wafer in a re-inspection coordinate system, wherein the second wafer and the first wafer undergo initial inspection using the same initial inspection equipment and the second wafer is a wafer of the same type as the first wafer; obtaining the coordinate deviation between the first wafer and the second wafer after wafer mounting based on the first coordinates and the second coordinates; obtaining the transformation matrix of the defect on the second wafer based on the coordinate deviation and the first transformation matrix; and obtaining the corresponding re-inspection coordinates based on the transformation matrix of the defect on the second wafer.

[0080] In this embodiment, for wafers of the same type as the first wafer (with the same grain distribution), it is not necessary to use the same wafer defect location method as the first wafer. Instead, the transformation matrix of the first wafer is modified to obtain the transformation matrix of the wafer of the same type. Based on the transformation matrix of the wafer of the same type, the re-inspection coordinates corresponding to the wafer of the same type are obtained, which can save time. For example, the first initial inspection coordinates of the first marker point of the first wafer are obtained from the initial inspection result file of the wafer defect detection. Wafers of the same type also have the same first initial inspection coordinates. That is, the second marker point on the second wafer and the first marker point on the first wafer (in the initial inspection coordinate system, i.e., the wafer coordinate system) have the same position. However, due to some wafer loading deviations after the second wafer is mounted, the position of the second wafer deviates from that of the first wafer, resulting in different coordinates of the second wafer and the first wafer in the re-inspection coordinate system. The coordinates of the second marker point and the first marker point are different in the re-inspection coordinate system of the same re-inspection equipment. That is, the second coordinates are different from the first coordinates. The coordinate deviation is obtained based on the first coordinates and the second coordinates. This coordinate deviation is taken as the coordinate deviation between the first wafer and the second wafer. Therefore, based on the coordinate deviation and the first transformation matrix, the second transformation matrix corresponding to the defect of the second wafer is obtained. Then, the initial inspection coordinates of the defect of the second wafer are converted into re-inspection coordinates through the second transformation matrix.

[0081] In one embodiment, the first marker point is moved to the center of the field of view of the re-inspection device to obtain the re-inspection coordinates of the first marker point, i.e., the first coordinates. The second marker point is moved to the center of the field of view of the re-inspection device to obtain the re-inspection coordinates of the second marker point, i.e., the second coordinates.

[0082] At least one embodiment of this disclosure also provides a wafer defect location device, which includes a processor and a memory. The memory stores computer-executable instructions, which, when executed by the processor, can implement the wafer defect location method provided in at least one embodiment of this disclosure.

[0083] Figure 5 This is a schematic block diagram of a wafer defect location device 500 provided for some embodiments of this disclosure. Figure 5 As shown, the wafer defect location device 500 includes a processor 510 and a memory 520. The memory 520 stores computer-executable instructions (e.g., one or more computer program modules). The processor 510 executes the computer-executable instructions, which, when executed by the processor 510, can perform one or more steps in the wafer defect location method described above. The memory 520 and the processor 510 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0084] For example, processor 510 may be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit with data processing and / or program execution capabilities. For example, the central processing unit (CPU) may be an x86 or ARM architecture. Processor 510 may be a general-purpose processor or a special-purpose processor, capable of controlling other components in wafer defect location equipment 500 to perform desired functions.

[0085] For example, memory 520 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 510 may run one or more computer program modules to implement various functions of the wafer defect location device 500. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0086] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the wafer defect location device 500 can be referred to the description of the wafer defect location method above, and will not be repeated here.

[0087] Figure 6 This is a schematic block diagram of an electronic device provided for some embodiments of this disclosure. The electronic device 600 is, for example, suitable for implementing the wafer defect location method provided in the embodiments of this disclosure. The electronic device 600 may be a terminal device or a computer system, etc. It should be noted that... Figure 6 The illustrated electronic device 600 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments of this disclosure.

[0088] like Figure 6 As shown, electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 610, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 620 or a program loaded from storage device 680 into random access memory (RAM) 630. RAM 630 also stores various programs and data required for the operation of electronic device 600. Processing device 610, ROM 620, and RAM 630 are interconnected via bus 640. Input / output (I / O) interface 650 is also connected to bus 640.

[0089] Typically, the following devices can be connected to I / O interface 650: input devices 660 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 670 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 680 including, for example, magnetic tapes, hard disks, etc.; and communication devices 690. Communication device 690 allows electronic device 600 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although... Figure 6 An electronic device 600 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 600 may alternatively implement or have more or fewer devices.

[0090] For example, according to embodiments of this disclosure, the above-described wafer defect location method can be implemented as a computer software program. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing the above-described wafer defect location method. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 690, or installed from a storage device 680, or installed from a ROM 620. When the computer program is executed by the processing device 610, the functions defined in the wafer defect location method provided by embodiments of this disclosure can be implemented.

[0091] The following points need to be explained:

[0092] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0093] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0094] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A method for locating wafer defects, characterized in that, include: The initial inspection results file of wafer defect detection is used to obtain the grain marker points and the initial inspection coordinates of defects in the initial inspection coordinate system. The grain marker points are the vertices of the grains or alignment points on the grains. Based on the coordinate distribution of the initial inspection coordinates, the wafer is divided into multiple partitions, wherein each partition includes a specified number of key points, and the key points include the grain marker points and / or the defects; Calculate the transformation matrix of the key points of each partition, wherein the transformation matrix is ​​used for coordinate transformation between the initial inspection coordinate system and the re-inspection coordinate system; For any of the aforementioned partitions, the transformation matrix of any point in the partition other than the keypoints is obtained based on the transformation matrix of the keypoints in that partition; and The initial inspection coordinates of the defect are converted into re-inspection coordinates in the re-inspection coordinate system using the defect transformation matrix.

2. The wafer defect location method according to claim 1, characterized in that, The key points are located on the edge of the partition, and there are at least three key points, and at least three key points are not located on the same straight line.

3. The wafer defect location method according to claim 1, characterized in that, Based on the coordinate distribution of the initial inspection coordinates, the wafer is divided into multiple partitions, including: Multiple polygonal units are determined based on the initial inspection coordinates of the grain marker and the defect, such that any vertex of the polygonal unit is either the grain marker or the defect, so as to divide the wafer into partitions with the vertex as the key point, wherein the number of vertices in each partition is a specified number.

4. The wafer defect location method according to claim 3, characterized in that, Calculate the transformation matrix of the key points for each partition, including: For any vertex, select at least two grain markers and / or defects adjacent to that vertex; Obtain the re-inspection coordinates of the vertex and the selected grain marker and / or defect in the re-inspection coordinate system; and The transformation matrix of the vertex is calculated using the initial and re-inspection coordinates of the selected grain marker and / or defect.

5. The wafer defect location method according to claim 4, characterized in that, Select at least two grain markers and / or defects adjacent to the vertex, including: If at least two grain markers adjacent to the vertex are selected, then grain markers in at least two grains adjacent to the grain containing the vertex are selected. When selecting at least two defects adjacent to a vertex, select at least two defects close to the vertex. When selecting at least two grain markers and defects adjacent to the vertex, a grain marker is selected from at least one grain adjacent to the grain containing the vertex, and a defect is selected from at least one defect close to the vertex.

6. The wafer defect location method according to claim 4, characterized in that, Obtaining the re-inspection coordinates of the vertex and the selected grain marker and / or defect in the re-inspection coordinate system includes: Move the vertex and the selected grain marker and / or defect to the center of the field of view of the re-inspection equipment to obtain the re-inspection coordinates of the vertex and the selected grain marker and / or defect in the re-inspection coordinate system; Using the vertex and the initial and re-inspection coordinates of the selected grain markers and / or defects, calculate the transformation matrix of the vertex, including: The transformation matrix of the vertex is calculated based on the linear transformation algorithm using the vertex and the initial and re-inspection coordinates of the selected grain markers and / or defects.

7. The wafer defect location method according to claim 3, characterized in that, The polygonal unit is a rectangular unit.

8. The wafer defect location method according to claim 1, characterized in that, Based on the transformation matrix of the key points in the partition, the transformation matrix of any point in the partition other than the key points is obtained by linear interpolation algorithm.

9. The wafer defect location method according to claim 8, characterized in that, The linear interpolation algorithm is a two-dimensional linear interpolation algorithm; each partition has a common edge with its adjacent partitions, and the overall region formed by the multiple partitions contains all the grains.

10. A method for locating wafer defects, characterized in that, include: The wafer defect location method as described in any one of claims 1-9 is used to obtain the first transformation matrix corresponding to the defect of the first wafer, a first marker point is selected on the first wafer and the first coordinate of the first marker point in the re-inspection coordinate system is obtained, wherein the first marker point is at least three of the said grain marker points; Obtain the second coordinates of the second marker point on the second wafer that is at the same position as the first marker point on the first wafer in the re-inspection coordinate system, wherein the second wafer and the first wafer are initially inspected by the same initial inspection equipment and the second wafer is a wafer of the same type as the first wafer; The coordinate deviation is obtained based on the first coordinate and the second coordinate. The transformation matrix of the defect on the second wafer is obtained based on the coordinate deviation and the first transformation matrix. The corresponding re-inspection coordinate is obtained based on the transformation matrix of the defect on the second wafer.

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