A packaging substrate structure and a method of arranging the same

Abstract

The application relates to the packaging technical field, and more particularly to a packaging substrate structure and a layout method thereof. The packaging substrate structure comprises a multilayer laminated packaging substrate and a plurality of first vias, second vias, third vias, fourth vias and fifth vias penetrating through the multilayer laminated packaging substrate; the first vias and the fourth vias are arranged in a digital region, the second vias and the fifth vias are arranged in an analog region, and the third vias are arranged between the digital region and the analog region to form a ground hole isolation zone. The application integrates digital ground and analog ground, increases the metal area of the ground plane, has good heat dissipation effect, and makes the packaging reflow have a complete reference plane design, which is beneficial to solving the high-temperature problem caused by the less reflow ground plane of a high-power chip, and reduces the crosstalk between the digital region and the analog region.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and more specifically, to a packaging substrate structure and its arrangement method. Background Technology

[0002] A printed circuit board (PCB) is an important electronic component that serves as the support for electronic components and the carrier for their electrical connections. As the name suggests, PCBs are manufactured using electronic printing techniques, hence the name "printed" circuit board.

[0003] Existing technologies for chip substrate packaging that include printed circuit boards employ structures such as digital signal layers, analog signal layers, digital ground, and analog ground. However, most of these designs separate and layer the digital signal layers and analog signal layers, as well as the digital ground and analog ground. While this approach helps reduce crosstalk between digital and analog signals, it also affects the return current of either digital or analog signals and results in a smaller heat dissipation area, thus impacting the transmission of high-speed signals. Summary of the Invention

[0004] Based on the above-mentioned technical problems, the present invention aims to integrate the digital ground and analog ground in the package substrate structure and set a ground hole isolation strip between the digital area and the analog area.

[0005] The first aspect of the present invention provides a method for arranging a packaging substrate structure, the packaging substrate structure including a multilayer stacked packaging substrate and a plurality of first vias, second vias, third vias, fourth vias and fifth vias penetrating the multilayer stacked packaging substrate; the first vias and the fourth vias are arranged in a digital region, the second vias and the fifth vias are arranged in an analog region, and the third vias are deployed between the digital region and the analog region to form a ground via isolation strip.

[0006] In some embodiments of the present invention, the first via is a digital power via and / or a digital signal via, and the second via is an analog power via and / or an analog signal via.

[0007] In some embodiments of the present invention, the third via, the fourth via, and the fifth via are all reference ground vias.

[0008] In some embodiments of the present invention, the multilayer stacked packaging substrate further includes a digital reference ground layer and an analog reference ground layer.

[0009] In some embodiments of the present invention, the fourth via is adjacent to the first via to form a digital signal return path; the fifth via is adjacent to the second via to form an analog signal return path.

[0010] In some embodiments of the present invention, the first via, the second via, the third via, the fourth via, and the fifth via are all metal vias.

[0011] In some embodiments of the present invention, a plurality of first vias, second vias, third vias, fourth vias and fifth vias penetrating the multilayer stacked packaging substrate serve as electrical connections to enable the transmission of digital signals and / or analog signals from the top layer of the substrate to the bottom layer of the substrate.

[0012] A second aspect of the present invention provides a method for arranging a packaging substrate structure, the method comprising:

[0013] A multilayer encapsulation substrate is provided with a plurality of first vias, second vias, third vias, fourth vias and fifth vias penetrating the multilayer encapsulation substrate;

[0014] The first via and the fourth via are configured in the digital region, the second via and the fifth via are configured in the analog region, and the third via is deployed between the digital region and the analog region to form a ground via isolation strip, wherein the first via is a digital power via and / or a digital signal via, and the second via is an analog power via and / or an analog signal via.

[0015] The fourth via is placed adjacent to the first via to form a digital signal return path, and the fifth via is placed adjacent to the second via to form an analog signal return path.

[0016] Among them, the first via, the second via, the third via, the fourth via, and the fifth via are all metal vias.

[0017] A third aspect of the present invention provides a computer device, including a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor causes the processor to perform the arrangement method of the packaging substrate structure described in the embodiments of the present invention.

[0018] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the arrangement method of the packaging substrate structure described in the embodiments of the present invention.

[0019] The technical solutions provided in this application embodiment have at least the following technical effects or advantages:

[0020] This application protects a packaging substrate structure and its arrangement method. The packaging substrate structure includes a multilayered packaging substrate and a plurality of first vias, second vias, third vias, fourth vias, and fifth vias penetrating the multilayered packaging substrate. The first vias and the fourth vias are disposed in a digital region, the second vias and the fifth vias are disposed in an analog region, and the third via is deployed between the digital region and the analog region to form a ground via isolation strip. The first vias are digital power vias and / or digital signal vias, the second vias are analog power vias and / or analog signal vias, and the third, fourth, and fifth vias are all reference ground vias, so that the ground of the digital region, the ground of the analog region, and the ground of the isolation region are merged into a common reference ground, which physically achieves interconnection, thereby providing better signal return and heat dissipation effects. This application integrates the reference ground of the digital region and the reference ground of the analog region into a single design, increasing the metal area of ​​the ground plane and improving heat dissipation. This allows for a more complete reference plane design for the package reflow, which is beneficial for high-power chips that suffer from high temperatures due to insufficient reflow ground planes. It also reduces crosstalk caused by the interconnection between the reference ground of the digital region and the reference ground of the analog region, thereby ensuring better transmission of high-speed signals.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0022] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0023] Figure 1 This illustration shows a schematic diagram of a packaging substrate structure in which a ground hole isolation strip is provided between a digital region and an analog region according to an exemplary embodiment of this application;

[0024] Figure 2 A schematic diagram illustrating the complete isolation between digital and analog regions in the prior art is shown;

[0025] Figure 3 This illustration shows a schematic diagram of a packaging substrate structure in which no ground hole isolation strip is provided between the digital region and the analog region according to an exemplary embodiment of this application;

[0026] Figure 4 This invention provides a schematic diagram illustrating a three-dimensional effect of another packaging substrate structure in an exemplary embodiment of this application.

[0027] Figure 5This illustration shows a schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0028] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of this application. It will be apparent to those skilled in the art that this application can be implemented without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described.

[0029] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0030] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. The drawings are not drawn to scale, and some details may be enlarged and omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0031] The following is in conjunction with the instruction manual appendix. Figure 1 - Appendix Figure 5 Several embodiments are given to describe exemplary implementations according to this application. It should be noted that the following application scenarios are shown only to facilitate understanding of the spirit and principles of this application, and the implementations of this application are not limited in any way. Rather, the implementations of this application can be applied to any applicable scenario.

[0032] Existing technologies for chip substrate packaging that include printed circuit boards employ structures such as digital signal layers, analog signal layers, digital ground, and analog ground. However, most of these designs separate and layer the digital signal layers and analog signal layers, as well as the digital ground and analog ground. While this approach helps reduce crosstalk between digital and analog signals, it also affects the return current of either digital or analog signals and results in a smaller heat dissipation area, thus impacting the transmission of high-speed signals.

[0033] Therefore, in some exemplary embodiments of this application, a packaging substrate structure is provided, with reference to Figure 1 The packaging substrate structure includes a multilayered packaging substrate and a plurality of first vias, second vias, third vias, fourth vias, and fifth vias penetrating the multilayered packaging substrate. The first and fourth vias are disposed in a digital region, the second and fifth vias are disposed in an analog region, and the third via is deployed between the digital and analog regions to form a ground isolation band. The digital region includes a digital power region and a digital signal region, and the analog region includes an analog power region and an analog signal region. The first via is a digital power via and / or a digital signal via, and the second via is an analog power via and / or an analog signal via. The third, fourth, and fifth vias are all reference ground vias. The fourth via is adjacent to the first via to form a digital signal return path; the fifth via is adjacent to the second via to form an analog signal return path. Figure 2 This illustration shows a current technology where the digital and analog regions are completely isolated, a traditional practice in existing packaging substrates. This involves separating the digital ground and analog ground in an isolated design. The advantage of this is that digital ground noise will not leak into the noise-sensitive analog area, interfering with the analog signal. For example... Figure 2 As shown, the peak current in the digital region reaches 1.42A, while the leakage current in the analog region is 0A. However, due to the segmentation of the ground plane, analog signals may cross the segment, leading to signal integrity loss and a significant degradation in signal quality. Furthermore, traditional designs are not conducive to heat dissipation. In contrast, due to the introduction of the isolation ground via (third via) in this application, the ground of the digital region, the ground of the analog region, and the ground of the isolation region are merged into a common reference ground, achieving physical interconnection and providing better signal return and heat dissipation. Moreover, analog signals will not cross the segment design, ensuring signal transmission quality.

[0034] In a preferred embodiment, the multilayer packaging substrate includes a digital reference ground layer, an analog reference ground layer, and of course, a signal layer, with digital and analog signals integrated into a single layer. Preferably, the first via, the second via, the third via, the fourth via, and the fifth via are all metal vias. Figure 1 As shown, with the above-described package substrate structure, the peak current in the digital region reaches 1.42A, while the leakage current in the analog region is 0.08A. In comparison, as... Figure 3 As shown, a combined digital and analog ground design is used, but no ground via isolation strip is set. The leakage current in the analog area is 0.4A. It can be seen that the third via (i.e....) Figure 1 The isolation vias (forming isolation holes) effectively reduce noise and current crosstalk caused by the merging of the reference ground of the digital region and the reference ground of the analog region; that is, the isolation vias effectively reduce crosstalk. Furthermore, the merging of the digital power region and the analog power region, as well as the digital signal region and the analog signal region, increases the metal area of ​​the package structure, enabling the package return current to have a complete reference ground plane design.

[0035] Figure 4 The three-dimensional effect of the encapsulation structure is illustrated, as follows: Figure 4 As shown, the surface of the top substrate of the multilayer packaging structure has many vias. The part framed by the white line is the third via described in each embodiment. The right side of the third via is the analog area, and the left side of the third via is the digital area. Figure 4 The digital area shown is larger than the analog area, but in practice, there is no fixed limit to the area of ​​either. The first via can be a digital signal via, a digital power via, or both. Similarly, the second via can be an analog signal via, an analog power via, or both. Figure 4 Multiple vias (first, second, third, fourth, and fifth vias) penetrating the multi-layered packaging substrate serve as electrical connections, forming a connection path for signals or power from the top layer of the substrate to the solder balls at the bottom layer. Furthermore, the fourth and fifth vias also function as return current channels; the fourth via facilitates the return current for digital signals, and the fifth via facilitates the return current for analog signals. The third via provides isolation between digital and analog ground. Additionally, the horizontal wiring for digital and analog signals in the signal layer is designed according to existing technology and is not specifically limited here.

[0036] Next, refer to Figure 1The digital reference formation has multiple fourth vias, and the analog reference formation has multiple fifth vias. The fourth vias are adjacent to the first vias to form a return current for digital signals, and the fifth vias are adjacent to the second vias to form a return current for analog signals. Figure 1 The triangle in the diagram represents the digital return ground via, i.e., the fourth ground via, and the pentagon represents the analog return ground via, i.e., the fifth ground via. The barrel shape represents the third via in the ground hole isolation strip. This embodiment integrates the analog and digital grounds, increasing the metal area of ​​the ground plane. It combines the return planes of two different attributes, digital and analog, resulting in good heat dissipation and providing a complete reference ground plane for the package return ground layer. This is beneficial for high-power chips that suffer from high temperatures due to insufficient return ground planes. Furthermore, by adding a certain density of ground for isolation, it reduces crosstalk between the digital and analog regions, which is beneficial for high-speed signal transmission. In other words, this application is a balanced design that improves upon the problems of traditional designs while retaining the advantages of low crosstalk. Moreover, digital and analog grounds can be integrated within the package substrate design, providing a very robust and reliable ground plane, offering an optimal solution for power delivery and high-speed signal reference.

[0037] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention.

[0038] In some exemplary embodiments of this application, a method for arranging a packaging substrate structure is also provided, the method comprising:

[0039] S1. A multi-layered encapsulation substrate and a plurality of first vias, second vias, third vias, fourth vias and fifth vias penetrating the multi-layered encapsulation substrate are arranged.

[0040] S2. The first via and the fourth via are configured in the digital region, the second via and the fifth via are configured in the analog region, and the third via is deployed between the digital region and the analog region to form a ground via isolation strip, wherein the first via is a digital power via and / or a digital signal via, the second via is an analog power via and / or an analog signal via, and the third, fourth, and fifth vias are all reference ground vias;

[0041] S3. Make the fourth via adjacent to the first via to form a digital signal return path, and make the fifth via adjacent to the second via to form an analog signal return path.

[0042] Among them, the first via, the second via, the third via, the fourth via, and the fifth via are all metal vias.

[0043] This arrangement method, by merging digital and analog grounds, increases the metal area of ​​the ground plane, resulting in better heat dissipation. It also allows for a complete reference ground plane design for the package return ground layer, which helps address the high-temperature issues caused by insufficient return ground planes in high-power chips. Furthermore, it reduces crosstalk between the digital and analog regions. The integration of digital and analog grounds within the package substrate design provides a very robust and reliable ground plane, offering an optimal solution for power delivery and high-speed signal reference. Therefore, as a flexible implementation, this arrangement method can be used for switch chip packaging, reducing crosstalk between analog and digital ground currents in switch chips.

[0044] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application.

[0045] Please refer to the following. Figure 5 This illustrates a schematic diagram of a computer device provided by some embodiments of this application. For example... Figure 5 As shown, the computer device 2 includes: a processor 200, a memory 201, a bus 202, and a communication interface 203. The processor 200, the communication interface 203, and the memory 201 are connected via the bus 202. The memory 201 stores a computer program that can run on the processor 200. When the processor 200 runs the computer program, it executes the arrangement method of the packaging substrate structure provided in any of the foregoing embodiments of this application.

[0046] This application also provides a computer-readable storage medium corresponding to the packaging substrate structure provided in the foregoing embodiments, which stores a computer program. When the computer program is run by a processor, it executes the arrangement method of the packaging substrate structure provided in any of the foregoing embodiments. The arrangement method includes: arranging a multilayered packaging substrate and a plurality of first vias, second vias, third vias, fourth vias, and fifth vias penetrating the multilayered packaging substrate; arranging the first vias and the fourth vias in a digital region, and arranging the second vias and the fifth vias in an analog region; and arranging the first vias and the fourth vias in a digital region. The third via is deployed between the digital region and the analog region to form a ground via isolation strip. The first via is a digital power via and / or a digital signal via, the second via is an analog power via and / or an analog signal via, and the third, fourth, and fifth vias are all reference ground vias. The fourth via is positioned adjacent to the first via to form a digital signal return path, and the fifth via is positioned adjacent to the second via to form an analog signal return path. The first, second, third, fourth, and fifth vias are all metallic vias.

[0047] In addition, examples of the computer-readable storage medium may include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be described in detail here.

[0048] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the arrangement method of the packaging substrate structure provided in any of the foregoing embodiments.

[0049] It should be noted that the algorithms and displays provided herein are not inherently related to any particular computer, virtual device, or other equipment. Various general-purpose devices can also be used in conjunction with the teachings herein. The required structure for constructing such devices is obvious from the above description. Furthermore, this application is not directed to any particular programming language. It should be understood that the content of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of this application. Numerous specific details are set forth in the specification provided herein. However, it is to be understood that embodiments of this application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0050] Those skilled in the art will understand that the various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art should understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the virtual machine creation apparatus according to embodiments of this application.

[0051] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A packaging substrate structure, characterized in that, The packaging substrate structure includes a multilayer stacked packaging substrate and a plurality of first vias, second vias, third vias, fourth vias and fifth vias penetrating the multilayer stacked packaging substrate; The first via and the fourth via are configured in the digital region, the second via and the fifth via are configured in the analog region, and the third via is deployed between the digital region and the analog region to form a ground via isolation strip; wherein, the first via is a digital power via and / or a digital signal via, and the second via is an analog power via and / or an analog signal via; the third, fourth, and fifth vias are all reference ground vias; the fourth via is adjacent to the first via to form a digital signal return path; the fifth via is adjacent to the second via to form an analog signal return path; the first, second, third, fourth, and fifth vias are all metallic vias.

2. The packaging substrate structure according to claim 1, characterized in that, The multilayer stacked packaging substrate also includes a digital reference ground layer and an analog reference ground layer.

3. The packaging substrate structure according to claim 1, characterized in that, Multiple first vias, second vias, third vias, fourth vias, and fifth vias that penetrate the multilayer packaging substrate serve as electrical connections to enable the transmission of digital signals and / or analog signals from the top layer of the substrate to the bottom layer.

4. A method for arranging a packaging substrate structure, characterized in that, The method includes: A multilayer encapsulation substrate is provided with a plurality of first vias, second vias, third vias, fourth vias and fifth vias penetrating the multilayer encapsulation substrate; The first via and the fourth via are configured in the digital region, the second via and the fifth via are configured in the analog region, and the third via is deployed between the digital region and the analog region to form a ground via isolation strip. The first via is a digital power via and / or a digital signal via, the second via is an analog power via and / or an analog signal via, and the third, fourth, and fifth vias are all reference ground vias. The fourth via is placed adjacent to the first via to form a digital signal return path, and the fifth via is placed adjacent to the second via to form an analog signal return path. Among them, the first via, the second via, the third via, the fourth via, and the fifth via are all metal vias.

5. A computer device, comprising a memory and a processor, characterized in that, The memory stores computer-readable instructions that, when executed by the processor, cause the processor to perform the method as described in claim 4.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method as described in claim 4.

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