Integrated chip structure and method of forming an integrated chip structure

Abstract

The present invention relates to integrated chip structures. An integrated chip structure includes one or more interconnects disposed within a dielectric structure above a substrate. A bond pad has a top surface arranged along a top surface of the dielectric structure. Wherein, as viewed in cross-section, the top surface of the bond pad includes a plurality of discrete top surface segments laterally separated from one another by a non-zero distance extending between inner sidewalls of the bond pad. The dielectric structure is disposed directly between the inner sidewalls of the bond pad. Embodiments of the present invention also provide methods of forming integrated chip structures.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated chip structures and methods for forming integrated chip structures. Background Technology

[0002] Multidimensional integrated circuits (MICs) are integrated circuits with multiple substrates and / or dies that are vertically stacked on top of each other and electrically interconnected. Through the electrically interconnected stacked substrates and / or dies, MICs function as a single device, offering improved performance, reduced power consumption, and a smaller footprint compared to conventional integrated circuits. Therefore, MICs provide a pathway to continue meeting the performance / cost requirements of next-generation integrated circuits. Summary of the Invention

[0003] Some embodiments of the present invention provide an integrated chip structure comprising: one or more interconnects disposed within a dielectric structure above a substrate; bonding pads having a top surface arranged along a top surface of the dielectric structure, wherein, as observed in a cross-sectional view, the top surface of the bonding pads comprises a plurality of discrete top surface segments laterally separated from each other by one or more non-zero distances extending between inner sidewalls of the bonding pads; and wherein the dielectric structure is directly disposed between the inner sidewalls of the bonding pads.

[0004] Other embodiments of the present invention provide an integrated chip structure comprising: one or more interconnects surrounded by a dielectric structure disposed on a substrate; a bonding pad surrounded by the dielectric structure, wherein the bonding pad includes a lower segment extending between outer edges of a lower sidewall disposed along the bottom of the bonding pad, and an upper segment extending between outer edges of an upper sidewall disposed along the top of the bonding pad; and wherein the upper segment of the bonding pad includes one or more inner sidewalls spaced apart by a non-zero distance between edges of a top surface of the bonding pad, the dielectric structure being located between the edges of the top surface of the bonding pad.

[0005] Some embodiments of the present invention provide a method for forming an integrated chip structure, comprising: forming a first bonding pad opening in a first upper dielectric structure formed above a lower dielectric structure, the lower dielectric structure surrounding one or more interconnects above a substrate; forming a first barrier layer and a first conductive core in the first bonding pad opening; forming a second upper dielectric structure above the first upper dielectric structure; forming a second bonding pad opening in the second upper dielectric structure to expose the first conductive core and to surround one or more inner sidewalls of the second upper dielectric structure; forming a barrier material and a conductive material in the second bonding pad opening; and removing portions of the barrier material and the conductive material, wherein the removal of the barrier material and the conductive material forms a bonding pad having inner sidewalls, the inner sidewalls of the bonding pad forming one or more cavities extending into the bonding pad.

[0006] Further embodiments of the present invention provide slotted bonding pads in a stacked wafer structure. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, aspects of the invention will be best understood from the following detailed description. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1A to 1B Some embodiments of an integrated chip structure including bonding pads having one or more cavities configured to reduce the recess of the bonding pads are shown.

[0009] Figure 2 Cross-sectional views of some embodiments of a multidimensional integrated chip structure including bonding pads each having one or more cavities are shown.

[0010] Figures 3A to 3B Additional embodiments of an integrated chip structure including bonding pads with one or more cavities are shown.

[0011] Figures 4A to 4B Additional embodiments of an integrated chip structure including bonding pads with one or more cavities are shown.

[0012] Figure 5 Cross-sectional views of some embodiments of a multidimensional integrated chip structure including bonding pads each having one or more cavities are shown.

[0013] Figures 6A to 6B Additional embodiments of an integrated chip structure including bonding pads with one or more cavities are shown.

[0014] Figures 7A to 7C Top views of some additional embodiments of the disclosed bonding pads, including one or more cavities, are shown. These cavities have different shapes and / or spatial configurations.

[0015] Figures 8A to 8C Additional embodiments of an integrated chip structure including bonding pads with one or more cavities are shown.

[0016] Figures 9A to 9C Top views of some additional embodiments of the disclosed bonding pads, including one or more cavities, are shown. These cavities have different shapes and / or spatial configurations.

[0017] Figures 10A to 10C Additional embodiments of an integrated chip structure including exposed bonding pads with one or more cavities are shown.

[0018] Figures 11 to 18 Some embodiments of a method for forming an integrated chip structure including the disclosed bonding pads having one or more cavities configured to reduce the recess of the bonding pads are shown.

[0019] Figures 19 to 28 Additional embodiments of a method for forming an integrated chip structure including the disclosed bonding pads having one or more cavities configured to reduce the recess of the bonding pads are shown.

[0020] Figures 29 to 35 Additional embodiments of a method for forming an integrated chip structure including the disclosed bonding pads having one or more cavities configured to reduce the recess of the bonding pads are shown.

[0021] Figure 36 A flowchart illustrating some embodiments of a method for forming an integrated chip structure including the disclosed bonding pads having one or more cavities configured to reduce the recess of the bonding pads is shown. Detailed Implementation

[0022] The following disclosure provides numerous embodiments or instances of different components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other) element or component as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0024] Multidimensional integrated chip structures (e.g., chip-on-wafer (CoW) structures, wafer-on-wafer (WoW) structures, three-dimensional integrated chip (3DIC) structures, etc.) are formed by stacking multiple integrated chip dies on top of each other. Multiple integrated chip dies are individually manufactured by forming interconnects within an ILD layer on one or more semiconductor substrates. One or more bonding pads are then formed on top of the interconnects. One or more bonding pads can be formed by depositing a conductive material (e.g., a metal such as copper) within the openings of the bonding pads, which are made of dielectric material extending through the ILD layer, followed by a planarization process (e.g., chemical mechanical planarization). The bonding pads of the integrated chip dies are then brought together to electrically couple the integrated chip dies.

[0025] When a planarization process is performed on the conductive material (e.g., copper) of one or more bonding pads, a polishing pad comes into contact with both the conductive material and the surrounding dielectric material. Because the conductive material is softer than the surrounding dielectric material, the polishing pad will remove the conductive material at a faster rate than the surrounding dielectric, resulting in a concavity or "dent" in the conductive material. This concavity results in one or more bonding pads having a recessed upper surface that descends below the top of the surrounding dielectric material. When the bonding pads of two integrated circuit dies are subsequently placed together, a gap (e.g., a spacer) may form between the recessed upper surfaces of the bonding pads. This gap can lead to poor electrical connections between the integrated circuit dies, which can degrade the performance of the multidimensional integrated circuit and / or ultimately cause the multidimensional integrated circuit to fail.

[0026] This invention relates to an integrated chip structure with bonding pads configured to mitigate recesses along the top of the bonding pads. The disclosed integrated chip structure includes bonding pads disposed within a dielectric structure above a substrate. The bonding pads include inner sidewalls defining one or more cavities surrounded by the bonding pads. The one or more cavities are filled with a dielectric material of the dielectric structure such that the top surface of the bonding pads includes a plurality of discrete top surface segments, as observed in the cross-sectional view, which are laterally spaced from each other by the dielectric structure. Because the dielectric material is disposed directly between the plurality of discrete top surface segments, the polishing pads used to form the bonding pads will have relatively small overlap with each of the top surface segments. The relatively small overlap reduces recesses in the individual top surface segments. When the bonding pads of individual integrated chip dies are placed together, the reduced recesses reduce the formation of voids, thereby improving the electrical performance and / or reliability of the multidimensional integrated chip structure.

[0027] Figure 1A Cross-sectional views of some embodiments of an integrated chip structure 100 including bonding pads having one or more cavities configured to reduce the recess of the bonding pads are shown.

[0028] The integrated chip structure 100 includes one or more interconnects 106 disposed within a dielectric structure 104 above a substrate 102. Bonding pads 112 are disposed within the dielectric structure 104 above the one or more interconnects 106. The bonding pads 112 include a top surface disposed along the top surface of the dielectric structure 104. In some embodiments, the top surface of the bonding pads 112 is substantially coplanar with the top surface of the dielectric structure 104. The plurality of interconnects 106 includes a topmost interconnect 108 disposed within the dielectric structure 104. The topmost interconnect 108 includes an upper surface 108u that directly contacts the bottommost surface of the bonding pads 112. In some embodiments, the upper surface 108u may extend continuously beyond the outermost outer wall of the bottom surface of the bonding pads 112.

[0029] In some embodiments, the bonding pad 112 includes a lower segment 114 and an upper segment 116 located above the lower segment 114. The lower segment 114 extends laterally between the relatively outermost edges of the lower sidewalls of the bonding pad 112. The lower sidewalls are disposed along the bottom of the bonding pad 112. The upper segment 116 extends laterally between the relatively outermost edges of the upper sidewalls of the bonding pad 112. The upper sidewalls are disposed along the top of the bonding pad 112. In some embodiments, the upper segment 116 includes a bottom surface extending laterally from directly above the lower segment 114 beyond one or more lower sidewalls.

[0030] The bonding pad 112 also includes one or more inner sidewalls 112s that define one or more cavities 113 (e.g., one or more slits) within the top surface of the bonding pad 112. (As along...) Figure 1A As observed in the cross-sectional view, one or more cavities 113 divide the top surface of the bonding pad 112 into a plurality of discrete top surface segments 112u. Dielectric structures 104 are disposed within the one or more cavities 113 and directly between the plurality of discrete top surface segments 112u. In some embodiments, the bottommost surface of the bonding pad 112 extends laterally and continuously beyond one or more inner sidewalls 112s defining the one or more cavities 113.

[0031] Because the dielectric structure 104 is directly disposed between the plurality of discrete top surface segments 112u, the overlap between each of the discrete top surface segments 112u and the chemical mechanical polishing (CMP) pad used to form the bonding pad 112 is smaller than the overlap between a bonding pad without one or more cavities and the CMP pad used to form the bonding pad. This smaller overlap reduces the recesses in each of the discrete top surface segments 112u. When the bonding pad 112 contacts another bonding pad, the reduced recesses mitigate void formation, thereby improving the electrical performance and / or reliability of the multidimensional integrated chip structure.

[0032] Figure 1B The section cut along section line A-A' is shown. Figure 1A A top view 118 of some embodiments of the integrated chip structure 100. In some embodiments, Figure 1A The cross-sectional view can be taken along the cross-sectional line B-B' of the top view 118.

[0033] As shown in top view 118, the bonding pad 112 is surrounded by a dielectric structure 104. An upper segment 116 of the bonding pad 112 extends around one or more cavities 113 (e.g., one or more slits) filled with the dielectric structure 104. In some embodiments, the upper segment 116 extends continuously between the outermost walls of the bonding pad 112 along a first direction 120 and / or along a second direction 122 perpendicular to the first direction 120. In some embodiments, the upper segment 116 continuously surrounds one or more cavities 113 in a closed and uninterrupted loop. The upper segment 116 is located directly above a portion of the lower segment 114. In some embodiments, one or more cavities 113 may also be located directly above a portion of the lower segment 114.

[0034] Figure 2 Cross-sectional views of some embodiments of a multidimensional integrated chip structure 200 including bonding pads with one or more cavities are shown.

[0035] The multidimensional integrated chip structure 200 includes a first integrated chip (IC) die 202 having a plurality of interconnects 106 disposed within a dielectric structure 104 on a substrate 102. In some embodiments, the plurality of interconnects 106 includes a topmost interconnect 108 that contacts a bonding pad 112 disposed within the dielectric structure 104. In some embodiments, the plurality of interconnects 106 may electrically couple the bonding pad 112 to one or more semiconductor devices 204 on and / or within the substrate 102. In various embodiments, the one or more semiconductor devices 204 may include transistor devices (e.g., planar FETs, FinFETs, gate all-around (GAA) devices, etc.), image sensor devices (e.g., photodiodes), MEMS (microelectromechanical systems) devices, etc. The bonding pad 112 has a top surface facing away from the substrate 102. The top surface of the bonding pad 112 is disposed along the top surface of the dielectric structure 104 facing away from the substrate 102. As observed in the cross-sectional view, the top surface comprises multiple discrete top surface segments separated by one or more cavities 113 filled with dielectric structures 104.

[0036] The multidimensional integrated chip structure 200 also includes a second IC die 208 having a plurality of additional interconnects 214 disposed within an additional dielectric structure 210 on an additional substrate 212. In some embodiments, one or more additional interconnects 214 include an additional topmost interconnect 216 that contacts additional bonding pads 218 disposed within the additional dielectric structure 210. In some embodiments, the plurality of additional interconnects 214 can electrically couple the additional bonding pads 218 to one or more additional semiconductor devices 222 (e.g., transistor devices, image sensor devices, MEMS devices, etc.) on and / or within the additional substrate 212. The additional bonding pads 218 have a surface facing away from the additional substrate 212. The surface of the additional bonding pads 218 is disposed along the surface of the additional dielectric structure 210 facing away from the additional substrate 212. As observed in the cross-sectional view, the top surface of the additional bonding pads 218 includes a plurality of discrete segments separated by one or more additional cavities 220 filled with the additional dielectric structure 210.

[0037] In some embodiments, one or more dummy bonding pads 206 may be arranged along the top surface of the dielectric structure 104 opposite to the substrate 102. The one or more dummy pads 206 may have the same layout as the bonding pads 112. For example, the one or more dummy bonding pads 206 may have a top surface opposite to the substrate 102, and as observed in the cross-sectional view, this top surface includes a plurality of discrete top surface segments spaced apart by one or more cavities filled with the dielectric structure 104. In some embodiments, one or more additional dummy bonding pads 224 may be arranged along the surface of the additional dielectric structure 210 opposite to the additional substrate 212. The one or more additional dummy bonding pads 224 may have the same layout as the additional bonding pads 218.

[0038] A first IC die 202 is bonded to a second IC die 208 along a hybrid bonding interface, in which bonding pad 112 contacts an additional bonding pad 218 along a conductive interface, and dielectric structure 104 contacts an additional dielectric structure 210 along a dielectric interface. In some embodiments, dielectric structure 104 within one or more cavities 113 contacts additional dielectric structure 210 within one or more additional cavities 220 along a dielectric interface. In some embodiments, a plurality of discrete top surface segments of bonding pad 112 may laterally overlap with a plurality of discrete surface segments of additional bonding pad 218. In some embodiments, at least one sidewall of additional bonding pad 218 may be located directly above the top surface of bonding pad 112.

[0039] Because the dielectric structure 104 is directly disposed between multiple discrete top surface segments of the bonding pad 112, the top surface of the bonding pad 112 is substantially flat. Similarly, because the additional dielectric structure 210 is directly disposed between multiple discrete segments of the additional bonding pad 218, the surface of the additional bonding pad 218 is substantially flat. The substantially flat top surface of the bonding pad 112 and the substantially flat surface of the additional bonding pad 218 reduce the voids along the interface between the bonding pad 112 and the additional bonding pad 218, thereby improving the electrical performance and / or reliability of the multidimensional integrated chip structure 200.

[0040] Figure 3A Cross-sectional views of some additional embodiments of the disclosed bonding pads, including one or more cavities, are shown.

[0041] The integrated chip structure 300 includes a dielectric structure 104 located above a substrate 102. In some embodiments, the dielectric structure 104 includes a plurality of interlayer dielectric (ILD) layers 104a-104d stacked on top of each other. The plurality of ILD layers 104a-104d may be perpendicularly separated from each other by a plurality of etch stop layers 105a-105c. A top dielectric layer 105t is disposed along the top of the dielectric structure 104. In some embodiments, the plurality of ILD layers 104a-104d may include one or more of silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), porous dielectric materials, etc. In some embodiments, the plurality of etch stop layers 105a-105c and / or the top dielectric layer 105t may include nitrides (e.g., silicon nitride, silicon oxynitride, etc.), carbides (e.g., silicon carbide, silicon oxycarbide, etc.), etc.

[0042] Multiple interconnects 106 are disposed within the lower dielectric structure 104L of the dielectric structure 104. In some embodiments, the multiple interconnects 106 include conductive contacts, interconnect lines, interconnect vias, etc. The multiple interconnects 106 include a topmost interconnect 108. In some embodiments, the topmost interconnect 108 may include a conductive core 108c surrounded by a barrier layer 108b. In some embodiments, the conductive core 108c may include copper, aluminum, etc. In some embodiments, the barrier layer 108b may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0043] A bonding pad 112 is disposed within the dielectric structure 104 and contacts the topmost interconnect 108. The bonding pad 112 includes a top surface disposed along the top surface of the dielectric structure 104. In some embodiments, the bonding pad 112 includes a lower segment 114 and an upper segment 116 located above the lower segment 114. The lower segment 114 extends laterally between the outermost edges of the lower sidewalls coupled to one or more bottom surfaces of the bonding pad 112. In some embodiments, the lower segment 114 may have a first width 302 in the range of about 0.2 μm to about 3 μm, about 0.4 μm to about 2 μm, or other similar values. The upper segment 116 extends laterally between the outermost edges of the upper outermost sidewalls of the bonding pad 112. In some embodiments, the upper segment 116 may have a second width 304 greater than about 1.5 μm, greater than about 2 μm, or other similar values. Typically, bonding pads with relatively large top surfaces (e.g., greater than about 1.5 μm) exhibit significant recesses, which can lead to void formation. However, by having one or more cavities 113 filled with dielectric structures 104 within the upper segment 116 of the bonding pad 112, the bonding pad 112 can have a relatively large size (e.g., greater than about 1.5 μm), which provides electrical connectivity to another IC while avoiding significant recesses.

[0044] The lower surface of the upper segment 116 physically contacts the upper surface of the lower segment 114. In some embodiments, the lower segment 114 may include a first barrier layer 114b surrounding the first conductive core 114c. In some embodiments, the upper segment 116 may include a second barrier layer 116b surrounding the second conductive core 116c. In some embodiments, the second barrier layer 116b may be directly disposed between the second conductive core 116c and the first conductive core 114c. In some embodiments, the first conductive core 114c and the second conductive core 116c may include copper, aluminum, tungsten, etc. In some embodiments, the first barrier layer 114b and the second barrier layer 116b may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0045] In some embodiments, the second barrier layer 116b of the upper segment 116 may extend a non-zero distance below the top of the first barrier layer 114b and / or the first conductive core 114c. In some embodiments, the first conductive core 114c may extend along the sidewall of the second barrier layer 116b. In some such embodiments, the upper outermost wall of the bonding pad 112 may extend vertically below the top of the lower sidewall of the bonding pad 112.

[0046] The top surface of the bonding pad 112 includes a plurality of discrete top surface segments 112u, which are laterally separated from each other by one or more cavities 113 defined by the inner sidewalls 112s of the bonding pad 112. In some embodiments, the upper segment 116 may also include discrete lower surfaces separated from each other by one or more cavities 113, as observed in the cross-sectional view. In some embodiments, the discrete lower surfaces may each have a third width 306 in the range of about 0.2 μm to about 3 μm, about 0.4 μm to about 2 μm, or other similar values. Dielectric structures 104 are disposed directly between the inner sidewalls 112s of the bonding pad 112.

[0047] Figure 3B The section cut along section line A-A' is shown. Figure 3A A top view 308 of some embodiments of the integrated chip structure 300. In some embodiments, Figure 3A The cross-sectional view can be taken along the cross-sectional line B-B' of the top view 308.

[0048] As shown in top view 308, the bonding pad 112 is surrounded by a dielectric structure 104. An upper segment 116 of the bonding pad 112 extends around the boundary of the lower segment 114. In some embodiments, one or more cavities 113 extend through the upper segment 116 and are positioned directly over a portion of the lower segment 114. In some embodiments, the one or more cavities 113 may be rectangular cavities surrounded by a continuous ring of the upper segment 116. In some embodiments, the continuous ring of the upper segment 116 extends along the outer periphery of the upper segment 116.

[0049] Figure 4A Cross-sectional views of some additional embodiments of an integrated chip structure 400 including disclosed bonding pads with one or more cavities are shown.

[0050] The integrated chip structure 400 includes a bonding pad 112 disposed within a dielectric structure 104 above a substrate 102. The bonding pad 112 includes a lower segment 114 and an upper segment 116 located above the lower segment 114. The lower segment 114 extends laterally between two opposite outermost walls coupled to the bottom of the bonding pad 112. The upper segment 116 extends laterally between two opposite outermost walls coupled to the top of the bonding pad 112. In some embodiments, the upper segment 116 includes inner sidewalls 112s coupled to a horizontally extending surface 112h facing away from the substrate 102 to form one or more cavities 113 within the top surface of the bonding pad 112. The horizontally extending surface 112h is located directly above the bottom surface 117 of the upper segment 116.

[0051] In some embodiments, one or more cavities 113 have a depth less than the height of the upper segment 116, such that the upper segment 116 extends along the bottom of one or more cavities 113. In some embodiments, the bottom surface 117 of the upper segment 116 extends laterally and continuously beyond the relatively outermost wall of the lower segment 114 and beyond one or more cavities 113. In some embodiments, the bottom surface 117 completely covers the top surface of the lower segment 114.

[0052] Figure 4B The section cut along section line A-A' is shown. Figure 4A A top view 402 of some embodiments of the integrated chip structure 400. In some embodiments, Figure 4A The cross-sectional view can be taken along the cross-sectional line B-B' of the top view 402.

[0053] As shown in top view 402, the bonding pad 112 is surrounded by a dielectric structure 104. The upper segment 116 of the bonding pad 112 extends around the boundary of the lower segment 114. In some embodiments, one or more cavities 113 extend through the upper segment 116 and are positioned directly above the lower segment 114.

[0054] Figure 5 Cross-sectional views of some additional embodiments of a multidimensional integrated chip structure 500 are shown, which includes disclosed bonding pads each having one or more cavities.

[0055] The multidimensional integrated chip structure 500 includes a first IC die 202 having a bonding pad 112 disposed above a substrate 102 within a dielectric structure 104. The bonding pad 112 has a top surface facing away from the substrate 102. The top surface includes a plurality of discrete top surface segments, which are separated by one or more cavities 113 defined by sidewalls and horizontally extending surfaces of the bonding pad 112. The one or more cavities 113 are filled with the dielectric structure 104.

[0056] The multidimensional integrated chip structure 500 also includes a second IC die 208 having additional bonding pads 218 disposed within an additional dielectric structure 210 on an additional substrate 212. The additional bonding pads 218 have a surface facing away from the additional substrate 212. This surface includes a plurality of discrete segments separated by one or more additional cavities 220 defined by sidewalls and horizontally extending surfaces of the additional bonding pads 218. The one or more additional cavities 220 are filled with the additional dielectric structure 210.

[0057] In some embodiments, one or more dummy bonding pads 206 may be arranged along the top surface of the dielectric structure 104 opposite to the substrate 102. The one or more dummy bonding pads 206 may have the same layout as the bonding pads 112. In some embodiments, one or more additional dummy bonding pads 224 may be arranged along the surface of the additional dielectric structure 210 opposite to the additional substrate 212. The one or more additional dummy bonding pads 224 may have the same layout as the additional bonding pads 218.

[0058] A first IC die 202 is bonded to a second IC die 208 along a hybrid bonding interface in which bonding pad 112 contacts an additional bonding pad 218 along a conductive interface, and dielectric structure 104 contacts an additional dielectric structure 210 along a dielectric interface (e.g., dielectric structure 104 within one or more cavities 113 contacts additional dielectric structure 210 within one or more additional cavities 220 along a dielectric interface). In some embodiments, the plurality of discrete top surface segments of bonding pad 112 and / or the plurality of discrete segments of additional bonding pad 218 may have slight recesses, which result in the formation of small gaps 502 along the conductive interface. However, because the one or more cavities mitigate the CMP recesses, the small gaps 502 have minimal impact on the performance of the multidimensional integrated chip structure 500. In some embodiments, the small gaps 502 may extend laterally along a portion but not all of the conductive interface (e.g., the small gaps 502 may be recessed by a non-zero distance from opposite sides of the plurality of discrete top surface segments of bonding pad 112).

[0059] Although the disclosed multidimensional integrated chip structures (e.g., multidimensional integrated chip structures 200 and / or 500) are shown as three-dimensional integrated chip (3DIC) structures, it should be understood that the disclosed bonding pads are not limited to this structure, but can be integrated within various multidimensional integrated chip structures. For example, in alternative embodiments, the disclosed bonding pads can be integrated within a chip-on-wafer (CoW) structure, a wafer-on-wafer (WoW) structure, etc.

[0060] Figure 6A Cross-sectional views of some additional embodiments of an integrated chip structure 600 including disclosed bonding pads with one or more cavities are shown.

[0061] The integrated chip structure 600 includes one or more interconnects 106 disposed within a dielectric structure 104 above a substrate 102. In some embodiments, the dielectric structure 104 includes a plurality of interlayer dielectric (ILD) layers 104a-104e stacked on top of each other. The plurality of ILD layers 104a-104e may be perpendicularly separated from each other by a plurality of etch stop layers 105a-105d. A top dielectric layer 105t is disposed along the top of the dielectric structure 104.

[0062] A bonding pad 112 is disposed within the dielectric structure 104. The bonding pad 112 contacts the topmost interconnect 108 of a plurality of interconnects 106. The bonding pad 112 includes a lower segment 114 and an upper segment 116 located above the lower segment 114. The lower segment 114 extends laterally between opposing outer walls coupled to the bottom of the bonding pad 112. The upper segment 116 extends laterally between opposing outermost walls of the bonding pad 112. In some embodiments, the lower segment 114 may include a first barrier layer 114b surrounding a first conductive core 114c. In some embodiments, the upper segment 116 may include a portion of the first barrier layer 114b surrounding a portion of the first conductive core 114c and a second barrier layer 116b surrounding a second conductive core 116c. In some embodiments, the second barrier layer 116b may be directly disposed between the second conductive core 116c and the first conductive core 114c. In some embodiments, the second barrier layer 116b may contact the first conductive core 114c at a location above the bottom of the upper segment 116 (e.g., above the bottom of the opposite outermost wall of the bonding pad 112). In some embodiments, the second barrier layer 116b may extend a non-zero distance below the top of the first barrier layer 114b and / or the first conductive core 114c.

[0063] In some embodiments, one or more cavities 113 extend into the upper segment 116 of the bonding pad 112. The one or more cavities may be defined by the sidewalls of the second barrier layer 116b and the upper surface of the first conductive core 114c. The one or more cavities may have a height less than the height of the upper segment 116 (e.g., less than the height of the relative outermost wall of the bonding pad 112).

[0064] Figure 6B The section cut along section line A-A' is shown. Figure 6A A top view 602 of some embodiments of the integrated chip structure 600. In some embodiments, Figure 6A The cross-sectional view can be taken along the cross-sectional line B-B' of the top view 602.

[0065] As shown in top view 602, the upper segment 116 of the bonding pad 112 is surrounded by a dielectric structure 104 and extends around the boundary of the lower segment 114. In some embodiments, one or more cavities 113 extend through the upper segment 116 and are positioned directly above a portion of the lower segment 114. In some embodiments, the one or more cavities 113 may be a rectangular region surrounded by a continuous ring of the upper segment 116. In some embodiments, the one or more cavities 113 may be positioned directly above a portion of the lower segment 114.

[0066] It should be understood that, in various embodiments, the upper segment of the disclosed bonding pad may have inner sidewalls defining one or more cavities with different shapes and / or spatial configurations. Figures 7A to 7C Top views of various embodiments of the disclosed integrated chip structure with bonding pads having one or more cavities having different shapes and / or spatial configurations are shown.

[0067] Figure 7A A top view 700 of some embodiments of an integrated chip structure including a bonding pad 112 with one or more cavities 113 is shown, each having a square shape. The square-shaped cavities extend along a first direction 120 to a first distance 702 and along a second direction 122 perpendicular to the first direction 120 to a second distance 704. The first distance 702 is approximately equal to the second distance 704. The square-shaped cavities are surrounded by a continuous outer ring of an upper segment 116 of the bonding pad 112 surrounding the square-shaped cavities. In some embodiments, the upper segment 116 of the bonding pad 112 includes a cross-shaped region coupled to the outer ring of the upper segment 116. The cross-shaped region separates the one or more cavities 113 from each other along the first direction 120 and along the second direction 122. The square-shaped cavities and the cross-shaped region are located directly above a lower segment 114 of the bonding pad 112. The outer ring of the upper segment 116 is laterally outside the lower segment 114 of the bonding pad 112.

[0068] Figure 7B A top view 706 shows some embodiments of an integrated chip structure including bonding pads 112 with one or more cavities 113, each having a cross shape. The cross-shaped cavities are surrounded by discrete portions of an upper segment 116 of the bonding pads 112. These discrete portions of the upper segment 116 of the bonding pads 112 are located directly above a lower segment 114 of the bonding pads 112. The cross-shaped cavities have branches that completely separate the discrete portions of the upper segment 116 from each other along a first direction 120 and along a second direction 122 perpendicular to the first direction 120.

[0069] Figure 7C A top view 708 is shown of some embodiments of an integrated chip structure including bonding pads 112 with one or more cavities 113, each having a square shape. The square-shaped cavities are surrounded by a continuous outer ring of an upper segment 116 of the bonding pad 112 surrounding the square-shaped cavities. The square-shaped cavities are positioned directly above a square-shaped cavity extending through a lower segment 114 of the bonding pad 112. In some embodiments, the lower segment of the bonding pad 112 has the same pattern as the upper segment 116 of the bonding pad 112.

[0070] Figure 8AA top view of some additional embodiments of an integrated chip structure 800 including disclosed bonding pads with one or more cavities is shown.

[0071] The integrated chip structure 800 includes bonding pads 112 disposed within a dielectric structure 104. The bonding pads include a lower segment 114 and an upper segment 116 located above the lower segment 114. The upper segment 116 includes an inner sidewall defining one or more cavities 113 surrounded by a continuous ring of the bonding pads 112. The one or more cavities 113 are filled with the dielectric structure 104.

[0072] The lower segment 114 may include a plurality of discrete lower segments 114d arranged in an array. The plurality of discrete lower segments 114d may be separated by a first distance 802 along a first direction 120 and by a second distance 804 along a second direction 122 perpendicular to the first direction 120. In some embodiments, the plurality of discrete lower segments 114d may include square-shaped segments. In other embodiments (not shown), the plurality of discrete lower segments 114d may include other shapes (e.g., circular segments, octagonal segments, polygonal segments, etc.). In some embodiments, the plurality of discrete lower segments 114d are completely covered by the upper segment 116.

[0073] Figure 8B The diagram shows the section intercepted along line A-A'. Figure 8A Cross-sectional view 806 of some additional embodiments of the integrated chip structure.

[0074] As shown in cross-sectional view 806, one or more cavities 113 extend completely through the bonding pad 112 such that portions of the dielectric structure 104 located between one or more sidewalls of the bonding pad 112 extend continuously from the top of the bonding pad 112 to the bottom of the bonding pad 112. In some embodiments, portions of the dielectric structure 104 located between one or more sidewalls of the bonding pad 112 extend continuously from the top of the bonding pad 112 to the topmost interconnect 108 within the dielectric structure 104.

[0075] The lower segment 114 of the bonding pad 112 extends laterally in a first direction 120 between the opposing outer edges of the lower sidewalls of the bonding pad 112. The lower sidewalls are arranged along the bottom of the bonding pad 112. In some embodiments, a plurality of discrete lower segments 114d include a plurality of discrete lower surfaces contacting the topmost interconnect 108 and a plurality of discrete upper surfaces contacting the upper segment 116. Both the plurality of discrete lower surfaces and the plurality of discrete upper surfaces of the plurality of lower segments 114d are laterally separated from each other in the first direction 120 by a dielectric structure 104.

[0076] The upper segment 116 of the bonding pad 112 extends laterally between the outermost outer walls of the bonding pad 112. The outermost outer walls are arranged along the top of the bonding pad 112. In some embodiments, the upper segment 116 may include a plurality of discrete lower surfaces laterally spaced apart from each other by dielectric structure 104. In some embodiments, the plurality of discrete lower surfaces of the upper segment 116 may each have a width greater than a corresponding upper surface of a plurality of discrete upper surfaces of a plurality of discrete lower segments 114d. In some embodiments, the plurality of discrete lower surfaces of the upper segment 116 may each extend beyond one or more outer edges of the plurality of discrete upper surfaces of a plurality of discrete lower segments 114d.

[0077] Figure 8C This shows the section along line B-B'. Figure 8A Cross-sectional view 808 of some additional embodiments of the integrated chip structure.

[0078] As shown in cross-sectional view 808, a plurality of discrete lower segments 114d within the lower segment 114 are separated from each other along a second direction 122. The upper segment 116 has a lower surface that extends continuously along the second direction 122 above the plurality of discrete lower segments 114d.

[0079] It should be understood that, in various embodiments, the lower segment of the disclosed bonding pad may have multiple discrete lower segments with different shapes and / or spatial configurations. Figures 9A to 9C A top view of some additional embodiments of the disclosed bonding pads, including one or more cavities, is shown.

[0080] Figure 9A A top view 900 of an integrated chip structure is shown, the structure including bonding pads 112 having a lower segment 114 and an upper segment 116. The lower segment 114 includes a plurality of discrete lower segments 114d arranged in an array extending in a first direction 120 and a second direction 122. The upper segment 116 is positioned directly above the plurality of discrete lower segments 114d within the array. The upper segment 116 includes sidewalls defining one or more cavities 113 having a rectangular shape. The rectangular cavities extend along the first direction 120 to a first distance 902 and along the second direction 122 to a second distance 904. The second distance 904 is smaller than the first distance 902. The rectangular cavities are surrounded by a continuous outer ring of the upper segment 116. Cross bars extend between portions of the continuous outer ring of the upper segment 116 to separate the rectangular cavities.

[0081] Figure 9BA top view 906 is shown of an integrated chip structure including bonding pads 112 having a lower segment 114 and an upper segment 116. The lower segment 114 includes a plurality of discrete lower segments 114d arranged in an array extending in a first direction 120 and a second direction 122. The upper segment 116 is positioned directly above the plurality of discrete lower segments 114d within the array. The upper segment 116 includes sidewalls defining one or more cavities 113, each having a square shape. The square-shaped cavities are surrounded by a continuous outer ring of the upper segment 116. A cross-shaped region of the upper segment 116 is surrounded by the continuous outer ring and separates the square-shaped cavities along the first direction 120 and along the second direction 122. The cross-shaped region includes a first cross bar extending in the first direction 120 and a second cross bar extending in the second direction 122.

[0082] Figure 9C A top view 908 of an integrated chip structure including bonding pads 112 having a lower segment 114 and an upper segment 116 is shown. The lower segment 114 includes a plurality of discrete lower segments 114d arranged in an array extending in a first direction 120 and a second direction 122. The upper segment 116 includes a plurality of discrete upper segments 116d arranged in an array extending in the first direction 120 and the second direction 122. In some embodiments, the plurality of discrete lower segments 114d may have a smaller size than the plurality of discrete upper segments 116d. In some such embodiments, the plurality of discrete upper segments 116d may completely cover the plurality of discrete lower segments 114d.

[0083] Figure 10A A top view of some additional embodiments of an integrated chip structure 1000 including disclosed bonding pads with one or more cavities is shown.

[0084] The integrated chip structure 1000 includes bonding pads 112 disposed within a dielectric structure 104. The bonding pads 112 include a lower segment 114 and an upper segment 116 located above the lower segment 114. The lower segment 114 and the upper segment 116 each include an inner sidewall defining one or more cavities 113 filled with the dielectric structure 104. In some embodiments, the one or more cavities 113 each have a rectangular shape. The lower segment 114 and the upper segment 116 extend continuously around the one or more cavities 113 in a closed loop. In some embodiments, the lower segment 114 is completely covered by the upper segment 116. In some such embodiments, the inner sidewalls of the lower segment 114 are spaced further apart along a first direction and along a second direction than the inner sidewalls of the upper segment 116.

[0085] In some embodiments, the upper segment 116 includes an upper outer ring segment surrounding one or more cavities 113 and an upper crossbar extending between portions of the upper outer ring segment. The lower segment 114 extends continuously around one or more cavities 113 in a closed loop manner. In some embodiments, the lower segment 114 includes a lower outer ring segment surrounding one or more cavities and a lower crossbar extending between portions of the lower outer ring segment. The upper outer ring segment is located directly above the lower outer ring segment, and the upper crossbar is located directly above the lower crossbar. The one or more cavities 113 are filled with a dielectric structure 104.

[0086] Figure 10B The diagram shows the section cut along line A-A'. Figure 10A Cross-sectional view 1002 of some additional embodiments of the integrated chip structure 1000.

[0087] As shown in cross-sectional view 1002, the bonding pad 112 includes a lower segment 114 having discrete upper surfaces and an upper segment 116 having discrete lower surfaces. The plurality of discrete upper surfaces and the plurality of discrete lower surfaces are separated from each other by dielectric structure 104 along a first direction 120.

[0088] Figure 10C The diagram shows the section taken along line B-B'. Figure 10A Cross-sectional view 1004 of some additional embodiments of the integrated chip structure.

[0089] As shown in cross-sectional view 1004, the bonding pad 112 includes a lower segment 114 having a lower surface and an upper surface extending between the outer edges of a lower sidewall coupled to a lower surface, respectively. The bonding pad 112 also includes an upper segment 116 having a lower surface and an upper surface extending between the outer edges of an upper sidewall coupled to a top surface, respectively. In some embodiments, the lower surface of the upper segment 116 extends continuously beyond the opposite side of the upper surface of the lower segment 114.

[0090] Figures 11 to 18 Some embodiments of a method for forming an integrated chip structure including disclosed bonding pads with one or more cavities are shown, the one or more cavities being configured to reduce the recess of the bonding pads. Although the method is described... Figures 11 to 18 However, it should be understood that Figures 11 to 18 The structures disclosed herein are not limited to this method, but can exist independently of this method.

[0091] like Figure 11As shown in cross-sectional view 1100, a substrate 102 is provided. In various embodiments, the substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or epitaxial layer associated therewith. In some embodiments (not shown), one or more semiconductor devices are formed on and / or within the substrate 102. In various embodiments, the one or more semiconductor devices may include transistor devices, image sensor devices, MEMS devices, etc.

[0092] One or more interconnects 106 are formed within a lower dielectric structure 104L formed above substrate 102. The lower dielectric structure 104L may include one or more lower interlayer dielectric (ILD) layers 104a-104b separated by one or more etch stop layers 105a. In some embodiments, the one or more interconnects 106 may include a topmost interconnect 108 comprising a barrier layer 108b and a conductive core 108c. In some embodiments, the topmost interconnect 108 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by forming ILD layers on substrate 102, etching the ILD layers to form vias and / or trenches, filling the vias and / or trenches with barrier layers and conductive material, and performing a planarization process (e.g., a CMP process). In some embodiments, the lower dielectric structure 104L may include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, porous dielectric materials, etc. In some embodiments, the lower dielectric structure 104L can be formed by one or more deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), etc.), and conductive materials (e.g., tungsten, copper, aluminum, etc.) can be formed by deposition processes and / or plating processes (e.g., electroplating, electroless plating, etc.).

[0093] like Figure 12As shown in cross-sectional view 1200, a first upper dielectric structure 1201 is formed above the lower dielectric structure 104L. In some embodiments, the first upper dielectric structure 1201 includes a first bonding pad etch stop layer 105b formed above the lower dielectric structure 104L and a first bonding pad ILD layer 104c formed on the first bonding pad etch stop layer 105b. In some embodiments, the first bonding pad etch stop layer 105b may include nitrides (e.g., silicon nitride, silicon oxynitride, etc.), carbides (e.g., silicon carbide, silicon oxycarbide, etc.). In some embodiments, the first bonding pad ILD layer 104c may include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, porous dielectric materials, etc. In some embodiments, the first bonding pad etch stop layer 105b and the first bonding pad ILD layer 104c may be formed by a deposition process (e.g., PVD process, CVD process, PE-CVD process, ALD process, etc.).

[0094] A first bonding pad opening 1202 is formed within the first upper dielectric structure 1201. In some embodiments, the first bonding pad opening 1202 may be formed according to a first patterning process. In some embodiments, the first patterning process may be performed by selectively exposing the first upper dielectric structure 1201 to a first etchant 1204 according to a first mask 1206. The first patterning process forms sidewalls of the first upper dielectric structure 1201 defining the first bonding pad opening 1202. In some embodiments, the first etchant 1204 may include a plasma etchant having a fluorine-based etching chemical (e.g., SF6 plasma, etc.). In some embodiments, the first mask 1206 may include a photosensitive material (e.g., photoresist), a hard mask, etc.

[0095] like Figure 13As shown in cross-sectional view 1300, a first barrier layer 114b and a first conductive core 114c are formed within the first bonding pad opening 1202. In such an embodiment, the first barrier layer 114b may be formed along the inner surface of the first upper dielectric structure 1201 defining the first bonding pad opening 1202. Subsequently, the first conductive core 114c may be formed over the first barrier layer 114b and within the first bonding pad opening 1202. In some embodiments, the first barrier layer 114b may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the first conductive core 114c may be formed by depositing a first conductive material using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the first barrier layer 114b may include titanium, tantalum, titanium nitride, tantalum nitride, etc. In various embodiments, the first conductive material may include copper, aluminum, tungsten, etc. After depositing the first conductive material within the first bonding pad opening 1202, a planarization process may be performed to remove excess first conductive material from above the first upper dielectric structure 1201 and define the lower segment 114 of the bonding pad. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. In other embodiments, the planarization process may include, for example, an etching process and / or a grinding process.

[0096] like Figure 14 As shown in cross-sectional view 1400, a second upper dielectric structure 1401 is formed above a first upper dielectric structure 1201. In some embodiments, the second upper dielectric structure 1401 includes a second bonding pad etch stop layer 105c formed above the first bonding pad ILD layer 104c, a second bonding pad ILD layer 104d formed on the second bonding pad etch stop layer 105c, and a top dielectric layer 105t formed on the second bonding pad ILD layer 104d. In some embodiments, the second bonding pad etch stop layer 105c and / or the top dielectric layer 105t may include nitrides (e.g., silicon nitride, silicon oxynitride, etc.), carbides (e.g., silicon carbide, silicon oxycarbide, etc.), etc. In some embodiments, the second bonding pad ILD layer 104d may include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, porous dielectric materials, etc. In some embodiments, the second bonding pad etch stop layer 105c, the second bonding pad ILD layer 104d, and the top dielectric layer 105t can be formed by deposition processes (e.g., PVD process, CVD process, PE-CVD process, ALD process, etc.).

[0097] like Figure 15As shown in cross-sectional view 1500, a second bonding pad opening 1502 is formed within the second upper dielectric structure 1401. In some embodiments, the second bonding pad opening 1502 may be formed according to a second patterning process. In some embodiments, the second patterning process may be performed by selectively exposing the second upper dielectric structure 1401 to a second etchant 1504 according to a second mask 1506. The second patterning process forms sidewalls of the second upper dielectric structure 1401 defining the second bonding pad opening 1502. In some embodiments, the second etchant 1504 may include a plasma etchant having a fluorine-based etching chemical (e.g., SF6 plasma, etc.). In some embodiments, the second mask 1506 may include a photosensitive material (e.g., photoresist), a hard mask, etc.

[0098] like Figure 16 As shown in cross-sectional view 1600, a barrier material 1602 and a second conductive material 1604 are formed within the second bonding pad opening 1502 and above the top dielectric layer 105t. The barrier material 1602 may be formed along the inner surface defining the second bonding pad opening 1502. Subsequently, the second conductive material 1604 may be formed above the barrier material 1602 and within the second bonding pad opening 1502. In some embodiments, the barrier material 1602 may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the second conductive material 1604 may be formed by a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the barrier material 1602 may include titanium, tantalum, titanium nitride, tantalum nitride, etc. In various embodiments, the second conductive material may include copper, aluminum, tungsten, etc.

[0099] like Figure 17A Cross-sectional view 1700 and Figure 17B As shown in top view 1706, the second bonding pad opening (e.g., Figure 16 A second conductive material is formed within 1502 (e.g., Figure 16Following step 1604), a planarization process can be performed (along line 1702). The planarization process removes excess second conductive material from above the top dielectric layer 105t to define an upper segment 116 of the bonding pad 112 on the first IC die 202. The upper segment 116 of the bonding pad 112 includes a second barrier layer 116b and a second conductive core 116c located above the second barrier layer 116b. The upper segment 116 of the bonding pad 112 includes a top surface having a plurality of discrete top surface segments 112u, which are laterally spaced from each other by one or more cavities 113 defined by the inner sidewalls of the bonding pad 112, as observed in cross-sectional view 1700. The one or more cavities 113 are filled with a second upper dielectric structure (e.g., the top dielectric layer 105t, the second bonding pad ILD layer 104d, and the second bonding pad etch stop layer 105c).

[0100] In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. During the CMP process, the upper surface of the first IC die 202 is brought into contact with a polishing pad 1704, such that the top dielectric layer 105t and the upper segment 116 of the bonding pad 112 are in contact with the polishing pad 1704. Because the top dielectric layer 105t is disposed directly between the inner sidewalls of the upper segment 116 of the bonding pad 112, the overlap between the polishing pad 1704 and each of the plurality of discrete top surface segments 112u is reduced. Reducing the overlap between the polishing pad 1704 and each of the plurality of discrete top surface segments 112u reduces the recesses of each of the plurality of discrete top surface segments 112u.

[0101] like Figure 18 As shown in cross-sectional view 1800, bonding pads 112 of a first IC die 202 are bonded to additional bonding pads 218 of a second IC die 208 to form a multidimensional integrated chip structure. During bonding, multiple discrete top surface segments of the bonding pad 112 are brought into contact with multiple discrete segments of the additional bonding pad 218. Furthermore, the top surface of the dielectric structure 104 is brought into contact with the surface of the additional dielectric structure 210 of the second IC die 208 to form a hybrid bonding interface between the first IC die 202 and the second IC die 208. The reduced recesses of the multiple discrete top surface segments of the bonding pad 112 reduce the formation of voids between the bonding pad 112 and the additional bonding pad 218, thereby improving the electrical performance and / or reliability of the multidimensional integrated chip structure.

[0102] Figures 19 to 28 Additional embodiments of a method for forming an integrated chip structure including disclosed bonding pads with one or more cavities are shown, the one or more cavities being configured to reduce the recess of the bonding pads. Although the method is described... Figures 19 to 28 However, it should be understood that Figures 19 to 28 The structures disclosed herein are not limited to this method, but can exist independently of this method.

[0103] like Figure 19 As shown in cross-sectional view 1900, a substrate 102 is provided. One or more interconnects 106 are formed within a lower dielectric structure 104L, which is formed above the substrate 102. In some embodiments, the one or more interconnects 106 may include a topmost interconnect 108 comprising a barrier layer 108b and a conductive core 108c.

[0104] like Figure 20 As shown in cross-sectional view 2000, a first upper dielectric structure 2001 is formed above the lower dielectric structure 104L. In some embodiments, the first upper dielectric structure 2001 includes a first bonding pad etch stop layer 105b formed above the lower dielectric structure 104L, a first bonding pad ILD layer 104c formed on the first bonding pad etch stop layer 105b, a second bonding pad etch stop layer 105c formed on the first bonding pad ILD layer 104c, and a second bonding pad ILD layer 104d formed on the second bonding pad etch stop layer 105c.

[0105] A central first bonding pad opening 2002 is formed within the first upper dielectric structure 2001. In some embodiments, the central first bonding pad opening 2002 may be formed according to a first patterning process. In some embodiments, the first patterning process may be performed by selectively exposing the first upper dielectric structure 2001 to a first etchant 2004 according to a first mask 2006.

[0106] like Figure 21 As shown in the cross-sectional view 2100, a sacrificial mask 2102 is formed within the opening 2002 of the first bonding pad in the middle. The sacrificial mask 2102 may include dielectric material, photoresist material, etc.

[0107] like Figure 22 As shown in cross-sectional view 2200, a first bonding pad opening 2202 is formed within the first upper dielectric structure 2001. In some embodiments, the first bonding pad opening 2202 may be formed according to a second patterning process. In some embodiments, the second patterning process may be performed by selectively exposing the first upper dielectric structure 2001 to a second etchant 2204 according to a second mask 2206.

[0108] like Figure 23 As shown in cross-sectional view 2300, the sacrificial mask is removed from the opening 2202 of the first bonding pad (e.g., Figure 22(2102). In various embodiments, the sacrificial mask 2102 can be removed by chemical developing agents, etching processes, etc.

[0109] like Figure 24 As shown in cross-sectional view 2400, a first barrier layer 114b is formed within the first bonding pad opening 2202, and a first conductive core 114c is formed on the first barrier layer 114b and within the first bonding pad opening 2202. In such an embodiment, the first barrier layer 114b may be formed along the inner surface defining the first bonding pad opening 2202. Subsequently, the first conductive core 114c may be formed above the barrier layer 114b and within the first bonding pad opening 2202.

[0110] like Figure 25 As shown in cross-sectional view 2500, a second upper dielectric structure 2501 is formed above a first upper dielectric structure 2001. In some embodiments, the second upper dielectric structure 2501 includes a third bonding pad etch stop layer 105d formed above a second bonding pad ILD layer 104d, a third bonding pad ILD layer 104e formed on the third bonding pad etch stop layer 105d, and a top dielectric layer 105t formed above the third bonding pad ILD layer 104e.

[0111] A second bonding pad opening 2502 is formed within the second upper dielectric structure 2501. In some embodiments, the second bonding pad opening 2502 may be formed according to a third patterning process. In some embodiments, the third patterning process may be performed by selectively exposing the second upper dielectric structure 2501 to a third etchant 2504 according to a third mask 2506. The third patterning process forms the sidewalls of the second upper dielectric structure 2501 that defines the second bonding pad opening 2502.

[0112] like Figure 26 As shown in cross-sectional view 2600, a barrier material 2602 and a conductive material 2604 are formed within the second bonding pad opening 2502 and above the top dielectric layer 105t. In such an embodiment, the barrier material 2602 may be formed along the inner surface defining the second bonding pad opening 2502. Subsequently, the conductive material 2604 may be formed above the barrier material 2602 and within the second bonding pad opening 2502.

[0113] like Figure 27A Cross-sectional view 2700 and Figure 27B As shown in the top view 2706, a conductive material (e.g., Figure 26Following line 2604, a planarization process can be performed (along line 2702). The planarization process removes excess conductive material from above the second upper dielectric structure to define an upper segment 116 of a bonding pad 112 on the first IC die 202. The upper segment 116 of the bonding pad 112 includes a portion of a first barrier layer 114b, a portion of a first conductive core 114c, a second barrier layer 116b, and a second conductive core 116c located above the second barrier layer 116b. The upper segment 116 of the bonding pad 112 includes a top surface comprising a plurality of discrete top surface segments 112u, which are laterally spaced from each other by one or more cavities 113 defined by the inner sidewalls of the bonding pad 112. The one or more cavities 113 are filled with the second upper dielectric structure.

[0114] In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. During the CMP process, the upper surface of the first IC die 202 is brought into contact with a polishing pad 2704, such that the top dielectric layer 105t and the upper segment 116 of the bonding pad 112 are in contact with the polishing pad 2704. Because the top dielectric layer 105t is disposed directly between the inner sidewalls of the upper segment 116 of the bonding pad 112, the overlap between the polishing pad 2704 and each of the plurality of discrete top surface segments 112u is reduced. Reducing the overlap between the polishing pad 2704 and each of the plurality of discrete top surface segments 112u reduces the depressions of each of the plurality of discrete top surface segments 112u.

[0115] like Figure 28 As shown in cross-sectional view 2800, the bonding pad 112 of the first IC die 202 is bonded to the additional bonding pad 218 of the second IC die 208. During bonding, a plurality of discrete top surface segments of the bonding pad 112 are brought into contact with a plurality of additional discrete segments of the additional bonding pad 218. Furthermore, the upper surface of the dielectric structure 104 is brought into contact with the surface of the additional dielectric structure 210 of the second IC die 208 to form a hybrid bonding interface between the first IC die 202 and the second IC die 208.

[0116] In some optional embodiments, this can be omitted. Figures 25 to 27B The action, and can extend along the hybrid bonding interface (e.g., along the top of the first barrier layer 114b and the first conductive core 114c) will have Figure 24 The first die of the structure is bonded to the bonding pad with the structure. Figure 24 The additional die with the bonding pad of the structure.

[0117] Figures 29 to 35Additional embodiments of a method for forming a disclosed bonding pad integrated chip structure are shown, wherein the one or more cavities are configured to reduce the recess of the bonding pads. Although the method is described... Figures 29 to 35 However, it should be understood that Figures 29 to 35 The structures disclosed herein are not limited to this method, but can exist independently of this method.

[0118] like Figure 29 As shown in cross-sectional view 2900, a substrate 102 is provided. One or more interconnects 106 are formed within a lower dielectric structure 104L formed above the substrate 102. In some embodiments, the one or more interconnects 106 may include a topmost interconnect 108 comprising a barrier layer 108b and a conductive core 108c.

[0119] like Figure 30 As shown in cross-sectional view 3000, a first upper dielectric structure 3001 is formed above a lower dielectric structure 104L. In some embodiments, the first upper dielectric structure 3001 includes a first bonding pad etch stop layer 105b formed above the lower dielectric structure 104L and a first bonding pad ILD layer 104c formed on the first bonding pad etch stop layer 105b. One or more first bonding pad openings 3002 are formed within the first upper dielectric structure 3001. In some embodiments, one or more first bonding pad openings 3002 may be formed according to a first patterning process. In some embodiments, the first patterning process may be performed by selectively exposing the first upper dielectric structure 3001 to a first etchant 3004 according to a first mask 3006.

[0120] like Figure 31A As shown in cross-sectional view 3100, a first barrier layer 114b and a first conductive core 114c are formed within one or more first bonding pad openings 3002. In some embodiments, the first barrier layer 114b may be formed along the inner surface of a first upper dielectric structure 3001 defining one or more first bonding pad openings 3002. Subsequently, the first conductive core 114c may be formed over the first barrier layer 114b and within one or more first bonding pad openings 3002. After depositing the first conductive material within one or more first bonding pad openings 3002, a planarization process may be performed to remove excess first conductive material from above the first upper dielectric structure 3001 and define the lower segment 114 of the bonding pad.

[0121] In some embodiments, such as Figure 31BAs shown in the top view 3102, the lower segment 114 of the bonding pad may include a plurality of discrete lower segments 114d. The plurality of discrete lower segments 114d may be formed in an array. The plurality of discrete lower segments 114d may be separated along a first direction 120 and along a second direction 122 perpendicular to the first direction 120. In some embodiments, Figure 31A The cross-sectional view 3100 is along Figure 31B It is intercepted by the cross-section line A-A'.

[0122] In some alternative embodiments, such as Figure 31C As shown in top view 3104, the lower segment 114 of the bonding pad may include a single continuous segment that extends continuously in a closed loop around one or more cavities 113. In some embodiments, the one or more cavities 113 each have a rectangular shape. Figure 31A The cross-sectional view 3100 is along Figure 31C It is intercepted by the cross-section line A-A'.

[0123] like Figure 32 As shown in cross-sectional view 3200, a second upper dielectric structure 3201 is formed above a first upper dielectric structure 3001. In some embodiments, the second upper dielectric structure 3201 includes a second bonding pad etch stop layer 105c formed above a first bonding pad ILD layer 104c, a second bonding pad ILD layer 104d formed on the second bonding pad etch stop layer 105c, and a top dielectric layer 105t formed on the second bonding pad ILD layer 104d.

[0124] like Figure 33 As shown in cross-sectional view 3300, one or more second bonding pad openings 3302 are formed within the second upper dielectric structure 3201. In some embodiments, the one or more second bonding pad openings 3302 may be formed according to a third patterning process. In some embodiments, the third patterning process may be performed by selectively exposing the second upper dielectric structure 3201 to a third etchant 3304 according to a third mask 3306. The third patterning process forms sidewalls of the second upper dielectric structure 3201 that define the one or more second bonding pad openings 3302.

[0125] like Figure 34AAs shown in cross-sectional view 3400, a second barrier layer 116b and a second conductive core 116c are formed within one or more second bonding pad openings 3302. In some embodiments, the second barrier layer 116b may be formed along the inner surface of a second upper dielectric structure 3201 defining one or more second bonding pad openings 3302. Subsequently, the second conductive core 116c may be formed over the second barrier layer 116b and within one or more second bonding pad openings 3302. A planarization process may be performed to remove portions of the second barrier layer 116b and the second conductive core 116c to form the upper segment 116 of the bonding pad.

[0126] In some embodiments, such as Figure 34B As shown in top view 3402, the upper segment 116 of the bonding pad may include a plurality of discrete upper segments 116d. The plurality of discrete upper segments 116d may be formed in an array. The plurality of discrete upper segments 116d may be separated along a first direction 120 and along a second direction 122. In some embodiments, Figure 34A The cross-sectional view 3400 is along Figure 34B It is intercepted by the cross-section line A-A'.

[0127] In some alternative embodiments, such as Figure 34C Top view 3404 and Figure 34D As shown in top view 3406, the upper segment 116 of the bonding pad may include a single continuous segment that extends continuously in a closed loop around one or more cavities 113. In some embodiments, the single continuous segment may be placed within a plurality of discrete lower segments 114d (e.g., as shown in top view 3406). Figure 31B Directly above (as shown), while in other embodiments, a single continuous segment can be directly above a single continuous lower segment (e.g., as shown). Figure 31C Directly above (as shown). In some embodiments, Figure 34A Cross-section diagram 3400 along Figure 34C The cross-section line A-A' or along Figure 34D The section line A-A' is cut off.

[0128] like Figure 35 As shown in cross-sectional view 3500, the bonding pad 112 of the first IC die 202 is bonded to the additional bonding pad 218 of the second IC die 208. During bonding, a plurality of discrete top surface segments of the bonding pad 112 are brought into contact with a plurality of additional discrete segments of the additional bonding pad 218. Furthermore, the upper surface of the dielectric structure 104 is brought into contact with the surface of the additional dielectric structure 210 of the second IC die 208 to form a hybrid bonding interface between the first IC die 202 and the second IC die 208.

[0129] Figure 36A flowchart of some embodiments of a method 3600 for forming an integrated chip structure including disclosed bonding pads having one or more cavities configured to reduce the recess of the bonding pads is shown.

[0130] While method 3600 is shown and described herein as a series of actions or events, it should be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events in addition to those shown and / or described herein. Furthermore, not all of the shown actions may be required to implement one or more aspects or embodiments described herein. Moreover, one or more actions depicted herein may be performed in one or more separate actions and / or stages.

[0131] At action 3602, one or more interconnects are formed within the lower dielectric structure above the substrate. Figure 11 A cross-sectional view 1100 is shown, corresponding to some embodiments of action 3602. Figure 19 Cross-sectional view 1900 shows some additional embodiments corresponding to action 3602. Figure 29 Cross-sectional view 2900 is shown, corresponding to some additional embodiments of action 3602.

[0132] At action 3604, a first upper dielectric structure is formed above the lower dielectric structure. Figure 12 A cross-sectional view 1200 is shown, corresponding to some embodiments of action 3604. Figure 20 Cross-sectional view 2000 shows some additional embodiments corresponding to action 3604. Figure 30 Cross-sectional view 3000 is shown, corresponding to some additional embodiments of action 3604.

[0133] At action 3606, a first bonding pad opening is formed within the first upper dielectric structure. Figure 12 A cross-sectional view 1200 is shown, corresponding to some embodiments of action 3606. Figures 20 to 23 Cross-sectional views 2000-2300 are shown corresponding to some additional embodiments of action 3606. Figure 30 Cross-sectional view 3000 is shown, corresponding to some additional embodiments of action 3606.

[0134] At action 3608, a first barrier layer and a first conductive core are formed within the opening of the first bonding pad. Figure 13 A cross-sectional view 1300 is shown, corresponding to some embodiments of action 3608. Figure 24 A cross-sectional view 2400 is shown, corresponding to some additional embodiments of action 3608. Figure 31A Cross-sectional view 3100 is shown, corresponding to some additional embodiments of action 3608.

[0135] At action 3610, a second upper dielectric structure is formed above the first upper dielectric structure. Figure 14 A cross-sectional view 1400 is shown, corresponding to some embodiments of action 3610. Figure 25 Cross-sectional view 2500 is shown, corresponding to some additional embodiments of action 3610. Figure 32 Cross-sectional view 3200 is shown, corresponding to some additional embodiments of action 3610.

[0136] At action 3612, a second bonding pad opening is formed within the second upper dielectric structure to expose the first conductive core and to surround one or more inner sidewalls of the second upper dielectric structure. Figure 15 A cross-sectional view 1500 is shown, corresponding to some embodiments of action 3612. Figure 25 Cross-sectional view 2500 is shown, corresponding to some additional embodiments of action 3612. Figure 33 A cross-sectional view 3300 is shown, corresponding to some additional embodiments of action 3612.

[0137] At action 3614, a barrier material and a conductive material are formed within the opening of the second bonding pad. Figure 16 A cross-sectional view 1600 is shown, corresponding to some embodiments of action 3614. Figure 26 Cross-sectional view 2600 is shown, corresponding to some additional embodiments of action 3614. Figure 34A A cross-sectional view 3400 is shown, corresponding to some additional embodiments of action 3614.

[0138] At action 3616, a chemical mechanical planarization (CMP) process is performed to remove portions of barrier and conductive material to define a bonding pad with an inner sidewall that forms one or more cavities extending into the bonding pad. The inner sidewall is coupled to the top of the bonding pad. Figures 17A to 17B Some embodiments corresponding to action 3616 are shown. Figures 27A to 27B Some additional embodiments corresponding to action 3616 are shown. Figure 34A Cross-sectional view 3400 is shown, corresponding to some additional embodiments of action 3616.

[0139] At action 3618, the integrated die including bonding pads is brought into contact with an additional integrated die including additional bonding pads along the hybrid bonding interface. Figure 18 A cross-sectional view 1800 is shown, corresponding to some embodiments of action 3618. Figure 28 Cross-sectional view 2800 is shown, corresponding to some additional embodiments of action 3618. Figure 35 Cross-sectional view 3500 is shown, corresponding to some additional embodiments of action 3618.

[0140] Therefore, the present invention relates to an integrated chip structure having bonding pads having one or more cavities surrounded by bonding pads and filled with dielectric material, the one or more cavities being configured to mitigate depressions along the upper surface of the bonding pads.

[0141] In some embodiments, the present invention relates to an integrated chip structure. The integrated chip structure includes one or more interconnects disposed within a dielectric structure above a substrate; bonding pads having a top surface arranged along the top surface of the dielectric structure, the top surface of the bonding pads comprising, as observed in a cross-sectional view, a plurality of discrete top surface segments laterally separated from each other by one or more non-zero distances extending between the inner sidewalls of the bonding pads; and the dielectric structure directly disposed between the inner sidewalls of the bonding pads. In some embodiments, the bottom surface of the bonding pads extends laterally and continuously beyond one or more of the inner sidewalls of the bonding pads. In some embodiments, the top surface of the bonding pads is substantially coplanar with the top surface of the dielectric structure. In some embodiments, one or more interconnects include a topmost interconnect disposed within the dielectric structure, the topmost interconnect having an upper surface that directly contacts the bottom surface of the bonding pad and extends continuously beyond the outermost sidewall of the bottom surface of the bonding pad. In some embodiments, one or more interconnects include a topmost interconnect disposed within the dielectric structure, the dielectric structure located between the inner sidewalls of the bonding pads extending continuously from the top surface of the dielectric structure to the topmost interconnect. In some embodiments, the bonding pad includes a lower segment extending laterally between opposing sidewalls coupled to the bottom of the bonding pad; and an upper segment having a lower surface disposed on an upper surface of the lower segment, the upper segment extending laterally between opposing outermost sidewalls of the bonding pad. In some embodiments, the lower surface of the upper segment physically contacts the upper surface of the lower segment. In some embodiments, an inner sidewall of the bonding pad is disposed within the upper segment and coupled to a horizontally extending surface directly above the lower surface of the upper segment. In some embodiments, as observed in a top view of the bonding pad, the bonding pad extends continuously in a non-discontinuous loop.

[0142] In other embodiments, the present invention relates to an integrated chip structure. The integrated chip structure includes one or more interconnects surrounded by a dielectric structure disposed on a substrate; bonding pads surrounded by the dielectric structure, the bonding pads having a lower segment extending between outer edges of a lower sidewall disposed along the bottom of the bonding pad, and an upper segment extending between outer edges of an upper sidewall disposed along the top of the bonding pad; and the upper segment of the bonding pad including one or more inner sidewalls spaced apart by a non-zero distance between edges of a top surface of the bonding pad, the dielectric structure being located between the edges of the top surface of the bonding pad. In some embodiments, the upper segment has a lower surface continuously extending beyond the opposing outer edges of the lower segment. In some embodiments, the integrated chip structure further includes: one or more additional interconnects surrounded by additional dielectric structures disposed on a second substrate; additional bonding pads surrounded by additional dielectric structures and having one or more additional inner sidewalls separated by the additional dielectric structures; and bonding pads contacting the additional bonding pads along a conductive interface, and the dielectric structure located between the edges of the top surface of the bonding pads contacting the additional dielectric structure separating the one or more additional inner sidewalls along a dielectric interface. In some embodiments, the upper sidewall extends vertically below the top of the lower sidewall. In some embodiments, the upper segment includes a barrier layer and a conductive core, with a dielectric structure contacting the sidewall of the barrier layer. In some embodiments, as observed in a cross-sectional view of the bonding pad, the top surface of the bonding pad includes a plurality of discrete top surface segments spaced apart from each other by a non-zero distance. In some embodiments, the inner sidewall of the bonding pad is also coupled to a horizontally extending surface of the bonding pad facing away from the substrate. In some embodiments, the bonding pad includes an outer ring segment that extends continuously in a non-discontinuous loop.

[0143] In another embodiment, the present invention relates to a method of forming an integrated chip structure. The method includes forming a first bonding pad opening within a first upper dielectric structure formed above a lower dielectric structure, the lower dielectric structure surrounding one or more interconnects above a substrate; forming a first barrier layer and a first conductive core within the first bonding pad opening; forming a second upper dielectric structure above the first upper dielectric structure; forming a second bonding pad opening within the second upper dielectric structure to expose the first conductive core and with one or more inner sidewalls surrounding the second upper dielectric structure; forming a barrier material and a conductive material within the second bonding pad opening; and removing portions of the barrier material and conductive material, the removed portions forming bonding pads with inner sidewalls forming one or more cavities extending into the bonding pads. In some embodiments, the one or more cavities are filled with the second upper dielectric structure. In some embodiments, as viewed along a cross-sectional view, the bonding pads have a plurality of discrete upper surfaces separated from each other by the second upper dielectric structure.

[0144] The foregoing outlines the features of the embodiments described herein, enabling those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of the invention.

Claims

1. An integrated chip structure, comprising: One or more interconnects are disposed within a dielectric structure above a substrate; A bonding pad having a top surface arranged along the top surface of the dielectric structure, wherein, as observed in the cross-sectional view, the top surface of the bonding pad includes a plurality of discrete top surface segments laterally separated from each other by one or more non-zero distances, the one or more non-zero distances extending between the inner sidewalls of the bonding pad; and The dielectric structure is directly disposed between the inner sidewalls of the bonding pads. The top surface of the bonding pad is coplanar with the top surface of the dielectric structure. The one or more interconnects include a topmost interconnect disposed within the dielectric structure, the topmost interconnect having an upper surface that directly contacts the bottom surface of the bonding pad and extends continuously beyond the outermost outer wall of the bottom surface of the bonding pad. The bonding pads and the dielectric structure are respectively bonded to another bonding pad and another dielectric structure of another integrated chip structure. The bonding pads include: The lower section extends laterally between opposing sidewalls coupled to the bottom of the bonding pad; and The upper section has a lower surface disposed on the upper surface of the lower section, the upper section extending laterally between the opposite outermost walls of the bonding pads.

2. The integrated chip structure according to claim 1, wherein, The bottom surface of the bonding pad extends laterally and continuously beyond one or more of the inner sidewalls of the bonding pad.

3. The integrated chip structure according to claim 1, wherein, The topmost interconnect includes a conductive core surrounded by a barrier layer.

4. The integrated chip structure according to claim 3, wherein, The conductive core comprises copper.

5. The integrated chip structure according to claim 3, wherein, The barrier layer comprises titanium.

6. The integrated chip structure according to claim 1, wherein, The dielectric structure includes a dielectric material.

7. The integrated chip structure according to claim 1, wherein, The lower surface of the upper section is in physical contact with the upper surface of the lower section.

8. The integrated chip structure according to claim 1, wherein, The inner sidewall of the bonding pad is disposed within the upper section and coupled to a horizontally extending surface directly above the lower surface of the upper section.

9. The integrated chip structure according to claim 1, wherein, As can be seen in the top view of the bonding pad, the bonding pad extends continuously in an uninterrupted loop.

10. An integrated chip structure, comprising: One or more interconnects are surrounded by a dielectric structure disposed on a substrate; A bonding pad is surrounded by the dielectric structure, and the bonding pad includes a lower segment extending between the outer edges of a lower sidewall arranged along the bottom of the bonding pad, and an upper segment extending between the outer edges of an upper sidewall arranged along the top of the bonding pad. as well as The upper segment of the bonding pad includes one or more inner sidewalls spaced apart by a non-zero distance between the edges of the top surface of the bonding pad, and the dielectric structure is located between the edges of the top surface of the bonding pad. The top surface of the bonding pad is coplanar with the top surface of the dielectric structure. One or more interconnects include a topmost interconnect disposed within the dielectric structure, the topmost interconnect having a top surface in direct contact with the bottom surface of the bonding pad and extending continuously beyond the outermost outer wall of the bottom surface of the bonding pad. The integrated chip structure further includes: One or more additional interconnects are surrounded by additional dielectric structures disposed on a second substrate; Additional bonding pads, surrounded by the additional dielectric structure and including one or more additional inner sidewalls separated by the additional dielectric structure; and Wherein, the bonding pad contacts the additional bonding pad along the conductive interface, and the dielectric structure located between the edges of the top surface of the bonding pad contacts the additional dielectric structure separating the one or more additional inner sidewalls along the dielectric interface.

11. The integrated chip structure according to claim 10, wherein, The upper segment has a lower surface that extends continuously beyond the opposite outer edge of the lower segment.

12. The integrated chip structure according to claim 10, wherein, The dielectric structure includes a dielectric material.

13. The integrated chip structure according to claim 10, wherein, The upper sidewall extends vertically below the top of the lower sidewall.

14. The integrated chip structure according to claim 10, wherein, The upper section includes a barrier layer and a conductive core, with the dielectric structure contacting the sidewall of the barrier layer.

15. The integrated chip structure according to claim 10, wherein, As observed in the cross-sectional view of the bonding pad, the top surface of the bonding pad comprises a plurality of discrete top surface segments separated from each other by the non-zero distance.

16. The integrated chip structure according to claim 10, wherein, The inner sidewall of the bonding pad is also coupled to a horizontally extending surface of the bonding pad that is away from the substrate.

17. The integrated chip structure according to claim 10, wherein, The bonding pads include an outer ring segment that extends continuously in an uninterrupted loop.

18. A method for forming an integrated chip structure, comprising: A first bonding pad opening is formed within a first upper dielectric structure formed above a lower dielectric structure, the lower dielectric structure surrounding one or more interconnects above a substrate; A first barrier layer and a first conductive core are formed within the opening of the first bonding pad; A second upper dielectric structure is formed above the first upper dielectric structure; A second bonding pad opening is formed within the second upper dielectric structure to expose the first conductive core and to surround one or more inner sidewalls of the second upper dielectric structure; A barrier material and a conductive material are formed within the opening of the second bonding pad; as well as Removing portions of the blocking material and the conductive material, wherein removing these portions forms a bonding pad with an inner sidewall, the inner sidewall of which forms one or more cavities extending into the bonding pad, the one or more cavities being filled with the second upper dielectric structure. The top surface of the bonding pad is coplanar with the top surface of the second upper dielectric structure. One or more interconnects include a topmost interconnect disposed within the lower dielectric structure, the topmost interconnect having a top surface in direct contact with the bottom surface of the bonding pad and extending continuously beyond the outermost outer wall of the bottom surface of the bonding pad. The bonding pads and the second upper dielectric structure are respectively bonded to the bonding pads and dielectric structure of another integrated chip structure.

19. The method according to claim 18, wherein, The second upper dielectric structure includes a dielectric material.

20. The method according to claim 18, wherein, As can be seen along the cross-sectional view, the bonding pads have a plurality of discrete upper surfaces separated from each other by the second upper dielectric structure.

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