Semiconductor structure and method of manufacturing the same, electronic device

Abstract

This invention discloses a semiconductor structure, its fabrication method, and an electronic device. The electronic device includes: a substrate; a rigid photomask formed on the substrate; a via extending through the rigid photomask and into the substrate, the via being filled with a first conductive material, the first conductive material being etched back to a predetermined depth to form an opening in the via; an isolation layer formed at the opening of the via, the isolation layer covering the edge of the first conductive material, the first conductive material being exposed in the middle of the isolation layer; and a second conductive material filling the middle of the isolation layer, a barrier adhesion layer disposed between the first conductive material and the second conductive material.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, its fabrication method, and an electronic device. Background Technology

[0002] In related technologies, such as Figure 1 As shown, the semiconductor structure includes a substrate 101 and a hard mask 102. After the silicon dioxide film layer of the hard mask 102 is etched, a via 103 is formed. An inverted trapezoidal structure 1031a defect is formed at the opening 1031 of the via 103, thereby enlarging the opening 1031. The via 103 is filled with a metal material (e.g., a first conductor material 106). The inverted trapezoidal structure 1031a defect may cause the metal filling material 1091 of the subsequent silicon via to invade the forbidden area designed with subsequent metal interconnects, that is, the metal filling material of the wiring layer connects with the metal material, resulting in serious problems such as short circuits.

[0003] Therefore, a new technical solution is needed to solve the above-mentioned technical problems. Summary of the Invention

[0004] One objective of this invention is to provide a new technical solution for semiconductor structures to solve the problem of short circuits caused by the connection between the metal filling material of the wiring layer and the metal material in the rigid mask in the prior art.

[0005] According to a first aspect of the present invention, a semiconductor structure is provided. The semiconductor structure includes: a substrate;

[0006] A rigid photomask, the rigid photomask being formed on the substrate;

[0007] A through-hole extends through the rigid photomask and into the substrate, the through-hole being filled with a first conductive material, the first conductive material being etched back to a predetermined depth to form an opening in the through-hole, an isolation layer being formed at the opening of the through-hole, the isolation layer covering the edge of the first conductive material, the first conductive material being exposed in the middle of the isolation layer; and

[0008] A second conductor material is filled in the middle of the insulating layer, and a barrier adhesion layer is provided between the first conductor material and the second conductor material.

[0009] Preferably, the material of the isolation layer is at least one of silicon dioxide, silicon fluoride, and organic polymer.

[0010] Preferably, the isolation layer is annular, and the outer diameter of the isolation layer gradually increases from the side closer to the first conductor material to the side farther away from the first conductor material.

[0011] Preferably, the thickness of the isolation layer at its highest point is 0.5μm-10μm, and the height of the isolation layer is 1μm-3μm.

[0012] Preferably, the rigid photomask includes silicon dioxide layers and silicon nitride layers alternately arranged along the thickness direction, wherein the silicon nitride layer is an etch stop layer.

[0013] According to a second aspect of the present invention, a method for preparing a semiconductor structure is provided, comprising:

[0014] Provide substrate;

[0015] A hard mask template is deposited on the substrate;

[0016] A through-hole is formed on the rigid photomask, and the through-hole extends into the substrate;

[0017] The through-hole is filled with a first conductor material;

[0018] The first conductor material at the opening of the through hole is removed by an etching process.

[0019] An isolation layer is formed at the opening of the through hole, the isolation layer covering the edge of the first conductor material, and the first conductor material being exposed in the middle of the isolation layer;

[0020] A barrier adhesion layer and a second conductor material are formed on the rigid mask. The second conductor material fills the middle of the isolation layer, and the barrier adhesion layer is disposed between the first conductor material and the second conductor material.

[0021] Preferably, an insulating layer is formed at the opening of the through-hole, the insulating layer covering the edge of the first conductor material, the first conductor material being exposed in the middle of the insulating layer, comprising:

[0022] An isolation film layer is deposited on the rigid mask and at the opening of the through hole;

[0023] The isolation film layer on the rigid mask is removed to form the isolation layer at the opening of the through hole, with the first conductor material exposed in the middle of the isolation layer.

[0024] Preferably, the isolation film layer is deposited using chemical vapor deposition.

[0025] The isolation film layer was removed using an anisotropic dry etching method.

[0026] According to a third aspect of the present invention, an electronic device is provided. The electronic device includes the semiconductor structure described in any one of the preceding claims.

[0027] Preferably, the structure includes a first component and a second component, the semiconductor structure is located between the first component and the second component, the first component is connected to the second conductor material, the first conductor material is connected to the second component at the end of the through-hole opposite to the second conductor material, and the first component is connected to the second component through the first conductor material and the second conductor material.

[0028] One technical advantage of this invention is that an isolation layer is formed at the edge of the first conductor material near the opening of the via. This isolation layer effectively reduces the exposed area of ​​the first conductor material and effectively prevents contact between the first conductor material and the second conductor material in the wiring layer, thereby reducing the risk of short circuits in the semiconductor structure.

[0029] In addition, the isolation layer can effectively reduce the distance between the first conductor material and the second conductor material, which can effectively reduce the area occupied by the conductor lines in the wiring layer.

[0030] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a semiconductor structure in the prior art.

[0033] Figures 2-7 This is a schematic diagram of each stage of a semiconductor structure fabrication method according to an embodiment of the present invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] 101. Substrate; 102. Rigid mask; 1021. Silicon dioxide layer; 1022. Silicon nitride layer; 103. Through-hole; 1031. Opening; 1031a. Inverted trapezoidal structure; 104. Insulating layer; 105. First barrier adhesion layer; 106. First conductor material; 107. Isolation film layer; 1071. Isolation layer; 108. Second barrier adhesion layer; 109. Second conductor material; 110. Interlayer dielectric layer. Detailed Implementation

[0036] The specific embodiments of the present invention will be described in detail below. To avoid excessive and unnecessary details, well-known structures or functions will not be described in detail in the following embodiments.

[0037] The approximate language used in the following embodiments is for quantitative expression, indicating that a certain degree of variation in quantity is permissible without changing the basic function. Therefore, the values ​​corrected using terms such as "approximately," "around," etc., are not limited to the exact value itself. In some embodiments, "approximately" indicates that the value being corrected is allowed to vary within a range of plus or minus ten percent (10%); for example, "approximately 100" could represent any value between 90 and 110. Furthermore, in the expression "approximately from the first value to the second value," both the first and second values ​​are corrected simultaneously. In some cases, the approximate language may be related to the accuracy of the measuring instrument.

[0038] Unless otherwise defined, the technical and scientific terms used in the following embodiments have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0039] One embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes:

[0040] Substrate 101;

[0041] A rigid photomask 102 is formed on the substrate 101;

[0042] A through-hole 103 extends through the rigid mask 102 and into the substrate 101. A first conductive material 106 is filled within the through-hole 103. The first conductive material is etched back to a predetermined depth to form an opening 1031 in the through-hole 103. An isolation layer 1071 is formed at the opening 1031 of the through-hole 103. The isolation layer 1071 covers the edge of the first conductive material 106, with the first conductive material 106 exposed in the center of the isolation layer 1071.

[0043] The second conductor material 109 is filled in the middle of the isolation layer 1071, and a barrier adhesion layer 108 is provided between the first conductor material 106 and the second conductor material 109.

[0044] In this embodiment of the invention, an etching process is used to form an opening 1031 in the via 103. An isolation layer 1071 is formed at the edge of the first conductor material 106 near the opening 1031 of the via 103. The isolation layer 1071 effectively reduces the exposed area of ​​the first conductor material 106 and effectively prevents the first conductor material 106 from contacting the second conductor material 109 in the wiring layer, thereby reducing the risk of short circuits in the semiconductor structure.

[0045] In addition, the isolation layer 1071 can effectively reduce the distance between the first conductor material 106 and the second conductor material 109, which can effectively reduce the area occupied by the conductor lines in the wiring layer.

[0046] In one specific embodiment of the present invention, such as Figure 7 As shown, the semiconductor structure includes:

[0047] Substrate 101;

[0048] A rigid photomask 102 is formed on the substrate 101;

[0049] A through-hole 103 extends through the rigid photomask 102 and into the substrate 101. An insulating layer 104 is formed on the inner wall of the through-hole 103. A first barrier adhesion layer 105 is formed on the insulating layer 104. A first conductive material 106 is filled in the cavity formed by the first barrier adhesion layer 105. The first conductive material is etched back to a set depth to form the opening 1031 of the through-hole. The cavity has an opening 1031 located on the side of the rigid photomask 102 facing away from the substrate 101. An isolation layer 1071 is formed at the opening 1031 of the through-hole. The isolation layer 1071 covers the edge of the first conductive material 106, and the first conductive material 106 is exposed in the middle of the isolation layer 1071. The isolation layer 1071 is an insulating material.

[0050] A wiring layer is disposed on the rigid mask 102 and at the opening 1031 of the through hole. The wiring layer includes a second conductor material 109, which fills the middle of the isolation layer 1071. A second barrier adhesion layer 108 is disposed between the first conductor material 106 and the second conductor material 109.

[0051] Specifically, the substrate 101 is made of silicon, such as polycrystalline silicon or monocrystalline silicon. The substrate 101 is typically a wafer. The rigid photomask 102 is an insulating material, such as at least one of silicon dioxide, silicon nitride, and titanium nitride. These materials exhibit good insulation properties and high structural strength.

[0052] A rigid photomask 102 made of a single material, such as silicon dioxide, is prone to warping, leading to reduced strength and decreased durability of the semiconductor structure. In a preferred embodiment, the rigid photomask 102 includes alternating layers of silicon dioxide 1021 and silicon nitride 1022 along its thickness direction. The silicon dioxide layer 1021 generates compressive stress, while the silicon nitride layer 1022 generates tensile stress. The alternating silicon dioxide layer 1021 and silicon nitride layer 1022 effectively balance the tensile and compressive stresses, thereby effectively reducing the warping of the rigid photomask 102 and improving the overall strength of the semiconductor structure.

[0053] In this example, the silicon nitride layer 1022 is an etch stop layer. That is, when etching the silicon dioxide layer 1021, the etching stops at the silicon nitride layer 1022 to control the etching depth. In this way, the silicon nitride layer 1022 can effectively avoid the problem of excessive etching depth.

[0054] In other examples, the etching stop layer is made of at least one of silicon oxynitride and silicon carbonitride. All of these materials can control the etching depth.

[0055] Of course, the materials of the substrate 101 and the rigid mask 102 are not limited to the above embodiments, and those skilled in the art can set them according to actual needs.

[0056] The via 103 can be formed in various ways, such as wet etching or dry etching. The size and depth of the via 103 can be set by those skilled in the art according to actual needs. The insulating layer 104 and the first barrier adhesion layer 105 are thin layers attached to the inner wall of the via 103. The insulating layer 104 is located between the first barrier adhesion layer 105 and the inner wall of the via 103. The first barrier adhesion layer 105 forms a cavity. A first conductor material 106 is filled in the cavity. The first conductor material 106 is made of metal, such as copper or tungsten. An isolation layer 1071 is formed by chemical vapor deposition. The isolation layer 1071 is an insulating material, thereby reducing the exposed area of ​​the first conductor material 106, reducing the probability of contact with other conductor materials, such as the second conductor material 109 described below, and reducing short circuits. Optionally, the first conductor material 106 and the second conductor material 109 are made of metal, such as, but not limited to, copper, aluminum, gold, and silver. The first conductor material 106 and the second conductor material 109 may be made of the same or different materials.

[0057] The wiring layer is used to form conductor lines, which are used to input electrical signals into the semiconductor structure. The wiring layer covers the rigid mask 102 and the openings 1031 of the vias. The second conductor material 109 forms conductor lines according to a predetermined wiring pattern.

[0058] In one example, the insulating layer 1071 is made of at least one of silicon carbide, silicon fluoride, and organic polymer. These materials have good insulation properties, and the formation process of the insulating layer 1071 is simple.

[0059] Organic polymers include plastics, thermoplastic elastomers, etc.

[0060] Among them, silicon dioxide also has good corrosion resistance and can effectively withstand the etching solution used in wet etching processes.

[0061] Of course, the material of the isolation layer 1071 is not limited to the above embodiments, and those skilled in the art can choose according to actual needs.

[0062] In one example, the isolation layer 1071 is annular. The outer diameter of the isolation layer 1071 gradually increases from the side closer to the first conductor material 106 to the side farther away from the first conductor material 106.

[0063] An inverted trapezoidal structure 1031a is formed at the opening 1031 of the through-hole 103. An insulating layer 1071 is disposed around the inverted trapezoidal structure 1031a to form a funnel-shaped annular structure. The insulating layer 1071 of this structure can effectively cover the edge of the first conductor material 106.

[0064] Furthermore, the inner diameter of the isolation layer 1071 is less than or equal to the inner diameter of the portion below the opening 1031 of the via 103. In this way, the isolation layer 1071 effectively reduces the area of ​​the first conductor material 106 exposed at the opening 1031, further reducing the risk of contact with the second conductor material 109 and reducing the risk of short circuits in the semiconductor structure.

[0065] In one example, the isolation layer 1071 has a thickness of 0.5 μm-10 μm at its highest point and a height of 1 μm-3 μm. The thickness refers to the radial dimension of the isolation layer 1071 along the via 103, and the height refers to the axial dimension of the isolation layer 1071 along the via 103. Within this dimensional range, the isolation layer 1071 can more effectively prevent the first conductor material 106 from contacting the second conductor material 109 in the wiring layer, thereby reducing the risk of short circuits in the semiconductor structure.

[0066] In one example, the first barrier adhesion layer 105 and the second barrier adhesion layer 108 are at least one of a refractory metal, a nitride of a refractory metal, or a nitride of a refractory metal. Optionally, the refractory metal is titanium or tantalum. For example, the first barrier adhesion layer 105 or the second barrier adhesion layer 108 is one of titanium, titanium nitride, titanium, and titanium nitride; it may also be one of tantalum, tantalum nitride, tantalum, and titanium nitride.

[0067] The aforementioned materials can effectively prevent the first conductor material 106 and the second conductor material 109 from migrating into the surrounding materials.

[0068] Of course, refractory metals are not limited to the above embodiments, and those skilled in the art can choose according to actual needs.

[0069] In one example, the insulating layer 104 is made of at least one of silicon dioxide, silicon nitride, and an organic polymer. These materials have good insulation properties and can effectively prevent short circuits in the semiconductor structure.

[0070] In one example, the wiring layer includes an interlayer dielectric layer 110, in which the second conductor material 109 is embedded. The interlayer dielectric layer 110 is made of at least one of silicon dioxide, phosphosilicate glass, and borosilicate glass.

[0071] The interlayer dielectric layer 110 is an insulating material. For example, trenches are formed on the interlayer dielectric layer 110 by etching. The second conductor material 109 is formed within the trenches by chemical vapor deposition, thereby forming a conductor circuit. The above-mentioned material has good insulation properties and high structural strength. The interlayer dielectric layer 110 is formed on a rigid mask 102 by physical vapor deposition or chemical vapor deposition.

[0072] Another embodiment of the present invention provides an electronic device. This electronic device includes the semiconductor structure described above.

[0073] Electronic devices can be, but are not limited to, mobile phones, computers, watches, speakers, display screens, etc.

[0074] In one example, the electronic device includes a first component and a second component, with the semiconductor structure located between the first component and the second component. The first component is connected to the second conductor material, and the first conductor material is connected to the second component at the end of the via opposite to the second conductor material. The first component is in communication with the second component through the first conductor material and the second conductor material.

[0075] In this example, the first and second components are connected through a semiconductor structure, and the electronic device can precisely control the on and off states of the first and second components.

[0076] Another embodiment of the present invention provides a method for fabricating a semiconductor structure. The method includes: providing a substrate 101;

[0077] A hard mask 102 is deposited on the substrate 101;

[0078] A through hole 103 is formed on the rigid mask 102, and the through hole extends to the substrate 101;

[0079] The through hole 103 is filled with a first conductor material 106;

[0080] The first conductor material 106 at the opening 1031 of the through hole 103 is removed by an etching process;

[0081] An isolation layer 1071 is formed at the opening of the through hole 103, the isolation layer 1071 covers the edge of the first conductor material 106, and the first conductor material 106 is exposed in the middle of the isolation layer 1071;

[0082] A barrier adhesion layer and a second conductor material 109 are formed on the rigid mask 102. The second conductor material 109 fills the middle of the isolation layer 1071, and the barrier adhesion layer is disposed between the first conductor material 106 and the second conductor material 109.

[0083] This preparation method can prepare the aforementioned semiconductor structure.

[0084] In one specific embodiment of the present invention, such as Figures 2-7 As shown, the preparation method includes:

[0085] Substrate 101 is provided;

[0086] A hard mask 102 is deposited on the substrate 101;

[0087] A through hole 103 is formed on the rigid mask 102, and the through hole 103 extends to the substrate 101;

[0088] An insulating layer 104 and a first barrier adhesion layer 105 are formed on the substrate 101. A cavity is formed in the first barrier adhesion layer 105. The cavity has an opening 1031 on the side of the rigid mask 102 facing away from the substrate 101. A first conductor material 106 is filled in the cavity.

[0089] The first conductor material 106 and the first barrier adhesion layer 105 at the opening 1031 of the through hole are removed by an etching process.

[0090] An isolation layer 1071 is formed at the opening 1031 of the through hole. The isolation layer 1071 covers the edge of the first conductor material 106, and the first conductor material 106 is exposed in the middle of the isolation layer 1071. The isolation layer 1071 is an insulating material.

[0091] A second barrier adhesion layer 108 and a wiring layer are formed on the rigid mask 102. The wiring layer includes a second conductor material 109, which fills the middle of the isolation layer 1071. The second barrier adhesion layer 108 is disposed between the first conductor material 106 and the second conductor material 109.

[0092] Specifically, the substrate 101 is made of silicon, such as polycrystalline silicon or monocrystalline silicon. The substrate 101 is typically a wafer. A hard mask 102 is deposited on the substrate 101 using methods such as physical vapor deposition or chemical vapor deposition. The hard mask 102 is an insulating material, such as at least one of silicon dioxide, silicon nitride, and titanium nitride. These materials have good insulating properties and high structural strength. Those skilled in the art can determine the thickness of the hard mask 102 according to actual needs.

[0093] In a preferred embodiment, a silicon dioxide layer 1021 and a silicon nitride layer 1022 are deposited alternately to form a hard photomask 102. The silicon dioxide layer 1021 and the silicon nitride layer 1022 are alternately disposed along the thickness direction. The silicon dioxide layer 1021 generates compressive stress, while the silicon nitride layer 1022 generates tensile stress. The alternating silicon dioxide layer 1021 and silicon nitride layer 1022 effectively balance the tensile and compressive stresses, thereby effectively reducing the warpage of the hard photomask 102 and improving the overall strength of the semiconductor structure. The silicon nitride layer 1022 serves as an etch stop layer; that is, when etching the silicon dioxide layer 1021, etching stops at the silicon nitride layer 1022 to control the etching depth. In this way, the silicon nitride layer 1022 effectively avoids the problem of excessive etching depth. In other embodiments, the etch stop layer is made of at least one of silicon oxynitride and silicon carbonitride. Both of these materials can control the etching depth.

[0094] Through-holes 103 are formed on the rigid photomask 102 using methods such as wet etching or dry etching. The size and depth of the through-holes 103 can be set by those skilled in the art according to actual needs.

[0095] An insulating layer 104 and a first barrier adhesion layer 105 are formed on a substrate 101 using methods such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). Both the insulating layer 104 and the first barrier adhesion layer 105 are located within a via 103. The first barrier adhesion layer 105 forms a cavity within the via 103. The materials of the insulating layer 104 and the first barrier adhesion layer 105 are as described previously. The first conductor material 106 is a metal, such as copper, gold, or silver. The first conductor material 106 is formed within the cavity using electroplating. Before electroplating, to ensure the electroplated metal adheres firmly to the first barrier adhesion layer 105, a seed layer is formed on the first barrier adhesion layer 105 using physical sputtering. The material of the seed layer is the same as that of the first conductor material 106. The seed layer forms a crystal nucleus, allowing the metal to grow on the nucleus during electroplating, resulting in a better electroplating effect.

[0096] The first barrier adhesion layer 105 at the opening 1031 of the via is etched away using an etching process. An isolation layer 1071 is then formed at the opening 1031 using methods such as physical vapor deposition or chemical vapor deposition. For example, an isolation layer 1071 can be deposited integrally on a hard mask 102, and then etching is used to retain the isolation layer 1071 at the opening 1031 while removing the isolation layer 1071 at other locations. The material of the isolation layer 1071 may be, but is not limited to, insulating materials such as silicon nitride and silicon carbide.

[0097] A second barrier adhesion layer 108 is formed on a rigid mask 102 using methods such as physical vapor deposition or chemical vapor deposition. The wiring layer can also be formed using the aforementioned deposition methods. A second conductor material 109 fills the middle of the isolation layer 1071. The second barrier adhesion layer 108 separates the first conductor material 106 and the second conductor material 109.

[0098] The above preparation method is characterized by its simple process and stable semiconductor structure.

[0099] In one example, an insulating layer 1071 is formed at the opening 1031 of the through-hole. The insulating layer 1071 covers the edge of the first conductor material 106, with the first conductor material 106 exposed in the middle of the insulating layer 1071. The insulating layer 1071 is an insulating material comprising:

[0100] Remove the first conductor material 106 and the first barrier adhesive layer 105 at the opening 1031 of the through hole;

[0101] An isolation film 107 is deposited on the rigid mask 102 and at the opening 1031 of the through hole;

[0102] The isolation film layer 107 on the rigid mask 102 is removed to form the isolation layer 1071 at the opening 1031 of the through hole, with the first conductor material 106 exposed in the middle of the isolation layer 1071.

[0103] For example, the first conductor material 106 and the first barrier adhesion layer 105 at the opening 1031 of the via are removed using a dry etching process or a wet etching process. The isolation film layer 107 is an insulating material, such as at least one of silicon oxycarbide, silicon oxyfluoride, and organic polymer.

[0104] In this way, the resulting insulating layer 1071 has a complete structure and uniform thickness, and can achieve good insulation effect.

[0105] In one example, an isolation film 107 is deposited on the rigid mask 102 and at the opening 1031 of the through-hole, comprising:

[0106] The isolation film 107 was deposited using chemical vapor deposition. The isolation film 107 formed by this method has a uniform thickness and a complete structure.

[0107] In one example, removing the isolation layer 107 on the rigid mask 102 to form the isolation layer 1071 at the opening 1031 of the via, with the first conductor material 106 exposed in the middle of the isolation layer 1071, includes removing the isolation layer 107 using anisotropic dry etching.

[0108] This method ensures that an annular insulating layer 1071 is formed at the opening 1031 of the through hole to isolate the edge of the first conductor material 106.

[0109] In one example, a hard mask 102 is deposited on the substrate 101, including:

[0110] The hard mask 102 is formed by alternately depositing silicon dioxide layer 1021 and silicon nitride layer 1022 on the substrate 101 using chemical vapor deposition.

[0111] In this way, the silicon dioxide layer 1021 and the silicon nitride layer 1022 formed are of uniform thickness. The bonding strength between the two film layers is high. The alternating arrangement of the silicon dioxide layer 1021 and the silicon nitride layer 1022 can effectively prevent warping of the rigid photomask 102.

[0112] In one example, an insulating layer 104 and a first barrier adhesion layer 105 are formed on the substrate 101. A cavity is formed within the first barrier adhesion layer 105. The cavity has an opening 1031 located on the side of the rigid mask 102 opposite to the substrate 101. The cavity is filled with a first conductive material 106, comprising:

[0113] The insulating layer 104 is deposited in the through-hole 103 using atomic layer deposition.

[0114] The first barrier adhesion layer 105 and the seed layer of the first conductor material 106 are deposited in the through hole 103 by physical sputtering.

[0115] The first conductor material 106 is electroplated onto the seed layer using a chemical electroplating method.

[0116] Atomic layer deposition (ALD) is a method of depositing material layer by layer in the form of single-atom films onto the surface of the through-hole 103. This method produces an insulating layer 104 with precise thickness and high controllability. ACD can form a uniform insulating layer 104 within the through-hole 103.

[0117] Physical sputtering refers to bombarding the target surface with ions, ejecting atoms from the target to form sputtering. The sputtered atoms are deposited on the inner wall of the through-hole 103. This method can form a uniform and dense first barrier adhesion layer 105, and the seed layer can be uniformly attached to the first barrier adhesion layer 105. The seed layer can form crystal nuclei during electroplating, thereby significantly increasing the efficiency of electroplating and making the formation of the first conductor material 106 faster and more uniform.

[0118] In one example, the removal of the first conductor material 106 and the first barrier adhesion layer 105 at the opening 1031 of the through-hole using an etching process includes:

[0119] The etching process described is a wet etching process.

[0120] The wet etching process can precisely remove the first conductor material 106 and the first barrier adhesion layer 105 at the via opening 1031.

[0121] In one example, a second barrier adhesion layer 108 and a wiring layer are formed on the rigid mask 102. The wiring layer includes a second conductor material 109, which fills the middle of the insulating layer 1071. The second barrier adhesion layer 108 is disposed between the first conductor material 106 and the second conductor material 109, and includes:

[0122] A silicon nitride thin film was deposited as an etch stop layer using chemical vapor deposition, and a highly filled silicon dioxide thin film was deposited on the silicon nitride thin film.

[0123] Silicon nitride prevents etching by the etching solution. As an etching stop layer, silicon nitride ensures etching accuracy. A highly filled silicon dioxide film has good insulating properties and can serve as an interlayer dielectric for the second conductor material 109. Wiring trenches are formed by etching the silicon dioxide film. The etching stop layer is used as the termination point. The second conductor material 109 is then filled into the wiring trenches to form electrodes.

[0124] In one example, the wiring trench is a metal wiring trench. The metal wiring pattern is formed on photoresist using a photolithography process.

[0125] The silicon dioxide thin film is etched using a dry etching method to form metal wiring trenches.

[0126] The metal wiring channel is filled with a metal material as a second conductor material 109.

[0127] In one example, a wet etching process is used to etch the etching stop layer;

[0128] The second barrier adhesion layer 108 and the seed layer of the second conductor material 109 are sequentially deposited in the metal wiring trench using a physical sputtering method.

[0129] The first conductor material 106 can be exposed by wet etching of the etch stop layer. A second barrier adhesion layer 108 and a seed layer of the second conductor material 109 can be formed on the first conductor material 106 by physical sputtering.

[0130] Furthermore, the second conductor material 109 is electroplated in the metal wiring trench using a chemical electroplating method. The seed layer is made of the same material as the second conductor material 109. The seed layer can form crystal nuclei, which makes the electroplating of the second conductor material 109 easier, the plating layer more uniform, and the second conductor material 109 more firmly bonded to the second barrier adhesion layer 108.

[0131] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor structure, characterized in that, include: Substrate (101); A rigid photomask (102) is formed on the substrate (101); A through-hole (103) extends through the rigid mask (102) and into the substrate (101), the through-hole (103) being filled with a first conductive material (106), the first conductive material being etched back to a set depth to form an opening (1031) of the through-hole, an isolation layer (1071) being formed at the opening (1031) of the through-hole, the isolation layer (1071) covering the edge of the first conductive material (106), the first conductive material (106) being exposed in the middle of the isolation layer (1071); and A second conductor material (109) is filled in the middle of the isolation layer (1071), and a barrier adhesion layer (108) is provided between the first conductor material (106) and the second conductor material (109).

2. The semiconductor structure according to claim 1, characterized in that, The material of the isolation layer (1071) is at least one of silicon dioxide, silicon fluoride, and organic polymer.

3. The semiconductor structure according to claim 1, characterized in that, The isolation layer (1071) is annular, and the outer diameter of the isolation layer (1071) gradually increases from the side closer to the first conductor material (106) to the side farther away from the first conductor material (106).

4. The semiconductor structure according to claim 1, characterized in that, The thickness of the isolation layer at its highest point is 0.5μm-10μm, and the height of the isolation layer is 1μm-3μm.

5. The semiconductor structure according to claim 4, characterized in that, The hard mask (102) includes a silicon dioxide layer (1021) and a silicon nitride layer (1022) alternately arranged along the thickness direction, wherein the silicon nitride layer is an etch stop layer.

6. A method for fabricating a semiconductor structure, characterized in that, include: Substrate (101) is provided; A hard mask template (102) is deposited on the substrate (101); A through hole (103) is formed on the rigid mask (102), and the through hole (103) extends to the substrate (101). The through hole is filled with a first conductor material (106); The first conductor material (106) at the opening (1031) of the through hole is removed by an etching process. An isolation layer (1071) is formed at the opening (1031) of the through hole, the isolation layer (1071) covering the edge of the first conductor material (106), and the first conductor material (106) exposed in the middle of the isolation layer (1071); A barrier adhesion layer (108) and a second conductor material (109) are formed on the rigid mask (102). The second conductor material (109) fills the middle of the isolation layer (1071). The barrier adhesion layer (108) is disposed between the first conductor material (106) and the second conductor material (109).

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, An insulating layer (1071) is formed at the opening (1031) of the through-hole. The insulating layer (1071) covers the edge of the first conductor material (106), and the first conductor material (106) is exposed in the middle of the insulating layer (1071). The insulating layer (1071) includes: An isolation film (107) is deposited on the rigid mask (102) and at the opening (1031) of the through hole. Remove the isolation film layer (107) on the rigid mask (102) to form the isolation layer (1071) at the opening (1031) of the through hole, with the first conductor material (106) exposed in the middle of the isolation layer (1071).

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The isolation membrane layer (107) was deposited using chemical vapor deposition. The isolation film layer (107) is removed by anisotropic dry etching.

9. An electronic device, characterized in that, Includes the semiconductor structure as described in any one of claims 1-5.

10. The electronic device according to claim 9, characterized in that, The device includes a first component and a second component, with the semiconductor structure located between the first component and the second component. The first component is connected to the second conductor material, and the first conductor material is connected to the second component at the end of the through-hole opposite to the second conductor material. The first component is connected to the second component through the first conductor material and the second conductor material.

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