Array substrate and display panel

Abstract

This application relates to an array substrate and a display panel. The array substrate includes a substrate and pixel circuitry disposed on the substrate. The pixel circuitry includes at least an initialization signal line, a first scan signal line, and at least one initialization transistor. The first scan signal line includes a first main line and a first branch line. The initialization transistor includes an active layer and a gate. The active layer includes a first sub-active portion connected to the initialization signal line. A first orthographic projection of the first sub-active portion on the substrate is located between a second orthographic projection of the first main line on the substrate and a third orthographic projection of the initialization signal line on the substrate. A fourth orthographic projection of the first branch line on the substrate overlaps with the first orthographic projection. The region on the first branch line corresponding to the overlapping portion serves as the gate of the initialization transistor. The above array substrate design reduces the space occupied by the first scan signal line traces, improves the light transmittance of the display panel, and thus improves the display quality of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Currently, in the conventional LTPS (Low Temperature Poly-Silicon) pixel circuit layout design, the pixel circuit includes a first initialization transistor and a second initialization transistor. The first initialization transistor adopts a dual-gate structure and is used to initialize the storage capacitor of the current row. The second initialization transistor adopts a single-gate structure and is used to initialize the anode of the previous stage light-emitting device.

[0003] This configuration results in a greater number of film layers stacked at the locations of the first initialization transistor and the upstream second initialization transistor. When a large number of metal film layers are involved, it will affect the light transmittance of the display panel, thereby affecting the display quality of the display panel. Summary of the Invention

[0004] Therefore, it is necessary to provide an array substrate and a display panel that can improve the light transmittance of the display panel in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides an array substrate, the array substrate including a substrate and a pixel circuit disposed on the substrate; the pixel circuit is used to drive a correspondingly connected light-emitting device to emit light, and the pixel circuit includes at least:

[0006] Initialization signal line, used to provide initialization signals;

[0007] The first scan signal line includes a first main line and a first branch line. The first branch line is connected to the first main line and is located on the side of the first main line close to the initialization signal line. The first scan signal line is used to provide a first scan signal.

[0008] At least one initialization transistor, the initialization transistor including an active layer and a gate, the active layer including a first sub-active portion, the first sub-active portion being connected to the initialization signal line, the first orthographic projection of the first sub-active portion on the substrate being located between the second orthographic projection of the first main line on the substrate and the third orthographic projection of the initialization signal line on the substrate, the fourth orthographic projection of the first branch line on the substrate overlapping the first orthographic projection, and the region on the first branch line corresponding to the overlapping portion of the fourth orthographic projection and the first orthographic projection serving as the gate of the initialization transistor.

[0009] The aforementioned array substrate, by including an active layer and a gate in the initialization transistor, wherein the active layer includes a first sub-active portion connected to the initialization signal line, and the first orthographic projection of the first sub-active portion on the substrate is located between the second orthographic projection of the first main line on the substrate and the third orthographic projection of the initialization signal line on the substrate, and the fourth orthographic projection of the first branch line on the substrate overlaps with the first orthographic projection, and a portion of the first branch line serves as the gate of the initialization transistor, thereby eliminating the need for the active layer to undergo multiple large-scale bending as in related technologies, thus reducing the space occupied by the first scan signal line trace. Therefore, a light-transmitting area can be formed on the side of the first scan signal line away from the initialization signal line, improving the light transmittance of the display panel and thus improving the display quality of the display panel.

[0010] In one embodiment, the at least one initialization transistor includes a first initialization transistor and a second initialization transistor, the first initialization transistor including the active layer, a first gate and a second gate, and the second initialization transistor including the active layer and a gate;

[0011] The first scan signal line further includes a second branch line, which is connected to the first main line and located on the side of the first main line close to the initialization signal line. The fifth orthographic projection of the second branch line on the substrate overlaps with the first orthographic projection, and the second orthographic projection overlaps with the orthographic projection of the active layer on the substrate.

[0012] Wherein, the region on the first main line corresponding to the overlap of the second orthographic projection and the orthographic projection of the active layer on the substrate serves as the first gate of the first initialization transistor, the region on the first branch line corresponding to the overlap of the fourth orthographic projection and the first orthographic projection serves as the second gate of the first initialization transistor, and the region on the second branch line corresponding to the overlap of the fifth orthographic projection and the first orthographic projection serves as the gate of the second initialization transistor.

[0013] The aforementioned array substrate, through the above-described configuration, can form a dual-gate first initialization transistor and a single-gate second initialization transistor. The gates of both the first and second initialization transistors are connected to a first scan signal line, allowing the switching states of the first and second initialization transistors to be controlled via the first scan signal line. Furthermore, the active layer in this embodiment does not require multiple bends as in related technologies, thus reducing the space occupied by the active layer traces and freeing up wiring-free space. Therefore, a light-transmitting area can be formed on the side of the first scan signal line away from the initialization signal line, improving the light transmittance of the display panel and consequently enhancing the display image quality.

[0014] In one embodiment, the initialization signal line and the first main line extend along a first direction, and the first branch line and the second branch line extend along a second direction. This causes the first and second branch lines to extend towards the initialization signal line. Furthermore, since the first orthographic projection of the first sub-active portion on the substrate is located between the second and third orthographic projections, the first sub-active portion does not require significant bending to allow the first orthographic projection to overlap with the fourth and fifth orthographic projections respectively, thereby optimizing the routing and forming a light-transmitting area on the side of the first scan signal line away from the initialization signal line.

[0015] In one embodiment, both the fourth orthographic projection and the fifth orthographic projection are located between the second orthographic projection and the third orthographic projection, and the first direction intersects the second direction. Therefore, the first branch and the second branch are located on the same side of the first main line, allowing the fourth and fifth orthographic projections to overlap with the second orthographic projection.

[0016] In one embodiment, the first direction is perpendicular to the second direction, thereby optimizing the routing direction of each signal line.

[0017] In one embodiment, the active layer further includes a second sub-active portion and a third sub-active portion. The second sub-active portion is connected to a first end of the first sub-active portion, and the third sub-active portion is connected to a second end of the first sub-active portion. The second sub-active portion is located on the side of the first main line close to the initialization signal line. The second sub-active portion is connected to the anode of the light-emitting device. The sixth orthographic projection of the third sub-active portion on the substrate overlaps with the second orthographic projection.

[0018] In this embodiment, by connecting the second sub-active portion to the first terminal of the first sub-active portion and the anode of the light-emitting device, the source or drain of the second initialization transistor is connected to the anode of the light-emitting device. Furthermore, since the first sub-active portion is connected to the initialization signal line, when the second initialization transistor is turned on, the initialization signal can initialize the anode of the light-emitting device via the second initialization transistor. The third sub-active portion is connected to the second terminal of the first sub-active portion, and the sixth orthographic projection of the third sub-active portion on the substrate overlaps with the second orthographic projection. Therefore, the region on the first main line corresponding to the overlapping projection can serve as the first gate of the first initialization transistor.

[0019] In one embodiment, the first sub-active portion extends along a first direction, and the second sub-active portion extends along a second direction, wherein the first direction intersects the second direction.

[0020] In this embodiment, the initialization signal line and the first main line extend along a first direction, and the first sub-active portion also extends along the first direction. This allows for a smaller interval between the orthographic projections of the initialization signal line and the first main line on the substrate, thereby increasing the non-signal wiring space on the side of the first main line away from the initialization signal line and thus increasing the area of ​​the light-transmitting region. The second sub-active portion extends along a second direction and can be connected to the anode of the light-emitting device.

[0021] In one embodiment, the pixel circuit further includes a second scan signal line located on the side of the first main line away from the initialization signal line. This second scan signal is then provided to the gate of the corresponding transistor via the second scan signal line.

[0022] In one embodiment, the second scan signal line includes a second main line and a third branch line, the second main line being connected to the third branch line, and the third branch line being located on the side of the second main line closer to the first scan signal line;

[0023] The third sub-active part includes a first branch and a second branch. The first end of the first branch is connected to the second end of the first sub-active part, and the second end of the first branch is connected to the second branch. The seventh orthographic projection of the first branch on the substrate overlaps with the second orthographic projection, and the eighth orthographic projection of the second branch on the substrate overlaps with the orthographic projections of the second main line and the third branch on the substrate, respectively.

[0024] The pixel circuit further includes a threshold compensation transistor, which includes a second branch, a first gate, and a second gate. The region on the second main line corresponding to the overlap between the orthographic projection of the second main line on the substrate and the eighth orthographic projection serves as the first gate of the threshold compensation transistor, and the region on the third branch corresponding to the overlap between the orthographic projection of the third branch on the substrate and the eighth orthographic projection serves as the second gate of the threshold compensation transistor.

[0025] In this embodiment, the above settings allow the second scanning signal to control the switching on and off of the threshold compensation transistor, resulting in a wiring-free space, i.e., a light-transmitting area, between the second branch and the first main line.

[0026] In one embodiment, the first sub-active portion extends along a first direction, the second sub-active portion extends along a second direction, and the first branch extends along the second direction, with the first direction intersecting the second direction. This allows the orthographic projection of the first branch onto the substrate to overlap with the second orthographic projection, enabling the region corresponding to the overlapping projection of the first main line to serve as the first gate of the first initialization transistor.

[0027] In one embodiment, the pixel circuit further includes a first power signal line extending along a second direction, the orthographic projection of the first power signal line on the substrate overlapping the seventh orthographic projection. The first power signal line extends along the second direction to connect to one plate of the storage capacitor Cst for writing a first power supply voltage.

[0028] Secondly, this application also provides a display panel, including the array substrate described above.

[0029] The aforementioned display panel includes the aforementioned array substrate. In the pixel circuit of the aforementioned array substrate, a light-transmitting area can be formed on the side of the first scan signal line away from the initialization signal line, thereby improving the light transmittance of the display panel and thus improving the display quality of the display panel. Therefore, the display panel described in this embodiment has a high display quality. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a planar schematic diagram of the pixel circuit of an array substrate in related technologies;

[0032] Figure 2 for Figure 1 A plan view of part of the structure within the dashed box;

[0033] Figure 3 This is a schematic diagram of the equivalent circuit of the pixel circuit in the related technology;

[0034] Figure 4 This is a planar schematic diagram of the pixel circuit of the array substrate in one embodiment of this application;

[0035] Figure 5 for Figure 4 A planar schematic diagram of part of the structure of the mid-pixel circuit. Detailed Implementation

[0036] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0038] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0039] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as "on" another layer or substrate, the layer or element may be directly on said other layer or substrate, or there may be intermediate layers. Furthermore, it is understood that when a layer is referred to as "between" two layers, the layer may be the only layer between said two layers, or there may be one or more intermediate layers. Additionally, the same reference numerals always denote the same elements.

[0040] In the following embodiments, when a layer, region, or element is “connected,” it can be interpreted as the layer, region, or element being connected not only directly but also through other constituent elements placed therebetween. For example, when a layer, region, element, etc., is described as being connected or electrically connected, the layer, region, element, etc., can not only be directly connected or directly electrically connected, but can also be connected or electrically connected through another layer, region, element, etc., placed therebetween.

[0041] In the following text, although terms such as “first” and “second” may be used to describe various components, these components are not necessarily limited to the terms above. The terms above are only used to distinguish one component from another. It will also be understood that expressions used in the singular form include plural expressions, unless the singular form has a distinctly different meaning in the context.

[0042] When a phrase such as “at least one of…” follows a list of elements, it modifies the entire list of elements, not individual elements within that list. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. As used in the application documents, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0043] While exemplary embodiments of the display module and the display device including the display module have been specifically described herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that the display module and the display device including the display module, constructed according to the principles of this application, may be implemented in ways other than those specifically described herein. This application is also defined in the claims and their equivalents.

[0044] As described in the background section, in conventional LTPS (Low Temperature Poly-Silicon) pixel circuit layout design, such as Figures 1 to 3 As shown, the pixel circuit includes a first initialization transistor T4 and a second initialization transistor T7. The first initialization transistor T4 adopts a dual-gate structure and is used to initialize the storage capacitor of this row. The second initialization transistor T7 adopts a single-gate structure and is used to initialize the anode of the previous stage light-emitting device.

[0045] After long-term research, the inventors discovered that, in order to save space occupied by the scan signal lines, the first initialization transistor T4 of this row needs to be turned on simultaneously with the second initialization transistor T7 of the previous row, as detailed below. Figure 1 As shown, Figure 1 In the pixel circuit, there are first initialization transistors T4 and second initialization transistors T7. The first initialization transistor T4 includes the active layer 11, a first gate, and a second gate. The second initialization transistor T7 includes the active layer 11 and a gate. The first scan signal line S1 uses a first metal layer and extends along a first direction. The active layer 11 is bent multiple times so that the orthographic projection of the active layer 11 on the substrate overlaps with the orthographic projection of the first scan signal line S1 on the substrate three times. The regions on the first scan signal line S1 corresponding to the three overlapping projections serve as the first gate, the second gate of the first initialization transistor T4, and the gate of the second initialization transistor T7, respectively.

[0046] This layout design results in a bent layout of the active layer 11, which compresses the layout space. When the PPI (Pixels Per Inch) is high, it is easy to cause more film layers to be stacked at the positions of the first initialization transistor T4 and the upper second initialization transistor T7. When more metal film layer processes are involved, it will affect the light transmittance of the display panel, and thus affect the display quality of the display panel.

[0047] For the reasons mentioned above, such as Figure 4 and Figure 5 As shown, this application provides an array substrate, the array substrate including a substrate and a pixel circuit disposed on the substrate; the pixel circuit is used to drive a correspondingly connected light-emitting device to emit light, and the pixel circuit includes at least: an initialization signal line vref', a first scan signal line S1' and at least one initialization transistor.

[0048] The initialization signal line 'vref' is used to provide initialization signals.

[0049] The first scan signal line S1' includes a first main line 221 and a first branch line 222. The first branch line 222 is connected to the first main line 221 and is located on the side of the first main line 221 close to the initialization signal line vref'. The first scan signal line S1' is used to provide a first scan signal.

[0050] The initialization transistor includes an active layer 21 and a gate. The active layer 21 includes a first sub-active portion 211, which is connected to the initialization signal line vref'. The first orthographic projection of the first sub-active portion 211 on the substrate is located between the second orthographic projection of the first main line 221 on the substrate and the third orthographic projection of the initialization signal line vref' on the substrate. The fourth orthographic projection of the first branch line 222 on the substrate overlaps with the first orthographic projection. The area on the first branch line 222 corresponding to the overlap between the fourth orthographic projection and the first orthographic projection serves as the gate of the initialization transistor.

[0051] It should be noted that, in this application, if Figure 4 As shown, the X direction is the first direction, and the Y direction is the second direction. The equivalent circuit of the pixel circuit in this application can also be found in [reference needed]. Figure 3 , Figure 3 T4 in this context corresponds to T4' in this application. Figure 3 T7 in this application corresponds to T7' in this application.

[0052] Specifically, the array substrate may include a first metal layer and a second metal layer. The first scan signal line S1' may use the first metal layer, and the initialization signal line vref' may use the second metal layer. Since the fourth orthographic projection of the first branch line 222 on the substrate overlaps with the first orthographic projection, the region corresponding to the overlapping projection of the first scan signal line S1' (first metal layer) can be used as the gate of the initialization transistor. Furthermore, since the first orthographic projection of the first sub-active portion 211 on the substrate is located between the second orthographic projection of the first main line 221 on the substrate and the third orthographic projection of the initialization signal line vref' on the substrate, the active layer 21 of this application does not need to be as described above. Figure 1 The active layer 11 shown undergoes multiple large-amplitude bends; for example, the first sub-active portion 211 can extend along the first direction without bending. However, if the active layer 21 is not bent multiple times, it will relatively... Figure 1 The pixel circuit layout design shown reduces the space occupied by the active layer 21 traces, thereby allowing a light-transmitting area to be set on the side of the first scan signal line S1' away from the initialization signal line vref', improving the light transmittance of the display panel and thus enhancing the display image quality. The second orthographic projection is adjacent to the orthographic projection of the light-transmitting area on the substrate.

[0053] The aforementioned array substrate, by including an active layer 21 and a gate in the initialization transistor, wherein the active layer 21 includes a first sub-active portion 211 connected to the initialization signal line vref', the first orthographic projection of the first sub-active portion 211 on the substrate is located between the second orthographic projection of the first main line 221 on the substrate and the third orthographic projection of the initialization signal line vref' on the substrate, and the fourth orthographic projection of the first branch line 222 on the substrate overlaps with the first orthographic projection, and a portion of the first branch line 222 serves as the gate of the initialization transistor, thereby eliminating the need for the active layer 21 to undergo multiple large-amplitude bends as in the related technology's active layer 11, thus reducing the space occupied by the active layer 21 wiring. Therefore, a light-transmitting area can be formed on the side of the first scan signal line S1' away from the initialization signal line vref', improving the light transmittance of the display panel and thus improving the display quality of the display panel.

[0054] In one embodiment, such as Figure 4 and Figure 5 As shown, the at least one initialization transistor includes a first initialization transistor T4' and a second initialization transistor T7'. The first initialization transistor T4' includes the active layer 21, a first gate, and a second gate. The second initialization transistor T7' includes the active layer 21 and a gate.

[0055] The first scan signal line S1' further includes a second branch 223, which is connected to the first main line 221 and located on the side of the first main line 221 closer to the initialization signal line vref'. The fifth orthographic projection of the second branch 223 on the substrate overlaps with the first orthographic projection. Furthermore, the second orthographic projection of the first main line 221 on the substrate overlaps with the orthographic projection of the active layer 21 on the substrate.

[0056] Specifically, the region on the first main line 221 corresponding to the overlapping portion of the second orthographic projection and the orthographic projection of the active layer 21 on the substrate serves as the first gate of the first initialization transistor T4', the region on the first branch line 222 corresponding to the overlapping portion of the fourth orthographic projection and the first orthographic projection serves as the second gate of the first initialization transistor T4', and the region on the second branch line 223 corresponding to the overlapping portion of the fifth orthographic projection and the first orthographic projection serves as the gate of the second initialization transistor T7'.

[0057] The first main line 221 is used to receive the first scan signal. Since the first branch line 222 and the second branch line 223 are respectively connected to the first main line 221, when the first main line 221 receives the first scan signal, the first scan signal can also be transmitted to the first branch line 222 and the second branch line 223. Since the orthographic projections of the first main line 221, the first branch line 222, and the second branch line 223 on the substrate all intersect with the orthographic projection of the active layer 21 on the substrate, the regions of the overlapping projection portions of the first main line 221, the first branch line 222, and the second branch line 223 can also be used as gates. Therefore, the regions of the overlapping projection portions on the first main line 221 and the first branch line 222 can be used as the first gate and the second gate of the first initialization transistor T4', respectively, and the region of the overlapping projection portion on the second branch line 223 can be used as the gate of the second initialization transistor T7'.

[0058] In this embodiment, by adding a first branch line 222 and a second branch line 223, and placing the first branch line 222 and the second branch line 223 on the side of the first main line 221 close to the initialization signal line vref', the overlapping projection regions on the first main line 221 and the first branch line 222 are respectively used as the first gate and the second gate of the first initialization transistor T4', and the overlapping projection region on the second branch line 223 is used as the gate of the second initialization transistor T7', thereby eliminating the need for the active layer 21 in this embodiment, as described in related technologies. Figure 1The active layer 11 shown is bent multiple times, thereby reducing the space occupied by the active layer 21 traces and freeing up space without wiring. Therefore, a light-transmitting area can be formed on the side of the first scan signal line S1' away from the initialization signal line vref', improving the light transmittance of the display panel and thus improving the display quality of the display panel.

[0059] In one embodiment, such as Figure 4 and Figure 5 As shown, the initialization signal line vref' and the first main line 221 extend along the first direction, and the first branch line 222 and the second branch line 223 extend along the second direction. Specifically, the fourth orthographic projection and the fifth orthographic projection are both located between the second orthographic projection and the third orthographic projection, and the first direction intersects the second direction.

[0060] It is understandable that the first direction is perpendicular to the second direction.

[0061] It can be understood that if the initialization signal line vref' and the first main line 221 extend along the first direction, then the initialization signal line vref' and the first main line 221 are parallel. By making the first branch line 222 and the second branch line 223 extend along the second direction, since the first direction intersects with the second direction, the first branch line 222 and the second branch line 223 extend towards the initialization signal line vref'. Furthermore, since the first orthographic projection of the first sub-active part 211 on the substrate is located between the second orthographic projection and the third orthographic projection, the first sub-active part 211 does not need to be bent significantly to make the first orthographic projection overlap with the fourth orthographic projection and the fifth orthographic projection respectively. For example, the first sub-active portion 211 can extend along the first direction. At this time, the first sub-active portion 211, the initialization signal line vref', and the first main line 221 are parallel. The orthographic projections of the initialization signal line vref' and the first main line 221 on the substrate can be spaced smaller, thereby increasing the non-signal wiring space on the side of the first main line 221 away from the initialization signal line vref', thereby increasing the area of ​​the light-transmitting area, improving the light transmittance of the display panel, and thus improving the display quality of the display panel.

[0062] In one embodiment, such as Figure 4 and Figure 5As shown, the active layer 21 further includes a second sub-active portion 212 and a third sub-active portion 213. The second sub-active portion 212 is connected to the first end of the first sub-active portion 211, and the third sub-active portion 213 is connected to the second end of the first sub-active portion 211. The second sub-active portion 212 is located on the side of the first main line 221 near the initialization signal line vref'. The second sub-active portion 212 is connected to the anode of the light-emitting device. The sixth orthographic projection of the third sub-active portion 213 on the substrate overlaps with the second orthographic projection.

[0063] In this embodiment, by connecting the second sub-active portion 212 to the first end of the first sub-active portion 211 and the anode of the light-emitting device, the source or drain of the second initialization transistor T7' is connected to the anode of the light-emitting device. Furthermore, since the first sub-active portion 211 is connected to the initialization signal line vref', when the second initialization transistor T7' is turned on, the initialization signal can initialize the anode of the light-emitting device via the second initialization transistor T7'. The third sub-active portion 213 is connected to the second end of the first sub-active portion 211. The sixth orthographic projection of the third sub-active portion 213 on the substrate overlaps with the second orthographic projection. Therefore, the region on the first main line 221 corresponding to the overlapping projection can serve as the first gate of the first initialization transistor T4'.

[0064] In one embodiment, such as Figure 4 As shown, the first sub-active portion 211 extends along a first direction, and the second sub-active portion 212 extends along a second direction, with the first direction intersecting the second direction.

[0065] Based on the above embodiments, since the initialization signal line vref' and the first main line 221 extend along the first direction, the first sub-active portion 211 also extends along the first direction. This allows the orthographic projections of the initialization signal line vref' and the first main line 221 on the substrate to be less spaced, thereby increasing the non-signal wiring space on the side of the first main line 221 away from the initialization signal line vref'. This increases the area of ​​the light-transmitting region, improves the light transmittance of the display panel, and ultimately improves the display quality of the display panel. Furthermore, since the second initialization transistor T7' needs to initialize the anode of the previous stage light-emitting device, and the anode of the light-emitting device is located on the side of the initialization signal line vref' away from the first main line 221, the second sub-active portion 212 needs to extend along the second direction to connect with the anode of the light-emitting device.

[0066] In one embodiment, such as Figure 4 As shown, the pixel circuit also includes a second scan signal line S2, which is located on the side of the first main line 221 away from the initialization signal line vref'.

[0067] The second scan signal line S2 is used to provide the second scan signal.

[0068] In one embodiment, such as Figure 4 As shown, the second scan signal line S2 includes a second main line 231 and a third branch line 232. The second main line 231 is connected to the third branch line 232, and the third branch line 232 is located on the side of the second main line 231 close to the first scan signal line S1'.

[0069] The third sub-active part 213 includes a first branch 2131 and a second branch 2132. The first end of the first branch 2131 is connected to the second end of the first sub-active part 211, and the second end of the first branch 2131 is connected to the second branch 2132. The seventh orthographic projection of the first branch 2131 on the substrate overlaps with the second orthographic projection. The eighth orthographic projection of the second branch 2132 on the substrate overlaps with the orthographic projections of the second main line 231 and the third branch 232 on the substrate, respectively.

[0070] The pixel circuit further includes a threshold compensation transistor T3, which includes a second branch 2132, a first gate, and a second gate. The region on the second main line 231 corresponding to the overlap between the orthographic projection of the second main line on the substrate and the eighth orthographic projection serves as the first gate of the threshold compensation transistor T3, and the region on the third branch 232 corresponding to the overlap between the orthographic projection of the third branch on the substrate and the eighth orthographic projection serves as the second gate of the threshold compensation transistor T3.

[0071] The second scan signal line S2 can utilize the first metal layer. Since the overlapping region of the projection on the second main line 231 serves as the first gate of the threshold compensation transistor T3, and the overlapping region of the projection on the third branch line 232 serves as the second gate of the threshold compensation transistor T3, the second scan signal can be transmitted to both the first and second gates of the threshold compensation transistor T3, thereby controlling the on / off state of the threshold compensation transistor T3 through the second scan signal. There is a no-wiring space, i.e., a light-transmitting area, between the second branch 2132 and the first main line 221. This light-transmitting area is horizontally adjacent to both the second branch 2132 and the first main line 221.

[0072] Specifically, based on the inventor's simulation data calculations, the area of ​​the light-transmitting region in this application occupies the area where the first initialization transistor T4' and the second initialization transistor T7' are located (e.g., Figure 5 The proportion of the area (of the area range) compared to existing technologies such as Figure 1The area ratio of the light-transmitting zone shown can be increased by 38%, which significantly improves the light transmittance of the display panel.

[0073] In one embodiment, such as Figure 4 As shown, the first active sub-part 211 extends along a first direction, the second active sub-part 212 extends along a second direction, and the first branch 2131 extends along the second direction, with the first direction intersecting the second direction.

[0074] It can be understood that the first sub-active portion 211 extends along the first direction, the second sub-active portion 212 extends along the second direction, and the first branch 2131 extends along the second direction. Then, the orthographic projection of the first branch 2131 on the substrate can overlap with the second orthographic projection, so that the area of ​​the first main line 221 corresponding to the overlapping projection can serve as the first gate of the first initialization transistor T4'.

[0075] In one embodiment, such as Figure 4 As shown, the pixel circuit also includes a first power signal line ELVDD, which extends along a second direction, and the orthographic projection of the first power signal line ELVDD on the substrate covers the seventh orthographic projection.

[0076] The storage capacitor Cst is located on the side of the second scan signal line S2 away from the first scan signal line S1'. The first power signal line ELVDD extends along the second direction and is connected to one plate of the storage capacitor Cst for writing the first power supply voltage.

[0077] Understandably, the pixel circuit may also include a second power supply signal line ELVSS for providing a second power supply voltage.

[0078] In the application, the pixel circuit also includes a light emission control signal line EM, a driving transistor T1, a data writing transistor T2, a first light emission control transistor T5, and a second light emission control transistor T6. The light emission control signal line EM provides a light emission control signal, and the driving transistor T1 provides a driving current to the light-emitting device. During the first writing phase, in response to the second scan signal S2, the data writing transistor T2 turns on its first and second terminals, thereby causing the first terminal of the driving transistor T1 to receive a data voltage Data. The data voltage Data is written to the gate of the driving transistor T1 by the first and second terminals of the driving transistor T1 and the threshold compensation transistor T3. During the light emission phase, the first and second terminals of the first light emission control transistor T5 are turned on, the first terminal of the driving transistor T1 is connected to a first power supply voltage, and the first and second terminals of the second light emission control transistor T6 are turned on, causing the second terminal of the driving transistor T1 to connect to the light-emitting device, thereby connecting to a second power supply voltage. This allows the driving transistor T1 to provide a driving current to the light-emitting device, driving it to emit light.

[0079] In one embodiment, this application also provides a display panel, including the array substrate described above.

[0080] The above-mentioned display panel includes the array substrate described in any of the above embodiments. In the pixel circuit of the array substrate, a light-transmitting area can be formed on the side of the first scan signal line away from the initialization signal line, thereby improving the light transmittance of the display panel and thus improving the display quality of the display panel. Therefore, the display panel described in this embodiment has a high display quality.

[0081] Based on the same inventive concept, this application also provides a display device (not shown), which includes the display panel in the above embodiments.

[0082] It is understood that the display device in the embodiments of this application can be any product or component with display function, such as OLED display device, QLED display device, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, Internet of Things device, etc., and the embodiments disclosed in this application do not limit this.

[0083] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized by, The array substrate includes a substrate and pixel circuits disposed on the substrate; The pixel circuit is used to drive the corresponding connected light-emitting device to emit light, and the pixel circuit includes at least: Initialization signal line, used to provide initialization signals; The first scan signal line includes a first main line and a first branch line. The first branch line is connected to the first main line and is located on the side of the first main line close to the initialization signal line. The first scan signal line is used to provide a first scan signal. At least one initialization transistor, the initialization transistor including an active layer and a gate, the active layer including a first sub-active portion, the first sub-active portion being connected to the initialization signal line, the first orthographic projection of the first sub-active portion on the substrate being located between the second orthographic projection of the first main line on the substrate and the third orthographic projection of the initialization signal line on the substrate, the fourth orthographic projection of the first branch line on the substrate overlapping the first orthographic projection, and the region on the first branch line corresponding to the overlapping portion of the fourth orthographic projection and the first orthographic projection serving as the gate of the initialization transistor; The at least one initialization transistor includes a first initialization transistor and a second initialization transistor, wherein the first initialization transistor includes the active layer, a first gate and a second gate, and the second initialization transistor includes the active layer and a gate; The first scan signal line further includes a second branch line, which is connected to the first main line and located on the side of the first main line close to the initialization signal line. The fifth orthographic projection of the second branch line on the substrate overlaps with the first orthographic projection, and the second orthographic projection overlaps with the orthographic projection of the active layer on the substrate. Wherein, the region on the first main line corresponding to the overlap of the second orthographic projection and the orthographic projection of the active layer on the substrate serves as the first gate of the first initialization transistor, the region on the first branch line corresponding to the overlap of the fourth orthographic projection and the first orthographic projection serves as the second gate of the first initialization transistor, and the region on the second branch line corresponding to the overlap of the fifth orthographic projection and the first orthographic projection serves as the gate of the second initialization transistor.

2. The array substrate of claim 1, wherein, The initialization signal line and the first main line extend along a first direction, and the first branch line and the second branch line extend along a second direction.

3. The array substrate of claim 2, wherein, The fourth orthographic projection and the fifth orthographic projection are both located between the second orthographic projection and the third orthographic projection, and the first direction intersects the second direction.

4. The array substrate according to any one of claims 1 to 3, wherein, The active layer further includes a second sub-active portion and a third sub-active portion. The second sub-active portion is connected to a first end of the first sub-active portion, and the third sub-active portion is connected to a second end of the first sub-active portion. The second sub-active portion is located on the side of the first main line close to the initialization signal line. The second sub-active portion is also connected to the anode of the light-emitting device. The sixth orthographic projection of the third sub-active portion on the substrate overlaps with the second orthographic projection.

5. The array substrate of claim 4, wherein, The first active sub-part extends along a first direction, and the second active sub-part extends along a second direction, wherein the first direction intersects the second direction.

6. The array substrate of claim 4, wherein, The pixel circuit further includes a second scan signal line, which is located on the side of the first main line away from the initialization signal line.

7. The array substrate of claim 6, wherein, The second scan signal line includes a second main line and a third branch line. The second main line is connected to the third branch line, and the third branch line is located on the side of the second main line closer to the first scan signal line. The third sub-active part includes a first branch and a second branch. The first end of the first branch is connected to the second end of the first sub-active part, and the second end of the first branch is connected to the second branch. The seventh orthographic projection of the first branch on the substrate overlaps with the second orthographic projection, and the eighth orthographic projection of the second branch on the substrate overlaps with the orthographic projections of the second main line and the third branch on the substrate, respectively. The pixel circuit further includes a threshold compensation transistor, which includes a second branch, a first gate, and a second gate. The region on the second main line corresponding to the overlap between the orthographic projection of the second main line on the substrate and the eighth orthographic projection serves as the first gate of the threshold compensation transistor, and the region on the third branch corresponding to the overlap between the orthographic projection of the third branch on the substrate and the eighth orthographic projection serves as the second gate of the threshold compensation transistor.

8. The array substrate of claim 7, wherein, The first active part extends along a first direction, the second active part extends along a second direction, the first branch extends along the second direction, and the first direction intersects the second direction.

9. The array substrate of claim 7, wherein, The pixel circuit also includes a first power signal line extending along a second direction, the orthographic projection of the first power signal line on the substrate covering the seventh orthographic projection.

10. A display panel, characterized by, Includes the array substrate as described in any one of claims 1 to 9.

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