Power device cell structure, method of manufacturing the same, and power device

Abstract

This invention discloses a power device cell structure, its fabrication method, and a power device. The power device cell structure includes: a collector, a collector region of a first conductivity type, a drift region of a second conductivity type, a well region of a first conductivity type, an injection region of a first conductivity type, a first insulating layer, and an emitter, stacked sequentially. A contact hole is formed in the first insulating layer, through which the emitter contacts the injection region. A gate trench structure is also included, with its top contacting the first insulating layer, extending through the injection region and the well region, and its bottom extending to the drift region. At least one side of the gate trench structure has an emitter region of a second conductivity type, extending from the top to the bottom of the gate trench structure. The power device cell structure of this invention can shorten the channel length, reduce channel resistance, and lower the forward voltage drop.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a power device cell structure, its fabrication method, and a power device. Background Technology

[0002] IGBT (Insulated Gate Bipolar Transistor) is a bipolar, fully controllable semiconductor power device with advantages such as low driving power consumption, simple driving circuit and low saturation voltage, and is therefore widely used in high voltage and high current fields.

[0003] However, in the current IGBT cell structure, the emitter region is formed by surface ion implantation, which results in a relatively long channel length and a large channel resistance, affecting the reduction of forward conduction voltage drop. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the first objective of the present invention is to provide a power device cell structure that can shorten the channel length, reduce the channel resistance, and lower the forward voltage drop.

[0005] The second objective of this invention is to provide a power device.

[0006] The third objective of this invention is to provide a method for fabricating the cell structure of a power device.

[0007] To achieve the above objectives, the power device cell structure proposed in the first aspect of the present invention includes: a collector, a collector region of a first conductivity type, a drift region of a second conductivity type, a well region of a first conductivity type, an injection region of a first conductivity type, a first insulating layer, and an emitter, which are stacked sequentially. A contact hole is formed in the first insulating layer, and the emitter contacts the injection region through the contact hole. A gate trench structure is also included, with the top of the gate trench structure contacting the first insulating layer and penetrating through the injection region and the well region. The bottom of the gate trench structure extends to the drift region. At least one side of the gate trench structure has an emitter region of a second conductivity type, which extends from the top of the gate trench structure to the bottom of the gate trench structure.

[0008] According to the power device cell structure proposed in this embodiment, a novel emitter region fabrication method is employed. A second conductivity type emitter region is formed on at least one side of the gate trench structure, i.e., ions are implanted along the sidewall of the gate trench structure to form the emitter region. The emitter region extends from the top to the bottom of the gate trench structure and is elongated along the sidewall, which shortens the channel length, forming a short channel. This reduces the channel resistance, lowers the forward voltage drop, and reduces device losses. Furthermore, forming a single-sided emitter region on one side of the gate trench structure reduces the channel density, thereby reducing the short-circuit current of the power device and improving its short-circuit capability.

[0009] In some embodiments of the present invention, there are multiple grid slot structures, which are arranged at intervals along a direction parallel to the drift region, and each grid slot structure has a transmission region with equal or unequal extension lengths on both sides.

[0010] In some embodiments of the present invention, there are multiple grid slot structures, which are arranged at intervals along a direction parallel to the drift region, and the emission region is provided on one side of each grid slot structure.

[0011] In some embodiments of the present invention, the extension length of the emitter region gradually shortens from the edge of the power element cell structure to the center of the power element cell structure, wherein the extension length is the length by which the emitter region extends from the top of the gate slot structure to the bottom of the gate slot structure.

[0012] In some embodiments of the present invention, the extension lengths of the emission regions corresponding to two adjacent grid slot structures are not the same.

[0013] In some embodiments of the present invention, the emission region includes a first emission region having a first extension length and a second emission region having a second extension length, wherein the first emission region and the second emission region are alternately arranged, and the first extension length is greater than the second extension length.

[0014] In some embodiments of the present invention, the gate trench structure includes: a gate trench that penetrates the injection region and the well region and extends to the drift region; a gate that is disposed in the gate trench; and a gate oxide layer that is between the inner surface of the gate trench and the gate.

[0015] In some embodiments of the present invention, the power device cell structure further includes a buffer layer disposed between the collector region and the drift region.

[0016] To achieve the above objectives, the power device proposed in the second aspect of the present invention includes at least one power device cell structure as described in any of the above claims.

[0017] According to the power device proposed in the embodiments of the present invention, at least one power device cell structure as described in any of the above embodiments is employed. By providing emitter regions of a second conductivity type on one or both sides of the gate trench structure and distributing them elongated along the sidewall of the gate trench, the channel length can be shortened to form a short channel, thereby reducing the resistance of the channel region, lowering the forward voltage drop, and reducing the power device losses. When a single-sided emitter region is formed on one side of the gate trench structure, the density of the channel region can also be reduced, thereby reducing the short-circuit current of the power device and improving the short-circuit capability of the power device. Furthermore, by arranging multiple gate trench structures according to a certain pattern based on the extension length of the emitter region, the turn-off speed of different regions of the power device can be balanced and the threshold voltage of different cell structures can be adjusted, thereby protecting the power device and the chip.

[0018] To achieve the above objectives, a method for fabricating a power device cell structure according to a third aspect embodiment of the present invention includes: providing a substrate and fabricating a drift region of a second conductivity type on the substrate; performing first conductivity type doping on the drift region to form a well region; etching the well region and the drift region to form a gate trench of a gate trench structure; implanting ions of the second conductivity type at a desired tilt angle along the sidewall of the gate trench near at least one side of the gate trench near the channel region to form an emitter region extending from the top to the bottom of the gate trench structure; forming a gate oxide layer on the inner surface of the gate trench and filling the gate trench with gate material to form the gate trench structure.

[0019] According to the method for fabricating the cell structure of a power device proposed in embodiments of the present invention, by implanting ions of a second conductivity type at a desired tilt angle along the sidewall of the gate trench near the channel region on at least one side, channel regions of different lengths can be formed. This allows for control of the short-circuit current in the corresponding region of the power device. Furthermore, by precisely controlling the length of the channel region to form a short channel, the resistance of the channel region can be reduced, thereby lowering the forward voltage drop. In addition, implanting ions of the second conductivity type on one side of the gate trench to form a unilateral emitter region reduces the density of the channel region, thereby reducing the short-circuit current of the power device and improving its short-circuit capability.

[0020] In some embodiments of the present invention, implanting ions of a second conductivity type along the sidewall of the gate trench at a desired tilt angle on at least one side of the gate trench near the channel region includes: implanting ions of the second conductivity type on both sides of the gate trench at the desired tilt angle using a tilted ion implantation process, wherein the desired tilt angle is the angle formed by the ion implantation direction and the direction of the sidewall of the gate trench, satisfying α = arctan(H / L), where α is the desired tilt angle, H is the extension length of the emitter region, and L is the width of the gate trench.

[0021] In some embodiments of the present invention, the tilted ion implantation process is used to implant ions of a second conductivity type on both sides of the gate trench at the desired tilt angle, including: implanting ions of the second conductivity type on one side of the gate trench at a first desired tilt angle using the tilted ion implantation process, and implanting ions of the second conductivity type on the other side of the gate trench at a second desired tilt angle using the tilted ion implantation process, wherein the first desired tilt angle is equal to the second desired tilt angle.

[0022] In some embodiments of the present invention, the tilted ion implantation process is used to implant ions of a second conductivity type on both sides of the gate trench at the desired tilt angle, including: implanting ions of the second conductivity type on one side of the gate trench at a first desired tilt angle using the tilted ion implantation process, and implanting ions of the second conductivity type on the other side of the gate trench at a second desired tilt angle using the tilted ion implantation process, wherein the first desired tilt angle and the second desired tilt angle are not equal.

[0023] In some embodiments of the present invention, implanting ions of a second conductivity type along the sidewall of the gate trench at a desired tilt angle on at least one side of the gate trench near the channel region includes: implanting ions of the second conductivity type on one side of the gate trench at the desired tilt angle using a tilted ion implantation process, wherein the desired tilt angle is the angle formed by the ion implantation direction and the direction of the sidewall of the gate trench, satisfying α = arctan(H / L), where α is the desired tilt angle, H is the extension length of the emitter region, and L is the width of the gate trench.

[0024] According to the method for fabricating the cell structure of the power device proposed in the embodiments of the present invention, when ions of a second conductivity type are implanted on one side of the gate trench to form a single-sided emitter region, the density of the channel region can be reduced, thereby reducing the short-circuit current of the power device and improving the short-circuit capability of the power device.

[0025] In some embodiments of the present invention, the fabrication method further includes: controlling the required tilt angle for ion implantation to gradually decrease from the edge of the power device cell structure to the center of the power device cell structure.

[0026] In some embodiments of the present invention, the preparation method further includes: alternately injecting ions of the second conductivity type along the sidewall of the gate trench at a third desired tilt angle and a fourth desired tilt angle, so that emission regions of different extension lengths are alternately arranged, wherein the third desired tilt angle is greater than the fourth desired tilt angle.

[0027] In some embodiments of the present invention, the preparation method further includes: selectively implanting ions of a first conductivity type into the well region to form an implantation region; depositing a first insulating layer and etching the portion of the first insulating layer that does not cover the gate trench structure and the emitter region to form a contact hole; depositing metal to form an emitter, the emitter contacting the implantation region through the contact hole; and forming at least a collector region and a collector electrode doped with a first conductivity type on the back side of the drift region in sequence.

[0028] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0029] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0030] Figure 1 This is a schematic diagram of the cell structure of a power device according to an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the cell structure of a power device according to another embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of the cell structure of a power device according to yet another embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of the cell structure of a power device according to yet another embodiment of the present invention;

[0034] Figure 5 This is a schematic diagram of the cell structure of a power device according to yet another embodiment of the present invention;

[0035] Figure 6 A block diagram of a power device according to an embodiment of the present invention;

[0036] Figure 7 This is a flowchart of a method for fabricating a power device cell structure according to an embodiment of the present invention;

[0037] Figure 8 This is a schematic diagram illustrating the fabrication of a power device cell structure according to an embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of the fabrication of a power device cell structure according to another embodiment of the present invention;

[0039] Figure 10 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention;

[0040] Figure 11 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention;

[0041] Figure 12 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention;

[0042] Figure 13 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention;

[0043] Figure 14 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention;

[0044] Figure 15 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention;

[0045] Figure 16 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention.

[0046] Figure label:

[0047] Power devices 1000;

[0048] Power device cell structure 100;

[0049] Emitter 1, First insulating layer 2, Contact hole 3, Well region 4, Gate trench structure N, Gate 5, Injection region 6, Emitter region 7, Gate oxide layer 8, Gate trench 9, Drift region 10, Buffer layer 11, Collector region 12, Collector electrode 13. Detailed Implementation

[0050] To provide a more detailed understanding of the features and technical content of the embodiments of the present invention, the implementation of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of the present invention. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0051] The following is for reference. Figure 1 - Figure 5 The power device cell structure 100 according to an embodiment of the present invention is described.

[0052] In some embodiments of the present invention, such as Figure 1The diagram shown is a schematic diagram of a power device cell structure according to an embodiment of the present invention. The power device cell structure 100 includes a collector 13, a collector region 12 of a first conductivity type, a drift region 10 of a second conductivity type, a well region 4 of a first conductivity type, an injection region 6 of a first conductivity type, a first insulating layer 2, an emitter 1, and a gate trench structure N stacked sequentially.

[0053] The first conductivity type can be P-type conductivity, and the second conductivity type can be N-type conductivity. Alternatively, the first conductivity type can be N-type conductivity, and the second conductivity type can be P-type conductivity.

[0054] In some embodiments, the emitter 1 is a front metal layer and the collector 13 is a back metal layer. The metal components can be deposited on the front or back of the power device cell structure 100 by means of vapor deposition or sputtering to form the emitter 1 or the collector 13. The metal components in the emitter 1 may include AlSi or AlSiCu, and the metal components in the collector 13 may include AlTiNiAg, AlTiNNiAg, or AlTiNiAu.

[0055] The well region 4 or the first conductivity type doped collector region 12 can be formed by implanting boron ions or other ions. For example, ions can be implanted, driven, or diffused to form the well region 4 or the collector region 12. Specifically, the dopant of both the well region 4 and the collector region 12 is boron (B), and both are heavily doped, for example, the doping concentration can be 10. 14 -10 16 cm -3 Furthermore, the impurity concentration follows a linear or Gaussian distribution.

[0056] Furthermore, ions of a first conductivity type are implanted onto the front side of the well region 4 using processes such as selective implantation, diffusion, or drive-in to form the implantation region 6. The implantation region 6 is heavily doped, with a doping concentration of 10⁻⁶. 16 -10 18 cm -3 The dopant in implantation region 6 is boron (B), with a Gaussian-like doping concentration. Implantation region 6 forms an ohmic contact with emitter 1, thereby improving the contact performance of power device 1000 and reducing contact resistance.

[0057] In other embodiments, the dopant of drift region 10 may be phosphorus (P) or arsenic (As), and the doping is light, with a doping concentration of 2 × 10⁻⁶ for drift region 10. 13 ㎝ -3 -4×10 14 ㎝ -3 Its light doping concentration has a linear or Gaussian distribution.

[0058] A contact hole 3 is formed in the first insulating layer 2, through which the emitter 1 contacts the injection region 6. The top of the gate trench structure N is located in the first insulating layer 2, and the gate trench structure N penetrates the injection region 6 and the well region 4, while the bottom of the gate trench structure N extends to the drift region 10.

[0059] Specifically, the first insulating layer 2 covers the gate trench structure N on the upper surface of the first conductivity type epitaxial layer. The first insulating layer 2 can prevent external impurities from entering the gate trench structure N, thus not affecting the threshold voltage. On the other hand, the first insulating layer 2 can also isolate the emitter 1, thereby preventing short circuits from affecting electrical characteristics. The isolation layer material selected for the first insulating layer 2 includes silicon oxide such as silicon dioxide, PSG, USG, BPSG, or combinations of the above materials.

[0060] In some embodiments, the gate trench structure N includes a gate trench 9, a gate electrode 5, and a gate oxide layer 8. The gate trench 9 penetrates the implantation region 6 and the well region 4 and extends to the drift region 10. Specifically, the shape of the gate trench 9 can be a rectangular trench, a trapezoidal trench, a U-shaped trench, or an irregularly shaped trench, etc. In embodiments of the present invention, [the shape is described in the original text]. Figure 1 Taking the U-shaped gate trench 9 as an example, the gate trench 9 can be formed by using photoresist to shield silicon etching and by etching silicon with a specific silicon etching solution or by dry etching of silicon. The depth of the gate trench 9 can be set to 2.5um-5.5um.

[0061] Furthermore, a gate 5 is disposed in a gate trench 9, wherein the gate 5 comprises silicon oxide, and the gate trench 9 can be filled with silicon oxide to form the gate 5. The gate 5 is heavily doped, with a doping concentration of 10⁻⁶. 21 cm -3 A gate oxide layer 8 is disposed between the inner surface of the gate trench 9 and the gate 5, that is, the gate 5 is disposed inside the gate oxide layer 8. It can be understood that the gate oxide layer 8 is an oxide layer inside the gate trench 9, which can be formed inside the gate trench 9 by oxidation or deposition methods, and the filled gate 5 is adapted to the shape of the gate trench 9.

[0062] In other embodiments, at least one side of the gate trench structure N is formed with an emission region 7 of a second conductivity type, the emission region 7 extending from the top of the gate trench structure N to the bottom of the gate trench structure N.

[0063] Specifically, a tilted ion implantation process can be used to implant ions of the second conductivity type along the sidewall of the gate trench 9 at a desired tilt angle on one or both sides near the channel region, thereby forming the emitter region 7. The tilted ion implantation angle can be represented by α, which is the angle formed by the implantation direction and the direction of the sidewall of the gate trench 9. Taking the width of the gate trench 9 as L and the height of the emitter region 7 as H as an example, the tilted ion implantation angle α = arctan(H / L), where the height H of the emitter region 7 is determined by the width of the protective layer defined by photolithography. Furthermore, the emitter region 7 is heavily doped with a doping concentration of 10⁻⁶. 16 -10 18 cm -3 The doping impurities in emitter region 7 can be phosphorus (P) or arsenic (As), and the doping concentration in emitter region 7 is linearly distributed or Gaussian-like distributed.

[0064] According to the power device cell structure 10 proposed in the embodiments of the present invention, based on the structure of collector 13, collector region 12, drift region 10, well region 4, implantation region 6, first insulation 2, emitter 1, and gate trench structure N, a novel method for fabricating emitter region 7 is adopted. A second conductivity type emitter region 7 is formed on at least one side of the gate trench structure N, i.e., ions are implanted along the sidewall of the gate trench structure N to form the emitter region 7. The emitter region 7 extends from the top to the bottom of the gate trench structure N. The emitter region 7 is elongated along the sidewall of the gate trench 9, which can shorten the channel length and form a short channel, thereby reducing the resistance of the channel region, lowering the forward voltage drop, and reducing device losses. Furthermore, when a single-sided emitter region 7 is formed on one side of the gate trench structure N, the density of the channel region can be reduced, thereby reducing the short-circuit current of the power device 1000 and improving the short-circuit capability of the power device 1000.

[0065] In some embodiments of the present invention, such as Figure 2 The diagram shown is a schematic diagram of a power device cell structure according to another embodiment of the present invention, wherein the power device cell structure 100 further includes a buffer layer 11, which is disposed between the collector region 12 and the drift region 10.

[0066] Specifically, H ions or other ions can be implanted between the collector region 12 and the drift region 10 by means of implantation, driving, or diffusion to form a buffer layer 11 below the drift region 10. The dopant of the buffer layer 11 can be phosphorus (P) or other ions, and the doping is light, with a doping concentration of 2 × 10⁻⁶. 14 ㎝ -3 —5×10 15 ㎝ -3 The doping concentration of buffer layer 11 is linearly distributed or Gaussian-like.

[0067] In some embodiments of the present invention, such as Figure 2As shown, there are multiple gate trench structures N, which are arranged at intervals along a direction parallel to the drift region 10. The distance between each gate trench structure N and its adjacent gate trench structure N can be set to 1µm-10µm. Each gate trench structure N has emission regions 7 on both sides with equal or unequal extension lengths. The extension length is the length by which the emission region 7 extends from the top to the bottom of the gate trench structure N. The extension length of the emission region 7 can be set as needed. For example, the extension length of the emission region 7 can be formed by defining a protective layer through photolithography, and a short channel can be formed by precisely controlling the extension length of the emission region 7.

[0068] In some embodiments of the present invention, such as Figure 3 The diagram shown is a schematic diagram of the cell structure of a power device according to another embodiment of the present invention, wherein there are multiple gate slot structures N, and the multiple gate slot structures N are arranged at intervals along a direction parallel to the drift region 10, and a transmitting region 7 is provided on one side of each gate slot structure N.

[0069] Specifically, by employing an angled ion implantation process, an emitter region 7 can be formed on one side of the gate trench 9 through unilateral implantation. Since N+ is implanted only on one side of the gate trench structure N to form a unilateral channel, the channel density can be greatly reduced under the same power device cell structure 100 area. This can reduce the short-circuit current of the power device 1000, improve the short-circuit current withstand capability of the power device 1000, and enhance the impact resistance of the power device 1000.

[0070] In some embodiments of the present invention, the extension length of the emitter region 7 gradually shortens from the edge of the power device cell structure 100 to the center of the power device cell structure 100, wherein the extension length is the length by which the emitter region 7 extends from the top of the gate slot structure N to the bottom of the gate slot structure N. Figure 4 The diagram shown is a schematic diagram of the cell structure of a power device according to another embodiment of the present invention.

[0071] Among them, with Figure 4In the power device cell structure 100 shown, each gate slot structure N has emitter regions 7 with equal extension lengths on both sides. Taking the example that the extension length of the emitter regions 7 on both sides of each gate slot structure N gradually decreases from the edge to the center of the power device cell structure 100, the extension length of the emitter regions 7 is the channel length. Specifically, the channel length is longer near the edge of the power device cell structure 100 and gradually decreases towards the center. By gradually shortening the channel length from the edge to the center of the power device cell structure 100, the turn-off speed of the power device 1000 at the edge and center can be balanced, and the short-circuit current of the central cell of the power device cell structure 100 can be reduced, giving it a stronger current-carrying capacity during turn-off. Ultimately, this increases the turn-off capability of the power device 1000 and extends its service life.

[0072] In other embodiments of the present invention, the extension lengths of the emission regions 7 corresponding to two adjacent gate slot structures N are not equal.

[0073] Specifically, the launch area 7 includes a first launch area with a first extension length and a second launch area with a second extension length, the first launch area and the second launch area are alternately arranged, wherein the first extension length is greater than the second extension length.

[0074] Among them, such as Figure 5 The diagram shown is a schematic representation of the cell structure of a power device according to another embodiment of the present invention. Figure 5 The first emission region shown includes emission regions 7 with a longer extension length disposed on both sides of a grid slot structure N, and the second emission region includes emission regions 7 with a shorter extension length disposed on both sides of a grid slot structure N. It can be understood that the first emission region and the second emission region are arranged alternately, that is, the corresponding multiple grid slot structures N can be arranged in a manner with alternating channel lengths.

[0075] Furthermore, when multiple grid slot structures N are arranged according to different extension lengths of the launch region 7, it is not limited to... Figure 5The alternating long and short arrangement exemplified in the example can also include a first emitter region comprising emitter regions 7 with longer extensions on both sides of two gate slot structures N, and a second emitter region comprising emitter regions 7 with shorter extensions on both sides of one gate slot structure N. Alternatively, the first emitter region can comprise emitter regions 7 with longer extensions on both sides of three gate slot structures N, and the second emitter region can comprise emitter regions 7 with shorter extensions on both sides of two gate slot structures N. In other words, multiple gate slot structures N can be arranged in any manner, such as two long and one short, or three long and two short, and the first and second emitter regions can be distributed at the edge or center of the power device cell structure 100, or distributed throughout the entire power device cell structure 100.

[0076] According to the power device cell structure 100 of the present invention, the emitter region 7 is arranged in alternating long and short configurations according to the different extension lengths of the emitter region 7. This allows the threshold voltages of different power device cell structures 100 to vary, thereby ensuring that the power device 1000 is always turned on and off at a certain gradient, thus protecting the power device 1000 and the chip.

[0077] In some embodiments of the present invention, such as Figure 6 The diagram shown is a block diagram of a power device according to an embodiment of the present invention, wherein the power device 1000 includes at least one power device cell structure 100 as described in any of the above.

[0078] In this embodiment, the power device 1000 includes one or more power device cell structures 100 as described above. The emitter region 7 in the power device cell structure 100 is positioned on one or both sides of the gate slot structure N, extending from the top to the bottom of the gate slot structure N. This allows for adaptive adjustment of the channel density in the power device cell structure 100, thereby reducing the short-circuit current of the power device 1000, increasing its short-circuit current withstand capability, and enhancing its impact resistance. The extension length of the emitter region 7 gradually shortens from the edge to the center of the power device cell structure 100, balancing the turn-off speed between the edge and center of the power device 1000, reducing the short-circuit current in the center of the power device cell structure 100, and providing a stronger current withstand capability during turn-off. Ultimately, this increases the turn-off capability of the power device 1000 and extends its service life. Furthermore, by setting the emitter region 7 to include a first emitter region and a second emitter region with different extension lengths, and by alternating the first emitter region and the second emitter region, the threshold voltages of different power device cell structures 100 can be differentiated into high and low levels, thereby ensuring that the power device 1000 is always turned on and off at a certain gradient, which can protect the power device 1000 and the chip.

[0079] According to the embodiments of the present invention, the power device 1000 employs at least one power device cell structure 100 as described in any of the above embodiments. By providing emitter regions 7 of a second conductivity type on one or both sides of the gate trench structure N and distributing them elongated along the sidewall of the gate trench 9, the channel length can be shortened to form a short channel, thereby reducing the resistance of the channel region, lowering the forward voltage drop, and reducing the losses of the power device 1000. When a single-sided emitter region 7 is formed on one side of the gate trench structure N, the density of the channel region can also be reduced, thereby reducing the short-circuit current of the power device 1000 and improving the short-circuit capability of the power device 1000. Furthermore, by arranging multiple gate trench structures N in a certain pattern according to the extension length of the emitter region 7, the turn-off speed of different regions of the power device 1000 can be balanced and the threshold voltage of different power device cell structures 100 can be adjusted, thereby protecting the power device 1000 and the chip.

[0080] In other embodiments of the present invention, a method for fabricating the cell structure of a power device is also proposed, which can be referred to in conjunction with Figure 7- Figure 16 The method for fabricating the power device cell structure according to embodiments of the present invention is described, such as... Figure 7 The diagram shows a flowchart of a method for fabricating a power device cell structure according to an embodiment of the present invention, wherein the method for fabricating the power device cell structure includes steps S1-S7, as detailed below.

[0081] S1 provides a substrate and prepares a drift region of a second conductivity type on the substrate.

[0082] Specifically, such as Figure 8 The diagram shown is a schematic diagram of the fabrication of a power device cell structure according to an embodiment of the present invention. The substrate of the second conductivity type can be selected as an N-monocrystalline silicon substrate. The substrate of the second conductivity type is cleaned and dried to serve as the drift region 10.

[0083] S2, doping of the first conductivity type is performed on the drift region to form a well region.

[0084] Among them, such as Figure 8 As shown, ions of the first conductivity type can be implanted onto the front side of the power device cell structure 100, i.e., the drift region 10, through selective implantation, diffusion, or driving processes to form a trap region 4.

[0085] S3, etching is performed on the well region and drift region to form the gate trench structure.

[0086] In an embodiment, such as Figure 9 The diagram shown is a schematic diagram of the fabrication of a power device cell structure according to another embodiment of the present invention, wherein a protective oxide layer is deposited on a substrate of a second conductivity type, and the area etched by the gate trench structure N is defined by photolithography to form a gate trench 9, the gate trench structure N penetrates the well region 4, and the bottom of the gate trench structure N extends to the drift region 10.

[0087] S4, ions of a second conductivity type are injected at a desired tilt angle along the sidewall of the gate trench near the channel region on at least one side of the gate trench to form an emission region extending from the top of the gate trench structure to the bottom of the gate trench structure.

[0088] Specifically, it can be combined with Figure 10 Step S4 will be described below. Figure 10 This is a schematic diagram of the cell structure for fabricating a power device according to another embodiment of the present invention. In this embodiment, a tilted ion implantation process can be used to implant ions of a second conductivity type and / or a first conductivity type along the sidewall of the gate trench 9 near the channel region at a desired tilt angle. The tilted ion implantation process allows the formed emitter region 7 to be elongated along the sidewall of the gate trench 9, shortening the channel length and forming a short channel, thereby reducing the resistance of the channel region. The tilt angle required for ion implantation, as well as the ion implantation dose and energy, can be adjusted according to the width of the gate trench 9 and the extension length of the emitter region 7.

[0089] In some embodiments, a tilted ion implantation process can be used to implant ions of a second conductivity type at a desired tilt angle on both sides of the gate trench 9. The desired tilt angle is the angle formed by the ion implantation direction and the direction of the gate trench sidewall, satisfying α = arctan(H / L), where α is the desired tilt angle, H is the extension length of the emitter region, and L is the width of the gate trench. This results in a structure as follows: Figure 2 The distribution of the emission region 7 shown in the diagram allows for the injection of ions onto both sides of the gate trench 9 at the required tilt angle. This enables the emission region 7 to be elongated along the sidewalls of the gate trench 9, which can shorten the channel length and form a short channel, thereby reducing the resistance of the channel region.

[0090] When performing ion implantation on both sides of the gate trench 9, the conductivity types of the implanted ions on both sides can be set to be the same or different, and the required tilt angles for ion implantation on both sides can be set to be equal or unequal. For example, a tilted ion implantation process can be used to implant ions of the second conductivity type on one side of the gate trench at a first required tilt angle α1, and a tilted ion implantation process can be used to implant ions of the second conductivity type on the other side of the gate trench at a second required tilt angle α2, wherein the first required tilt angle α1 and the second required tilt angle α2 are equal. Alternatively, a tilted ion implantation process can be used to implant ions of the second conductivity type on one side of the gate trench at a first required tilt angle α1, and a tilted ion implantation process can be used to implant ions of the second conductivity type on the other side of the gate trench at a second required tilt angle α2, wherein the first required tilt angle α1 and the second required tilt angle α2 are unequal.

[0091] In other embodiments, a tilted ion implantation process can be used to implant ions of a second conductivity type on one side of the gate trench 9 at the desired tilt angle. The desired tilt angle is the angle formed by the ion implantation direction and the direction of the gate trench sidewall, satisfying α = arctan(H / L), where α is the desired tilt angle, H is the extension length of the emitter region, and L is the width of the gate trench. This results in a structure as follows: Figure 3 The distribution of emitter region 7 shown is such that emitter region 7, formed by unilateral ion implantation on one side of gate trench 9, can control the density of the channel region, reduce the short-circuit current of power device 1000, and improve the short-circuit capability of power device 1000.

[0092] In other embodiments, the required tilt angle for ion implantation can be gradually reduced from the edge to the center of the power device cell structure 100. This forms a structure as follows: Figure 4The distribution of the emitter region 7 shown in the figure is such that the extension length of the emitter region 7 gradually shortens from the edge of the power device cell structure 100 to the center of the power device cell structure 100. This can balance the turn-off speed of the power device 1000 at the edge and the center, and reduce the short-circuit current in the center of the power device cell structure 100, so that it has a strong current-carrying capacity when turned off, and ultimately increase the turn-off capability of the power device 1000 and extend the service life of the power device 1000.

[0093] Ions of the second conductivity type can also be injected alternately along the sidewall of the gate trench 9 at a third desired tilt angle α3 and a fourth desired tilt angle α4, so that emission regions 7 with different extension lengths are alternately arranged, wherein the third desired tilt angle α3 is greater than the fourth desired tilt angle α4. For example Figure 5 The distribution of the emitter region 7 shown in the figure can be alternating between emitter regions 7 with different extension lengths, so that the threshold voltage of different power device cell structures 100 can be high or low, thereby ensuring that the power device 1000 is always turned on and off with a certain gradient, thus protecting the power device 1000 and the chip.

[0094] Furthermore, when ions are injected along the sidewall of the gate trench 9 near the channel region at the desired tilt angle, the high temperature allows impurities in the emitter region 7 to diffuse, achieving a suitable concentration, depth, and width. After ion activation, the emitter region 7 can be elongated along the sidewall of the gate trench 9. By precisely controlling the extension length of the emitter region 7, a short channel is formed, allowing electrons to diffuse downwards rapidly through the short channel, thereby reducing the resistance of the channel region and ultimately lowering the saturation voltage drop and on-state voltage drop of the power device 1000. Additionally, in step S5, a gate oxide layer is formed on the inner surface of the gate trench, and gate material is filled into the gate trench to form a gate trench structure.

[0095] Specifically, such as Figure 11 The diagram shown is a schematic representation of the cell structure for fabricating a power device according to another embodiment of the present invention, wherein a gate oxide layer is grown or deposited on the inner wall surface of the gate trench 9 to serve as the gate oxide layer 8. The gate material may include silicon oxide, for example, polysilicon deposition and polysilicon etching are performed within the gate oxide layer 8, or polysilicon is filled within the gate trench 9 using methods such as CMP to form the gate 5.

[0096] In some embodiments of the present invention, such as Figure 7 As shown, the method for fabricating the cell structure of the power device also specifically includes steps S6 and S7.

[0097] S6, selectively implant ions of a first conductivity type into the well region to form an implantation region, deposit a first insulating layer and etch the portion of the first insulating layer that is not covered by the gate trench structure and the emitter region to form a contact hole, deposit metal to form an emitter, and the emitter contacts the implantation region through the contact hole.

[0098] Among them, can be combined Figures 12-14 Step S6 of this embodiment is described. Figure 12 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention; Figure 13 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention; Figure 14 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention.

[0099] Specifically, such as Figure 12 As shown, a mask can be used, and ions of the first conductivity type can be implanted on the front side of the trap region 4 through processes such as selective implantation, diffusion, or drive-in to form the implantation region 6. For example... Figure 13 As shown, a first insulating layer 2 is deposited on top of the gate trench structure N, and the first insulating layer 2 is subjected to high-temperature reflow to isolate the gate trench structure N. The first insulating layer 2 can also be selectively etched; for example, the portion of the first insulating layer 2 not covering the gate trench structure N and the emitter region 7 is etched to form contact holes 3. Further, as... Figure 14 As shown, metal is deposited on the front side of the first insulating layer 2 and the contact hole 3 to form a front metal electrode, namely the emitter 1. The emitter 1 is isolated by the first insulating layer 2 and does not contact the gate trench structure N. The emitter 1 contacts the emitter region 7 and also contacts the injection region 6 through the contact hole 3. Furthermore, a passivation layer (not shown in the figure) can also be deposited during the front metal deposition to protect the power device 1000.

[0100] S7, at least a collector region and a collector electrode of the first conductivity type are sequentially formed on the back side of the drift region.

[0101] Among them, can be combined Figure 15 , Figure 16 and Figure 2 Step S6 of this embodiment is described. Figure 15 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention; Figure 16 This is a schematic diagram of the cell structure for fabricating a power device according to yet another embodiment of the present invention.

[0102] Specifically, such as Figure 15 As shown, the substrate of the second conductivity type is thinned using chemical or physical methods, and boron ions or other ions are implanted on the back side of the drift region 10, and the implanted ions are activated to form a collector region 12 on the back side of the drift region 10. For example, as Figure 16As shown, a buffer layer 11 can also be formed below the drift region 10 by implanting H ions or other ions between the current collector region 12 and the drift region 10. Finally, a current collector 13 can be formed on the back side of the current collector region 12 by means of evaporation or sputtering to serve as a back metal electrode, thus forming a complete power device cell structure 100 as shown in Figure 2.

[0103] According to the method for fabricating the cell structure of the power device proposed in the embodiments of the present invention, by injecting ions of a second conductivity type along the sidewall of the gate trench 9 at a desired tilt angle on at least one side near the channel region, channel regions of different lengths can be formed. This allows for control of the short-circuit current in the corresponding region of the power device 1000. Furthermore, by precisely controlling the length of the channel region to form a short channel, the resistance of the channel region can be reduced, thereby lowering the forward voltage drop. In addition, by injecting ions of a second conductivity type on one side of the gate trench 9 to form a single-sided emitter region 7, the density of the channel region can be reduced, thereby reducing the short-circuit current of the power device 1000 and improving its short-circuit capability.

[0104] Other configurations and operations of the power device cell structure 100 and the power device 1000 according to embodiments of the present invention are known to those skilled in the art and will not be described in detail here.

[0105] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0106] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A power device cell structure, characterized in that, include: The following components are stacked in sequence: a collector, a collector region of a first conductivity type, a drift region of a second conductivity type, a well region of a first conductivity type, an injection region of a first conductivity type, a first insulating layer, and an emitter. A contact hole is formed in the first insulating layer, and the emitter contacts the injection region through the contact hole. A gate trench structure, wherein the top of the gate trench structure contacts the first insulating layer, the gate trench structure penetrates the injection region and the well region, and the bottom of the gate trench structure extends to the drift region; At least one side of the gate trench structure is formed with an emission region of a second conductivity type, and the emission region extends from the top of the gate trench structure to the bottom of the gate trench structure. The gate slot structure is a plurality of such structures, which are arranged at intervals along a direction parallel to the drift region. The extension length of the emitter region gradually shortens from the edge of the power device cell structure to the center of the power device cell structure. The extension length is the length by which the emitter region extends from the top of the gate slot structure to the bottom of the gate slot structure.

2. The power device cell structure according to claim 1, characterized in that, Each of the grid slot structures has a transmission area with equal or unequal extension lengths on both sides.

3. The power device cell structure according to claim 1, characterized in that, The emission area is provided on one side of each of the grid slot structures.

4. The power device cell structure according to claim 1, characterized in that, The extension lengths of the emission regions corresponding to two adjacent grid slot structures are not the same.

5. The power device cell structure according to claim 1, characterized in that, The grid slot structure includes: A gate groove that penetrates the injection region and the well region and extends into the drift region; A gate, the gate being disposed in the gate trench; A gate oxide layer is disposed between the inner surface of the gate trench and the gate.

6. The power device cell structure according to claim 1, characterized in that, It also includes a buffer layer disposed between the collector region and the drift region.

7. A power device, characterized in that, It includes at least one power device cell structure as described in any one of claims 1-5.

8. A method for fabricating a cell structure of a power device, characterized in that, include: A substrate is provided, and a drift region of a second conductivity type is formed on the substrate; Doping of the first conductivity type is performed on the drift region to form a well region; Etching is performed on the well region and the drift region to form gate trenches of the gate trench structure; Ions of a second conductivity type are injected along the sidewall of the gate trench at a desired tilt angle on at least one side of the gate trench near the channel region to form an emission region extending from the top to the bottom of the gate trench structure, wherein the desired tilt angle used for ion implantation is gradually reduced from the edge of the power device cell structure to the center of the power device cell structure. A gate oxide layer is formed on the inner surface of the gate trench, and gate material is filled into the gate trench to form the gate trench structure.

9. The method for fabricating the power device cell structure according to claim 8, characterized in that, Implanting ions of a second conductivity type along the sidewall of the gate trench at a desired tilt angle on at least one side of the trench near the channel region, including: A tilted ion implantation process is used to implant ions of a second conductivity type into both sides of the gate trench at the desired tilt angle. The desired tilt angle is the angle formed by the ion implantation direction and the direction of the gate trench sidewall, satisfying α=arctan(H / L), where α is the desired tilt angle, H is the extension length of the emission region, and L is the width of the gate trench.

10. The method for fabricating the power device cell structure according to claim 9, characterized in that, The process involves implanting ions of a second conductivity type onto both sides of the gate trench at the desired tilt angle using a tilted ion implantation process, including: The tilted ion implantation process is used to implant ions of a second conductivity type on one side of the gate trench at a first desired tilt angle, and the tilted ion implantation process is used to implant ions of a second conductivity type on the other side of the gate trench at a second desired tilt angle, wherein the first desired tilt angle and the second desired tilt angle are equal.

11. The method for fabricating the power device cell structure according to claim 9, characterized in that, The process involves implanting ions of a second conductivity type onto both sides of the gate trench at the desired tilt angle using a tilted ion implantation process, including: The tilted ion implantation process is used to implant ions of a second conductivity type on one side of the gate trench at a first desired tilt angle, and the tilted ion implantation process is used to implant ions of a second conductivity type on the other side of the gate trench at a second desired tilt angle, wherein the first desired tilt angle and the second desired tilt angle are not equal.

12. The method for fabricating the power device cell structure according to claim 8, characterized in that, Implanting ions of a second conductivity type along the sidewall of the gate trench at a desired tilt angle on at least one side of the trench near the channel region, including: A tilted ion implantation process is used to implant ions of a second conductivity type into one side of the gate trench at the desired tilt angle. The desired tilt angle is the angle formed by the ion implantation direction and the direction of the gate trench sidewall, satisfying α=arctan(H / L), where α is the desired tilt angle, H is the extension length of the emitter region, and L is the width of the gate trench.

13. The method for fabricating the power device cell structure according to claim 8, characterized in that, The preparation method further includes: Ions of a first conductivity type are selectively implanted into the well region to form an implantation region. A first insulating layer is deposited, and the portion of the first insulating layer that does not cover the gate trench structure and the emitter region is etched to form a contact hole. Metal is deposited to form an emitter, which contacts the implantation region through the contact hole. At least a collector region and a collector electrode of a first conductivity type are formed sequentially on the back side of the drift region.

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