Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are disclosed. The semiconductor structure includes a gallium nitride (GaN) layer, a gallium aluminum nitride (AlGaN) layer on the GaN layer, a polarity promoting layer on the AlGaN layer and directly contacting the AlGaN layer, and a gate spacer layer on the polarity promoting layer.

Description

Technical Field

[0001] This invention relates to an insulating structure for a high electron mobility transistor and a method for fabricating the same, comprising a polarity promoting layer that can enhance the polarity of an aluminum gallium nitride (AlGaN) layer. Background Technology

[0002] III-V semiconductor compounds, due to their semiconductor properties, can be used to form many types of integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). In HEMTs, two semiconductor materials with different band gaps are combined to form a heterojunction, providing a channel for charge carriers. In recent years, gallium nitride (GaN) series materials have become suitable for high-power and high-frequency products due to their wide band gap and high saturation velocity. GaN series HEMTs generate a two-dimensional electron gas (2DEG) through the piezoelectric effect of the material itself. Compared to traditional transistors, HEMTs have higher electron velocity and density, thus increasing switching speed.

[0003] High electron mobility transistors based on gallium nitride (GaN) materials possess numerous advantages in electronic, mechanical, and chemical properties, such as wide bandgap, high breakdown voltage, high electron mobility, large elastic modulus, high piezoelectricity, high piezoresistive coefficients, and chemical passivation. These advantages enable GaN-based materials to be used in the fabrication of components for applications such as high-brightness light-emitting diodes, power switching devices, regulators, battery protectors, panel display drivers, and communication components. Summary of the Invention

[0004] The present invention provides a semiconductor structure comprising a gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer on the gallium nitride layer, a polar promoting layer on the aluminum gallium nitride layer and in direct contact with the aluminum gallium nitride layer, and a gate pad layer on the polar promoting layer.

[0005] The present invention provides a method for fabricating a semiconductor structure, comprising forming a gallium nitride (GaN) layer, forming an aluminum gallium nitride (AlGaN) layer on the gallium nitride layer, forming a polarity promoting layer on the aluminum gallium nitride layer and in direct contact with the aluminum gallium nitride layer, and forming a gate pad layer on the polarity promoting layer.

[0006] This invention utilizes a polarity-enhancing layer on an aluminum gallium nitride (AlGaN) layer, wherein the polarity-enhancing layer is p-type doped silicon. This enhances the polarity of the AlGaN layer, thereby increasing the polarity of the 2DEG layer and further improving transistor performance. Furthermore, a portion of the polarity-enhancing layer transforms into a polarity-modifying layer during fabrication, reducing surface roughness and preventing ion diffusion. Attached Figure Description

[0007] Figures 1 to 6 This is a schematic diagram illustrating a method for fabricating an insulating structure for a high electron mobility transistor according to a first preferred embodiment of the present invention. Wherein:

[0008] Figure 2 yes Figure 1 A diagram illustrating the subsequent steps;

[0009] Figure 3 yes Figure 2 A diagram illustrating the subsequent steps;

[0010] Figure 4 yes Figure 3 A diagram illustrating the subsequent steps;

[0011] Figure 5 yes Figure 4 A diagram illustrating the subsequent steps; and

[0012] Figure 6 yes Figure 5 A diagram illustrating the subsequent steps.

[0013] Explanation of main component symbols

[0014] 10: Base

[0015] 12: Gallium nitride layer

[0016] 14: AlGaN layer

[0017] 16: Polarity Promotion Layer

[0018] 17: Polar Modified Layer

[0019] 18: Dielectric layer

[0020] 20: Gate pad layer

[0021] 22: Gate electrode

[0022] 24: Source / Drain Electrodes

[0023] 26: Enhanced two-dimensional electron gas (2DEG) layer

[0024] TK1: Thickness

[0025] TK2: Thickness

[0026] G1: Groove

[0027] P1: Pre-processing steps Detailed Implementation

[0028] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.

[0029] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art as referring to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0030] Please refer to Figures 1 to 6 , Figures 1 to 6 This is a schematic diagram illustrating a method for fabricating an insulating structure for a high electron mobility transistor according to a first preferred embodiment of the present invention. Figure 2 yes Figure 1 A diagram illustrating the subsequent steps; Figure 3 yes Figure 2 A diagram illustrating the subsequent steps; Figure 4 yes Figure 3 A diagram illustrating the subsequent steps; Figure 5 yes Figure 4 A diagram illustrating the subsequent steps; and Figure 6 yes Figure 5 A diagram illustrating the subsequent steps. (See diagram below.) Figure 1 As shown, a substrate 10 is first provided, such as a substrate made of silicon, silicon carbide, or aluminum oxide (or sapphire), wherein the substrate 10 may be a single-layer substrate, a multilayer substrate, a gradient substrate, or a combination thereof. According to other embodiments of the present invention, the substrate 10 may further comprise a silicon-on-insulator (SOI) substrate.

[0031] A gallium nitride layer 12 is then formed on the surface of the substrate 10. In one embodiment, the gallium nitride layer 12 can be formed on the substrate 10 using molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), or a combination thereof. Furthermore, in some embodiments, a buffer layer (not shown) can be additionally formed between the substrate 10 and the gallium nitride layer 12. The buffer layer can help the gallium nitride layer 12 form on the substrate 10. The buffer layer material is, for example, aluminum nitride (AlN), but is not limited to this.

[0032] like Figure 2 As shown, an aluminum gallium nitride (AGaN) layer 14 is then formed on the surface of the gallium nitride (GaN) layer 12. Preferably, the AGaN layer 14 comprises an epitaxial layer formed by an epitaxial growth process. Similar to the method described above for forming the GaN layer 12, the AGaN layer 14 can be formed on the GaN layer 12 using molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), or a combination thereof.

[0033] It is worth noting that after forming the aluminum gallium nitride (AGaN) layer 14 on the surface of the gallium nitride (GaN) layer 12, due to the difference in band gap between the GaN and AGaN layers, a heterojunction is formed with a higher number of interfaces between them. The band bending at the heterojunction creates a quantum well deep within the conduction band, confining electrons generated by the piezoelectric effect within the quantum well. Therefore, a channel region or a two-dimensional electron gas (2DEG) layer is formed at the interface between the GaN and AGaN layers, thereby enabling current conduction.

[0034] Please refer to the following: Figure 2, a polarity promotion layer is formed on the aluminum gallium nitride layer 14, and a dielectric layer 18 is further formed on the polarity promotion layer 16. Herein, the material of the polarity promotion layer 16 in this embodiment is a p-type doped silicon layer, which is doped with ions such as boron, aluminum, gallium, indium, thallium, for example, but is not limited thereto. The material of the dielectric layer 18 is, for example, an insulating material such as silicon oxide or silicon nitride. This embodiment is characterized in that the polarity promotion layer 16 is disposed on the aluminum gallium nitride layer 14. Since the polarity promotion layer 16 is a p-type doped silicon layer, it can attract negative charges in the underlying aluminum gallium nitride layer 14 (attract the negative charges in the aluminum gallium nitride layer 14 upward), and at the same time make the positive charges in the aluminum gallium nitride layer 14 more concentrated at the lower portion. As a result, the polarity of the 2DEG layer is increased, thereby improving the quality and performance of the high electron mobility transistor.

[0035] Then as Figure 3 shown, an etching step is performed, for example, to remove a part of the dielectric layer 18 and the polarity promotion layer 16, thereby forming a groove G1 in the dielectric layer 18 and the polarity promotion layer 16. The position of the groove G1 is approximately the position where a gate pad is预定 to be formed in a subsequent step. It is worth noting that the etching step does not completely remove the polarity promotion layer 16, that is, a part of the polarity promotion layer 16 remains on the bottom surface of the groove G1, but the thickness of the polarity promotion layer 16 under the groove is thinner than that of the polarity promotion layer 16 in other regions. In other words, defining the thickness of the polarity promotion layer 16 under the groove G1 as TK1, and the thickness of the polarity promotion layer 16 in other regions not under the groove G1 as TK2, 0<TK1<TK2. In addition, TK2 is preferably less than 30 angstroms, but is not limited thereto.

[0036] Subsequently, the 2DEG layer needs to be truncated at the position where the gate structure is预定 to be formed, so that the transistor is in a normally off state, and the 2DEG layer is only connected when a voltage is provided to the gate, so as to achieve the switching function of the transistor. To achieve the above object, as Figure 4As shown, a gate pad layer is formed within the recess G1 to cut off the 2DEG layer (the gate pad layer is, for example, P-type doped gallium nitride, which will be described later). Before forming the gate pad layer, some pretreatment steps P1 may be performed on the interior of the recess G1, such as annealing, plasma treatment, doping, wet cleaning, etc., but not limited to these. These pretreatment steps P1 may cause material transformation of the polar promoting layer 16 exposed under the recess G1, making its material different from other polar promoting layers 16. Here, after the pretreatment step P2, the polar promoting layer 16 at the bottom of the recess G1 will be completely transformed, while the polar promoting layer 16 exposed on the sidewall of the recess G1 will be partially transformed. The portion of the polar promoting layer 16 below the recess G1 is defined as the polar modification layer 17, wherein the polar modification layer 17 may contain, but is not limited to, elements such as carbon, oxygen, nitrogen, and fluorine, compared to the polar promoting layer 16.

[0037] Then as Figure 5 As shown, a gate pad layer 20 is formed above the polarity modification layer 17 of the recess G1, wherein the material of the gate pad layer 20 is, for example, p-type doped gallium nitride. The purpose of forming the gate pad layer 20 is to cut off a portion of the 2DEG layer directly below, so that the overall high electron mobility transistor is in a normally off state. The method of forming the gate pad layer 20 may include first forming a gallium nitride layer in the recess G1, and then doping the gallium nitride layer, followed by removing excess gallium nitride layer, for example, through a patterning step. It is worth noting that in this embodiment, the width of the gate pad layer 20 is greater than the width of the recess G1, so a portion of the gate pad layer 20 covers the dielectric layer 18, but the present invention is not limited thereto.

[0038] It is worth noting that the polar modification layer 17 formed here also has other advantages, including a smoother surface, which reduces the surface roughness of the material layer and improves the quality of the subsequently formed gate pad layer (e.g., P-type doped gallium nitride). Furthermore, since the gate pad layer 20 is doped with P-type ions (e.g., magnesium ions), these P-type dopant ions can sometimes diffuse to other areas; the polar modification layer 17 can prevent ion diffusion, thereby improving device quality.

[0039] Finally, as Figure 6As shown, a gate electrode 22 is formed on the gate pad layer 20, and source / drain electrodes 24 are formed in the dielectric layer 18 and the polarity enhancement layer 16 on both sides of the gate electrode 22, respectively. It is worth noting that a polarity enhancement layer 16 with a partial full thickness is included between the gate electrode 22 and the source / drain electrodes 24. The polarity of the aluminum gallium nitride layer 14 directly below the polarity enhancement layer 16 with a partial full thickness is enhanced, thereby improving the conductivity of the underlying 2DEG layer. The position of the enhanced two-dimensional electron gas (2DEG) layer 26 is defined here. The enhanced 2DEG layer 26 in this embodiment has better conductivity than the 2DEG layer formed simply at the interface of the gallium nitride layer 12 and the aluminum gallium nitride layer 14 (that is, without the polarity enhancement layer 16), thus improving the response speed of the transistor. In addition, a portion of the polarity promotion layer 16 is also left below the source / drain electrode 24. The thickness of the polarity promotion layer 16 below the source / drain electrode 24 is greater than the thickness of the polarity modification layer 17 below the groove G1.

[0040] Based on the above description and figures, the present invention provides a semiconductor structure comprising a gallium nitride (GaN) layer 12, an aluminum gallium nitride (AlGaN) layer 14 located on the gallium nitride layer 12, a polarization promoting layer 16 located on the aluminum gallium nitride layer 14 and in direct contact with the aluminum gallium nitride layer 14, and a gate pad layer 20 located on the polarization promoting layer 16.

[0041] In some embodiments of the present invention, the polarity promoting layer 16 is made of p-type doped silicon.

[0042] In some embodiments of the invention, the minimum thickness of the polarity promoting layer 16 is less than 30 angstroms.

[0043] In some embodiments of the present invention, a groove G1 is located within the polarity promoting layer 16, and a portion of the gate pad layer 20 is located within the groove G1.

[0044] In some embodiments of the present invention, the polarity promoting layer 16 is located at a thickness TK1 directly below the groove G1, which is less than the thickness TK2 of the polarity promoting layer 16 located next to the groove G2.

[0045] In some embodiments of the present invention, a polarity modification layer 17 is further included in the groove G1 and between the gate pad layer 20 and the polarity promotion layer 16.

[0046] In some embodiments of the present invention, the polar modification layer 17 comprises silicon and contains a higher carbon concentration than the polar promotion layer.

[0047] In some embodiments of the present invention, the gate pad layer 20 comprises p-type doped gallium nitride.

[0048] In some embodiments of the present invention, a dielectric layer 18 is further included on the polarity promoting layer 16, and a portion of the gate pad layer 20 covers the dielectric layer 18.

[0049] In some embodiments of the present invention, the polarity promoting layer comprises dopant ions selected from boron, aluminum, gallium, indium, and thallium.

[0050] The present invention also provides a method for fabricating a semiconductor structure, comprising forming a gallium nitride (GaN) layer 12, forming an aluminum gallium nitride (AlGaN) layer 14 on the gallium nitride layer 12, forming a polarity promoting layer 16 on the aluminum gallium nitride layer 14 and in direct contact with the aluminum gallium nitride layer 14, and forming a gate pad layer 20 on the polarity promoting layer 16.

[0051] In some embodiments of the present invention, an etching step is further included to form a groove G1 within the polarity promoting layer 16, and the gate pad layer 20 is partially located in the groove G1.

[0052] In some embodiments of the present invention, after the groove G1 is formed, the surface of the polar promoting layer 16 partially exposed by the groove G1 is converted into a polar modified layer 17 within the groove G1.

[0053] In summary, this invention, by setting a polarity promoting layer on an aluminum gallium nitride (AlGaN) layer, wherein the polarity promoting layer is p-type doped silicon, can enhance the polarity of the aluminum gallium nitride layer, thereby increasing the polarity of the 2DEG layer and further improving the transistor performance. Furthermore, a portion of the polarity promoting layer becomes a polarity modification layer during fabrication, which has the effects of reducing surface roughness and preventing ion diffusion.

[0054] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure comprising: Gallium nitride (GaN) layer; An aluminum gallium nitride (AlGaN) layer is located on the gallium nitride layer; A polarity promoting layer is located on and in direct contact with the gallium aluminum nitride layer, wherein the polarity promoting layer is made of p-type doped silicon. A gate pad layer is located on the polarity promoting layer; as well as The groove is located within the polarity promoting layer, and the gate pad layer is partially located within the groove.

2. The semiconductor structure of claim 1, wherein the minimum thickness of the polarity promoting layer is less than 30 angstroms.

3. The semiconductor structure of claim 1, wherein the thickness of the polar promoting layer located directly below the groove is less than the thickness of the polar promoting layer located beside the groove.

4. The semiconductor structure of claim 1, further comprising a polarity modifier layer located within the groove and between the gate pad layer and the polarity enhancement layer.

5. The semiconductor structure of claim 4, wherein the polar modification layer comprises silicon and has a higher carbon concentration than the polar promotion layer.

6. The semiconductor structure of claim 1, wherein the gate pad layer comprises p-type doped gallium nitride.

7. The semiconductor structure of claim 1, further comprising a dielectric layer located on the polarity promoting layer, and a portion of the gate pad layer covering the dielectric layer.

8. The semiconductor structure of claim 1, wherein the polar promoting layer comprises dopant ions selected from boron, aluminum, gallium, indium, and thallium.

9. A method for fabricating a semiconductor structure, comprising: Forming a gallium nitride (GaN) layer; An aluminum gallium nitride (AlGaN) layer is formed on top of the gallium nitride layer; A polar promoting layer is formed on the gallium aluminum nitride layer and in direct contact with the gallium aluminum nitride layer, wherein the material of the polar promoting layer includes p-type doped silicon; A gate pad layer is formed on the polarity promoting layer; as well as An etching step is performed to form a groove within the polarity promoting layer, and the gate pad layer is partially located within the groove.

10. The fabrication method of claim 9, wherein the minimum thickness of the polarity promoting layer is less than 30 angstroms.

11. The manufacturing method of claim 9, wherein the thickness of the polarity promoting layer located directly below the groove is less than the thickness of the polarity promoting layer located beside the groove.

12. The manufacturing method of claim 9, wherein after the groove is formed, a portion of the surface of the polar promoting layer exposed by the groove is converted into a polar modified layer within the groove.

13. The fabrication method of claim 12, wherein the polar modification layer comprises silicon and has a higher carbon concentration than the polar promotion layer.

14. The fabrication method of claim 9, wherein the gate pad layer comprises p-type doped gallium nitride.

15. The fabrication method of claim 9, further comprising forming a dielectric layer on the polarity promoting layer, and a portion of the gate pad layer covering the dielectric layer.

16. The fabrication method of claim 9, wherein the polarity promoting layer comprises dopant ions selected from boron, aluminum, gallium, indium, and thallium.

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