transistor element

Abstract

This invention provides a transistor device comprising a gallium nitride (GaN) transistor, a bias element, and a voltage-controlled current (VDC) element. The GaN transistor has a drain, a source, and a gate. The drain is coupled to a first terminal of the transistor device. The bias element is connected in series between the source of the GaN transistor and a second terminal of the transistor device. The VDC element is coupled to a control terminal of the transistor device. The VDC element provides a bias current to the bias element based on the voltage at the control terminal of the transistor device, thereby controlling the GaN transistor to be turned on or off.

Description

Technical Field

[0001] This invention relates to an element, and more particularly to a transistor element. Background Technology

[0002] Gallium nitride (GaN) transistors are widely used due to their advantages in physical characteristics such as device size, on-resistance, and operating frequency. However, GaN transistors also have a low threshold voltage, which often results in significant power consumption in circuits.

[0003] Existing technologies have proposed several enhancement-mode (e-mode) gallium nitride (GaN) transistors in an attempt to reduce their power consumption. However, these enhancement-mode GaN transistors often require special processes to modify the GaN transistor structure, or they need to cascode GaN transistors together. This often leads to higher manufacturing costs, or the current of the GaN transistor is limited by the cascaded transistors, thus affecting the circuit performance of the GaN transistor. Summary of the Invention

[0004] This invention relates to a transistor device that can improve the manufacturing cost of gallium nitride transistors without affecting the circuit performance of the gallium nitride transistors themselves.

[0005] According to an embodiment of the present invention, a transistor device includes a gallium nitride (GaN) transistor, a bias element, and a voltage-controlled current (VDC) element. The GaN transistor has a drain, a source, and a gate. The drain is coupled to a first terminal of the transistor device. The bias element is connected in series between the source of the GaN transistor and a second terminal of the transistor device. The VDC element is coupled to a control terminal of the transistor device. The VDC element provides a bias current to the bias element based on the voltage at the control terminal of the transistor device to control the GaN transistor to be turned on or off.

[0006] Based on the above, the transistor element of the present invention controls the operation of the gallium nitride transistor to be turned on and / or turned off through the coupling relationship between the gallium nitride transistor, the bias element and the voltage-controlled current element.

[0007] The transistor element of this invention achieves the effect of an enhancement-mode gallium nitride (GaN) transistor through the coupling relationship of a gallium nitride transistor, a bias element, and a voltage-controlled current element. It effectively adjusts the voltage difference between the gate and source of the GaN transistor based on the input voltage level, allowing the GaN transistor to be optimally turned off, thus disconnecting the connection between its drain and source. Furthermore, since the voltage-controlled current element is connected in parallel with the GaN transistor, it does not limit the on-current of the GaN transistor. Therefore, it improves power consumption while retaining the advantages of high current and fast switching inherent in GaN transistors. Attached Figure Description

[0008] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0009] Figure 1 This is a schematic diagram of a transistor element according to Embodiment 1 of the present invention;

[0010] Figure 2A This is a circuit diagram of a transistor element according to Embodiment 1 of the present invention;

[0011] Figure 2B This is a schematic diagram of the structure of a transistor element according to Embodiment 1 of the present invention;

[0012] Figure 3A This is a circuit diagram of a transistor element according to Embodiment 1 of the present invention;

[0013] Figure 3B This is a schematic diagram of the structure of a transistor element according to Embodiment 1 of the present invention;

[0014] Figure 4A This is a circuit diagram of a transistor element according to Embodiment 1 of the present invention;

[0015] Figure 4B This is a schematic diagram of the structure of a transistor element according to Embodiment 1 of the present invention;

[0016] Figure 5A This is a circuit diagram of a transistor element according to Embodiment 1 of the present invention;

[0017] Figure 5B This is a schematic diagram of the structure of a transistor element according to Embodiment 1 of the present invention;

[0018] Figure 6 This is a schematic diagram of a transistor element according to Embodiment 1 of the present invention;

[0019] Figure 7 This is a schematic diagram of a transistor element according to Embodiment 1 of the present invention.

[0020] Explanation of icon numbers

[0021] 1-7: Transistor components;

[0022] 10: Gallium nitride transistor;

[0023] 11, 21, 41: Bias components;

[0024] 12, 22, 32, 62, 72: Voltage-controlled current elements;

[0025] 23~26, 33~37, 43~46, 53~57: Electrical connection structure;

[0026] 27, 38, 47, 58: Isolation structure;

[0027] 100: Base;

[0028] 101: Buffer layer;

[0029] 102: Channel layer;

[0030] 103: Barrier layer;

[0031] 1031: First barrier layer;

[0032] 1032: Second barrier layer;

[0033] 1033: Third barrier layer;

[0034] M1, M2: Bias transistors;

[0035] R1, R2, Rd: Resistors;

[0036] T1: First end;

[0037] T2: Second end;

[0038] TC: Control terminal;

[0039] ZD: Zener diode. Detailed Implementation

[0040] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0041] Figure 1This is a schematic diagram of a transistor element 1 according to an embodiment of the present invention. The transistor element 1 has a first terminal T1, a second terminal T2, and a control terminal TC. The transistor element 1 includes a gallium nitride (GaN) transistor 10, a bias element 11, and a voltage-controlled current element 12. The drain of the GaN transistor 10 is coupled to the first terminal T1 of the transistor element 1, the source of the GaN transistor 10 is coupled to the first terminal of the bias element 11, and the gate of the GaN transistor 10 is coupled to the second terminal T2 of the transistor element 1. The first terminal of the voltage-controlled current element 12 is coupled to the first terminal T1 of the transistor element 1, the second terminal of the voltage-controlled current element 12 is coupled to the second terminal of the GaN transistor 10, and the control terminal of the voltage-controlled current element 12 is coupled to the control terminal TC of the transistor element 1. The second terminal of the bias element 11 is coupled to the second terminal T2 of the transistor element 1. In simple terms, the gallium nitride transistor 10 and the bias element 11 are connected in series between the first terminal T1 and the second terminal T2 of the transistor element 1, while the voltage-controlled current element 12 is connected in parallel with the gallium nitride transistor 10 and is directly coupled to the source of the gallium nitride transistor 10.

[0042] In some embodiments, the gallium nitride transistor 10 exhibits excellent characteristics for high-power operation, such as fast switching, high voltage tolerance, relatively small size, and better heat dissipation. However, on the other hand, because the gallium nitride transistor 10 typically has a low threshold voltage, it is not easy to turn off, resulting in greater power consumption. Therefore, the present invention, through the overall connection structure of the gallium nitride transistor 10, the bias element 11, and the voltage-controlled current element 12 in the transistor element 1, enables the voltage-controlled current element 12 to control the conduction and / or cutoff of the gallium nitride transistor 10 according to the voltage received at the control terminal TC, thereby making the gallium nitride transistor 10 more effectively turned off. The transistor element 1 as a whole can be regarded as a three-terminal transistor, which, while possessing the excellent operating characteristics of the gallium nitride transistor 10, also reduces the power consumption of the transistor element 1.

[0043] In one embodiment, the gallium nitride transistor 10 may be, for example, an n-type gallium nitride transistor 10, having a drain, a source, and a gate. The drain of the gallium nitride transistor 10 is coupled to a first terminal T1 of the transistor element 1, the source of the gallium nitride transistor 10 is coupled to a bias element 11, and the gate of the gallium nitride transistor 10 is coupled to a second terminal T2 of the transistor element 1. For example, the gallium nitride transistor 10 may be, for example, an n-type depletion-mode gallium nitride transistor 10. In this way, the n-type gallium nitride transistor 10 can carry current using electrons as carriers and has high mobility. On the other hand, the process steps required for depletion-mode gallium nitride transistors are relatively simple, which can effectively reduce the process complexity and manufacturing cost of electronic component 1.

[0044] The bias element 11 is coupled between the source of the gallium nitride transistor 10 and the second terminal T2 of the transistor element 1. The gallium nitride transistor 10 and the bias element 11 are connected in series between the first terminal T1 and the second terminal T2 of the transistor element 1. The bias element 11 can change the source voltage of the gallium nitride transistor 10 according to the current it receives.

[0045] The voltage-controlled current element 12 is connected in parallel with the gallium nitride transistor 10. The voltage-controlled current element 12 is a three-terminal element, and the conduction between its first and second terminals is controlled according to the voltage received at its control terminal. The first terminal of the voltage-controlled current element 12 is coupled to the first terminal T1 of the transistor element 1, the second terminal of the voltage-controlled current element 12 is directly coupled to the source of the gallium nitride transistor 10, and the control terminal of the voltage-controlled current element 12 is coupled to the control terminal TC of the transistor element 1.

[0046] Overall, the voltage-controlled current element 12 selectively provides current to the bias element 11 based on the voltage received at the control terminal TC. The bias element 11, based on the received bias current, provides a negative bias between the gate and source of the gallium nitride transistor 10, thereby increasing the source voltage of the gallium nitride transistor 10 and reducing the voltage difference between its gate and source, thus controlling the gallium nitride transistor 10 to be off. Therefore, the transistor element 1 as a whole can control the gallium nitride transistor 10 to be on and / or off through the coordinated operation of the voltage-controlled current element 12 and the bias element 11. On the other hand, since the voltage-controlled current element 12 is not connected in series with the gallium nitride transistor 10, it does not limit the on-current of the gallium nitride transistor 10, effectively preserving the advantages of the gallium nitride transistor 10's high current and fast switching.

[0047] Figure 2A This is a circuit diagram of transistor element 2 according to an embodiment of the present invention. Transistor element 2 includes a gallium nitride transistor 10, a bias element 21, a voltage-controlled current element 22, and a resistor Rd. The gallium nitride transistor 10 can be connected to the first terminal T1 of transistor element 1 via resistor Rd.

[0048] Specifically, the bias element 21 includes a resistor R2. The voltage-controlled current element 22 includes a resistor R1 and a bias transistor M1 connected in series. The bias transistor M1 may be a pMOSFET. The resistor R1 is coupled between the first terminal T1 of the transistor element 2 and the source of the bias transistor M1. The gate of the bias transistor M1 is coupled to the control terminal TC of the transistor element 2, and the drain of the bias transistor M1 is coupled to the source of the gallium nitride transistor 10.

[0049] In some embodiments, the gallium nitride transistor 10 may have a higher operating voltage (e.g., about 600V), while the resistor R1 can step down the voltage received at the first terminal of the transistor element 2 to a voltage suitable for operation of the metal-oxide-semiconductor transistor (e.g., about 30V).

[0050] The resistor Rd can be biased according to the operating requirements of the gallium nitride transistor 10. In some embodiments, the resistor Rd can be implemented, for example, by an external resistor or by the internal impedance of the gallium nitride transistor 10.

[0051] Therefore, when bias transistor M1 receives a low logic level voltage, bias transistor M1 can be turned on, thus providing bias current to resistor R2 of bias element 21. The source voltage of gallium nitride transistor 10 can thus rise, and correspondingly, the voltage difference between the gate and source of gallium nitride transistor 10 is reduced. When the voltage difference between the gate and source of gallium nitride transistor 10 is less than or equal to a threshold voltage (e.g., -11V), gallium nitride transistor 10 can thus be turned off, disconnecting the connection between its drain and source. Therefore, when transistor element 2 receives a low logic level voltage, gallium nitride transistor 10 can be turned off, allowing the overall transistor element 2 to operate as an n-type transistor.

[0052] Figure 2B This is a schematic diagram of the structure of transistor element 2 in Embodiment 1 of the present invention. Figure 2B The diagram illustrates partial cross-sectional structures and electrical connections of transistor element 2 in some embodiments. Please refer to the following sections. Figure 2A , Figure 2B Let's understand the structural description of transistor element 2 in the following section.

[0053] In detail, the structure of transistor element 2 may include a substrate 100, a buffer layer 101, a channel layer 102, a barrier layer 103, electrical connection structures 23-26, and an isolation structure 27. The gallium nitride transistor 10 may be formed by sequentially stacking the substrate 100, buffer layer 101, channel layer 102, and barrier layer 103. The barrier layer 103 further includes a first barrier layer 1031, a second barrier layer 1032, and a third barrier layer 1033. Electrical connection structures 23-26 may be disposed on the barrier layer 103 to provide electrical connections.

[0054] Electrical connection structures 23-26 can be the drain, gate, source, and second terminal T2 of the gallium nitride transistor 10, respectively. The resistor Rd is the internal impedance between the drain and gate of the gallium nitride transistor 10.

[0055] An isolation structure 27 is disposed between electrical connection structures 25 and 26, and its depth extends from the barrier layer 103 to the bottom of the channel layer 102. The isolation structure 27 can be used to isolate the current in the channel layer 102 between electrical connection structures 25 and 26.

[0056] Therefore, according to Figure 2B The schematic diagram shows that the bias transistor M1 can control the source voltage level of the gallium nitride transistor 10 based on whether the voltage received at the control terminal is a high logic level or a low logic level. When transistor element 2 receives a low logic level, the source voltage level of the gallium nitride transistor 10 is increased, thus turning the gallium nitride transistor 10 off.

[0057] In simple terms, in transistor element 2, the bias element 21 receives the bias current provided by the voltage-controlled current element 22, allowing the bias element 21, connected between the gate and source of the gallium nitride transistor 10, to raise the source voltage of the gallium nitride transistor 10. This, in turn, reduces the voltage difference between the gate and source of the gallium nitride transistor 10, effectively controlling the gallium nitride transistor to be off. Furthermore, since the bias element 21 is implemented by a passive element (i.e., a resistor), it does not limit the conduction current of the gallium nitride transistor 10, thus effectively preserving the high current characteristics of the gallium nitride transistor 10.

[0058] Figure 3A This is a schematic diagram of transistor element 3 according to an embodiment of the present invention. Transistor element 3 includes a gallium nitride transistor 10, a bias element 21, a voltage-controlled current element 32, and a resistor Rd. The first terminal of resistor Rd is coupled to the first terminal T1 of transistor element 1, and the second terminal of resistor Rd is coupled to the drain of gallium nitride transistor 10 and the first terminal of voltage-controlled current element 32.

[0059] Specifically, the bias element 21 includes a resistor R2. The voltage-controlled current element 32 includes a bias transistor M1. The bias transistor M1 may be a pMOSFET. The source of the bias transistor M1 is coupled to the drain of the gallium nitride transistor 10, the gate of the bias transistor M1 is coupled to the control terminal TC of the transistor element 3, and the drain of the bias transistor M1 is coupled to the source of the gallium nitride transistor 10.

[0060] In some embodiments, the gallium nitride transistor 10 may have a higher operating voltage (e.g., about 600V), while the resistor Rd can step down the voltage received at the first terminal of the transistor element 3 to a voltage suitable for operation of the metal-oxide-semiconductor transistor (e.g., about 30V).

[0061] The resistor Rd can be biased according to the operating requirements of the gallium nitride transistor 10. In some embodiments, the resistor Rd can be implemented, for example, by an external resistor or by the internal impedance of the gallium nitride transistor 10.

[0062] Therefore, when bias transistor M1 receives a low logic level voltage, bias transistor M1 can be turned on, thus providing bias current to resistor R2 of bias element 21. The source voltage of gallium nitride transistor 10 can thus rise, and correspondingly, the voltage difference between the gate and source of gallium nitride transistor 10 is reduced. When the voltage difference between the gate and source of gallium nitride transistor 10 is less than or equal to a threshold voltage (e.g., -11V), gallium nitride transistor 10 can thus be turned off, disconnecting the connection between its drain and source. Therefore, when transistor element 3 receives a low logic level voltage, gallium nitride transistor 10 can be turned off, allowing the overall transistor element 3 to operate as an n-type transistor.

[0063] Figure 3B This is a schematic diagram of the structure of transistor element 3 in Embodiment 1 of the present invention. Figure 3B The diagram illustrates partial cross-sectional structures and electrical connections of transistor element 3 in some embodiments. Please refer to the following sections for further details. Figure 3A , Figure 3B Let's understand the structural description of transistor element 3 in the following section.

[0064] In detail, the structure of the transistor element 3 may include a substrate 100, a buffer layer 101, a channel layer 102, a barrier layer 103, electrical connection structures 33-37, and an isolation structure 38. The gallium nitride transistor 10 may be formed by sequentially stacking the substrate 100, buffer layer 101, channel layer 102, and barrier layer 103. The barrier layer 103 further includes a first barrier layer 1031, a second barrier layer 1032, and a third barrier layer 1033. The electrical connection structures 33-37 may be disposed on the barrier layer 103 to provide electrical connections.

[0065] Electrical connection structures 33 and 35-37 can be the drain, gate, source, and second terminal T2 of the gallium nitride transistor 10, respectively. Electrical connection structure 34 can obtain an appropriate bias voltage from the channel between the drain and gate of the gallium nitride transistor 10 and provide it to the first terminal of the voltage-controlled current element 32. The resistor Rd is the internal impedance between the drain and gate of the gallium nitride transistor 10.

[0066] An isolation structure 38 is disposed between electrical connection structures 36 and 37, and its depth extends from the barrier layer 103 to the bottom of the channel layer 102. The isolation structure 38 can be used to isolate the current in the channel layer 102 between the electrical connection structures 36 and 37.

[0067] Therefore, according to Figure 3BThe schematic diagram shows that the bias transistor M1 can control the source voltage level of the gallium nitride transistor 10 based on whether the voltage received at the control terminal is a high logic level or a low logic level. When transistor element 3 receives a low logic level, the source voltage level of the gallium nitride transistor 10 is increased, thus turning the gallium nitride transistor 10 off.

[0068] In simple terms, in transistor element 3, the bias element 31 receives the bias current provided by the voltage-controlled current element 32, allowing the bias element 31, connected between the gate and source of the gallium nitride transistor 10, to raise the source voltage of the gallium nitride transistor 10. This, in turn, reduces the voltage difference between the gate and source of the gallium nitride transistor 10, effectively controlling the gallium nitride transistor to be off. Furthermore, since the bias element 31 is implemented by a passive element (i.e., a resistor), it does not limit the conduction current of the gallium nitride transistor 10, thus effectively preserving the high current characteristics of the gallium nitride transistor 10.

[0069] Figure 4A This is a circuit diagram of transistor element 4 according to an embodiment of the present invention. Transistor element 4 includes a gallium nitride transistor 10, a bias element 41, a voltage-controlled current element 22, and a resistor Rd. Resistor Rd is coupled between the first terminal T1 of transistor element 1 and the drain of gallium nitride transistor 10.

[0070] Specifically, the bias element 41 includes a resistor R2 and a Zener diode ZD connected in series between the source of the gallium nitride transistor 10 and the second terminal T2 of the transistor element 4. The anode and cathode of the Zener diode ZD are coupled to the second terminal T2 of the transistor element 4 and the resistor R2, respectively. The voltage-controlled current element 22 includes a resistor R1 and a bias transistor M1 connected in series. The bias transistor M1 can be a pMOSFET. The resistor R1 is coupled between the first terminal T1 of the transistor element 4 and the source of the bias transistor M1. The gate of the bias transistor M1 is coupled to the control terminal TC of the transistor element 4, and the drain of the bias transistor M1 is coupled to the source of the gallium nitride transistor 10.

[0071] In some embodiments, the gallium nitride transistor 10 may have a higher operating voltage (e.g., about 600V), while the resistor R1 can step down the voltage received at the first terminal of the transistor element 4 to a voltage suitable for operation of the metal-oxide-semiconductor transistor (e.g., about 30V).

[0072] The resistor Rd can be biased according to the operating requirements of the gallium nitride transistor 10. In some embodiments, the resistor Rd can be implemented, for example, by an external resistor or by the internal impedance of the gallium nitride transistor 10.

[0073] Therefore, when bias transistor M1 receives a low logic level voltage, bias transistor M1 can be turned on, thus providing bias current to resistor R2 of bias element 41. The source voltage of gallium nitride transistor 10 can thus rise, and correspondingly, the voltage difference between the gate and source of gallium nitride transistor 10 is reduced. When the voltage difference between the gate and source of gallium nitride transistor 10 is less than or equal to a threshold voltage (e.g., -11V), gallium nitride transistor 10 can thus be turned off, disconnecting the connection between its drain and source. Therefore, when transistor element 4 receives a low logic level voltage, gallium nitride transistor 10 can be turned off, allowing the overall transistor element 4 to operate as an n-type transistor.

[0074] In some embodiments, when the Zener diode ZD breaks down, it can provide a stable voltage difference across its terminals, thereby enabling the voltage difference between the gate and source of the gallium nitride transistor 10 to be stably biased at less than or equal to a threshold voltage (e.g., -11V) when the bias transistor M1 is turned on.

[0075] Figure 4B This is a schematic diagram of the structure of transistor element 4 in Embodiment 1 of the present invention. Figure 4B The diagram illustrates partial cross-sectional structures and electrical connections of transistor element 4 in some embodiments. Please refer to the following sections. Figure 4A , Figure 4B Let's understand the structural description of transistor element 4 in the following section.

[0076] In detail, the structure of the transistor element 4 may include a substrate 100, a buffer layer 101, a channel layer 102, a barrier layer 103, electrical connection structures 43-46, and an isolation structure 47. The gallium nitride transistor 10 may be formed by sequentially stacking the substrate 100, buffer layer 101, channel layer 102, and barrier layer 103. The barrier layer 103 further includes a first barrier layer 1031, a second barrier layer 1032, and a third barrier layer 1033. The electrical connection structures 43-46 may be disposed on the barrier layer 103 to provide electrical connections.

[0077] Electrical connection structures 43-46 can be the drain, gate, and source of gallium nitride transistor 10, respectively, and the second terminal T2 of transistor element 4. The resistor Rd is the impedance between electrical connection structure 43 and gallium nitride transistor 10. The bias element 41 is coupled between electrical connection structures 45 and 46.

[0078] An isolation structure 47 is disposed between electrical connection structures 45 and 46, and its depth extends from the barrier layer 103 to the bottom of the channel layer 102. The isolation structure 47 can be used to isolate the current in the channel layer 102 between electrical connection structures 45 and 46.

[0079] Therefore, according to Figure 4B The schematic diagram shows that the bias transistor M1 can control the source voltage level of the gallium nitride transistor 10 based on whether the voltage received at the control terminal is a high logic level or a low logic level. When transistor element 4 receives a low logic level, the source voltage level of the gallium nitride transistor 10 is increased, thus turning the gallium nitride transistor 10 off.

[0080] Figure 5A This is a circuit diagram of transistor element 5 according to an embodiment of the present invention. Transistor element 5 includes a gallium nitride transistor 10, a bias element 41, a voltage-controlled current element 32, and a resistor Rd. Resistor Rd is coupled between the first terminal T1 of transistor element 1 and the drain of gallium nitride transistor 10.

[0081] Specifically, the bias element 41 includes a resistor R2 and a Zener diode ZD connected in series between the source of the gallium nitride transistor 10 and the second terminal T2 of the transistor element 5. The anode and cathode of the Zener diode ZD are coupled to the second terminal T2 of the transistor element 5 and the resistor R2, respectively. The voltage-controlled current element 32 includes a bias transistor M1. The bias transistor M1 can be a pMOSFET. The source of the bias transistor M1 is coupled to the drain of the gallium nitride transistor 10, the gate of the bias transistor M1 is coupled to the control terminal TC of the transistor element 5, and the drain of the bias transistor M1 is coupled to the source of the gallium nitride transistor 10.

[0082] In some embodiments, the gallium nitride transistor 10 may have a higher operating voltage (e.g., about 600V), while the resistor Rd can step down the voltage received at the first terminal of the transistor element 5 to a voltage suitable for operation of the metal-oxide-semiconductor transistor (e.g., about 30V).

[0083] The resistor Rd can be biased according to the operating requirements of the gallium nitride transistor 10. In some embodiments, the resistor Rd can be implemented, for example, by an external resistor or by the internal impedance of the gallium nitride transistor 10.

[0084] Therefore, when bias transistor M1 receives a low logic level voltage, bias transistor M1 can be turned on, thus providing bias current to resistor R2 of bias element 41. The source voltage of gallium nitride transistor 10 can thus rise, and correspondingly, the voltage difference between the gate and source of gallium nitride transistor 10 is reduced. When the voltage difference between the gate and source of gallium nitride transistor 10 is less than or equal to a threshold voltage (e.g., -11V), gallium nitride transistor 10 can thus be turned off, disconnecting the connection between its drain and source. Therefore, when transistor element 5 receives a low logic level voltage, gallium nitride transistor 10 can be turned off, allowing the overall transistor element 5 to operate as an n-type transistor.

[0085] In some embodiments, when the Zener diode ZD breaks down, it can provide a stable voltage difference across its terminals, thereby enabling the voltage difference between the gate and source of the gallium nitride transistor 10 to be stably biased at less than or equal to a threshold voltage (e.g., -11V) when the bias transistor M1 is turned on.

[0086] Figure 5B This is a schematic diagram of the structure of transistor element 5 in Embodiment 1 of the present invention. Figure 5B The diagram illustrates partial cross-sectional structures and electrical connections of transistor element 5 in some embodiments. Please refer to the following sections. Figure 5A , Figure 5B Let's understand the structural description of transistor element 5 in the following section.

[0087] In detail, the structure of the transistor element 5 may include a substrate 100, a buffer layer 101, a channel layer 102, a barrier layer 103, electrical connection structures 53-57, and an isolation structure 58. The gallium nitride transistor 10 may be formed by sequentially stacking the substrate 100, buffer layer 101, channel layer 102, and barrier layer 103. The barrier layer 103 further includes a first barrier layer 1031, a second barrier layer 1032, and a third barrier layer 1033. The electrical connection structures 53-57 may be disposed on the barrier layer 103 to provide electrical connections.

[0088] Electrical connection structures 53 and 55-57 can be the drain, gate, source, and second terminal T2 of the gallium nitride transistor 10, respectively. Electrical connection structure 54 can obtain an appropriate bias voltage from the channel between the drain and gate of the gallium nitride transistor 10 and provide it to the first terminal of the voltage-controlled current element 32. The resistor Rd is the impedance between electrical connection structure 53 and electrical connection structure 54 (i.e., the drain of the gallium nitride transistor 10). The bias element 41 is coupled between electrical connection structures 56 and 57.

[0089] An isolation structure 58 is disposed between electrical connection structures 56 and 57, and its depth extends from the barrier layer 103 to the bottom of the channel layer 102. The isolation structure 58 can be used to isolate the current in the channel layer 102 between electrical connection structures 56 and 57.

[0090] Therefore, according to Figure 5B The schematic diagram shows that the bias transistor M1 can control the source voltage level of the gallium nitride transistor 10 based on whether the voltage received at the control terminal is a high logic level or a low logic level. When transistor element 5 receives a low logic level, the source voltage level of the gallium nitride transistor 10 is increased, thus turning the gallium nitride transistor 10 off.

[0091] Furthermore, those skilled in the art can, of course, modify the above embodiments according to different design requirements. For example, the above embodiments describe an implementation of using a first conduction type (i.e., n-type) gallium nitride transistor in a transistor element, but various embodiments of the present invention are not limited thereto; a second conduction type (i.e., p-type) gallium nitride transistor can also be used in the implementation of a transistor element. In another example, the above embodiments describe an implementation in which a p-type metal-oxide-semiconductor transistor is included in the voltage-controlled current element, causing the transistor element to operate as an n-type transistor, but various embodiments of the present invention are not limited thereto; the voltage-controlled current element in the transistor element can also include an n-type metal-oxide-semiconductor transistor.

[0092] Figure 6 This is a schematic diagram of transistor element 6 according to Embodiment 1 of the present invention. Figure 6 The transistor element 6 in the middle is similar to Figure 4A In transistor element 4, the only difference is that the voltage-controlled current element 22 in transistor element 4 is replaced by a voltage-controlled current element 62 in transistor element 6. Therefore, the same elements are represented by the same symbols, and the relevant descriptions can be found in the relevant paragraphs above, which will not be repeated here.

[0093] The voltage-controlled current element 62 includes a resistor R1 connected in series between the first terminal T1 of the transistor element 6 and the source of the gallium nitride transistor, and a bias transistor M2. The bias transistor M2 is an n-type MOSFET. The resistor R1 is coupled between the first terminal of the transistor element 6 and the drain of the bias transistor M2. The source of the bias transistor M2 is coupled to the source of the gallium nitride transistor, and the gate of the bias transistor M2 is coupled to the control terminal TC of the transistor element 6.

[0094] In this way, when bias transistor M2 receives a high logic level voltage, bias transistor M2 can be turned on, thus providing bias current to resistor R2 of bias element 41 and Zener diode ZD. The source voltage of gallium nitride transistor 10 can thus rise, and correspondingly, the voltage difference between the gate and source of gallium nitride transistor 10 is reduced. When the voltage difference between the gate and source of gallium nitride transistor 10 is less than or equal to a threshold voltage (e.g., -11V), gallium nitride transistor 10 can thus be turned off, disconnecting the connection between its drain and source. Therefore, when transistor element 6 receives a high logic level voltage, gallium nitride transistor 10 can be turned off, allowing the overall transistor element 6 to operate as a p-type transistor.

[0095] Figure 7 This is a schematic diagram of transistor element 7 according to Embodiment 1 of the present invention. Figure 7 The transistor element 6 in the middle is similar to Figure 5AIn transistor element 5, the only difference is that the voltage-controlled current element 32 in transistor element 5 is replaced by a voltage-controlled current element 72 in transistor element 7. Therefore, the same elements are represented by the same symbols, and the relevant descriptions can be found in the relevant paragraphs above, which will not be repeated here.

[0096] The voltage-controlled current element 72 includes a bias transistor M2. The bias transistor M2 is an n-type metal-oxide-semiconductor transistor (n-type MOSFET). The drain of the bias transistor M2 is coupled to the drain of the gallium nitride transistor 10, the source of the bias transistor M2 is coupled to the source of the gallium nitride transistor 10, and the gate of the bias transistor M2 is coupled to the control terminal TC of the transistor element 6.

[0097] In this way, when bias transistor M2 receives a high logic level voltage, bias transistor M2 can be turned on, thus providing bias current to resistor R2 of bias element 41 and Zener diode ZD. The source voltage of gallium nitride transistor 10 can thus rise, and correspondingly, the voltage difference between the gate and source of gallium nitride transistor 10 is reduced. When the voltage difference between the gate and source of gallium nitride transistor 10 is less than or equal to a threshold voltage (e.g., -11V), gallium nitride transistor 10 can thus be turned off, disconnecting the connection between its drain and source. Therefore, when transistor element 7 receives a high logic level voltage, gallium nitride transistor 10 can be turned off, allowing the overall transistor element 7 to operate as a p-type transistor.

[0098] In summary, the transistor element of the present invention achieves the effect of an enhancement-mode gallium nitride transistor through the coupling relationship of a gallium nitride transistor, a bias element, and a voltage-controlled current element. It effectively adjusts the voltage difference between the gate and source of the gallium nitride transistor based on the input voltage level, allowing the gallium nitride transistor to be optimally turned off, thus disconnecting the connection between its drain and source. Furthermore, since the voltage-controlled current element and the gallium nitride transistor 10 are connected in parallel, the voltage-controlled current element does not limit the conduction current of the gallium nitride transistor. Therefore, while improving power consumption, it retains the advantages of high current and fast switching inherent in gallium nitride transistors.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A transistor device having a first terminal, a second terminal, and a control terminal, characterized in that, The transistor element includes: A gallium nitride transistor has a drain, a source, and a gate, wherein the drain of the gallium nitride transistor is coupled to a first terminal of the transistor element; A biasing element is connected in series between the source of the gallium nitride transistor and the second terminal of the transistor element; and A voltage-controlled current element is coupled to the control terminal of the transistor element. The voltage-controlled current element is used to provide a bias current to the bias element according to the voltage of the control terminal of the transistor element. The bias element raises the source voltage of the gallium nitride transistor to control the gallium nitride transistor to be turned on or off. The voltage-controlled current element does not limit the on current of the gallium nitride transistor.

2. The transistor device according to claim 1, characterized in that, The voltage-controlled current element provides the bias current to the bias element to reduce the voltage difference between the gate and source of the gallium nitride transistor, thereby controlling the gallium nitride transistor to be off.

3. The transistor device according to claim 1, characterized in that, The gallium nitride transistor is a depletion-type gallium nitride transistor.

4. The transistor device according to claim 1, characterized in that, When the voltage difference between the gate and source of the gallium nitride transistor is less than or equal to the threshold voltage, the gallium nitride transistor is turned off.

5. The transistor device according to claim 1, characterized in that, The voltage-controlled current element includes a bias transistor having a first terminal, a second terminal, and a control terminal. The first terminal of the bias transistor is coupled to the drain of the gallium nitride transistor, the second terminal of the bias transistor is directly coupled to the source of the gallium nitride transistor, the control terminal of the bias transistor is coupled to the control terminal of the transistor element, and the control terminal of the gallium nitride transistor is coupled to the second terminal of the transistor element.

6. The transistor device according to claim 5, characterized in that, When the bias transistor is a p-type metal-oxide-semiconductor field-effect transistor (MOSFET), and the source, drain, and gate of the p-type MOSFET are respectively the first terminal, the second terminal, and the control terminal of the bias transistor, the transistor element operates as an n-type transistor. When the bias transistor is an n-type metal-oxide-semiconductor field-effect transistor, and the drain, source, and gate of the n-type metal-oxide-semiconductor field-effect transistor are the first terminal, the second terminal, and the control terminal of the bias transistor, respectively, the transistor element operates as a p-type transistor.

7. The transistor device according to claim 5, characterized in that, The gallium nitride transistor includes: substrate; Buffer layer; Channel layer; and Barrier layer, The drain, source, and gate of the gallium nitride transistor are disposed on the barrier layer.

8. The transistor device according to claim 7, characterized in that, include: First electrical connection structure; Second electrical connection structure; A third electrical connection structure is disposed between the first electrical connection structure and the second electrical connection structure; A fourth electrical connection structure is disposed on the other side of the third electrical connection structure, corresponding to the second electrical connection structure. The first electrical connection structure, the second electrical connection structure, the third electrical connection structure, and the fourth electrical connection structure are respectively the drain of the gallium nitride transistor, the source of the gallium nitride transistor, the gate of the gallium nitride transistor, and the second terminal of the transistor element.

9. The transistor element according to claim 8, characterized in that, The voltage-controlled current element further includes a first resistor disposed between the first terminal of the transistor element and the first terminal of the bias transistor. A second resistor is also provided between the first electrical connection structure and the third electrical connection structure, which is the internal resistance between the drain and gate of the gallium nitride transistor. The biasing element further includes a third electrical group.

10. The transistor device according to claim 8, characterized in that, It also includes a fifth electrical connection structure, disposed between the first electrical connection structure and the third electrical connection structure. The first electrical connection structure and the fifth electrical connection structure also have a first resistance, which is the internal resistance between the drain and gate of the gallium nitride transistor. The voltage-controlled current element is coupled to the fifth electrical connection structure. The biasing element further includes a second electrical group.

11. The transistor device according to claim 1, characterized in that, The biasing element further includes a Zener diode having an anode coupled to a second end of the transistor element and a cathode coupled to the source of the gallium nitride transistor.

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