Multi-level trench SiC MOSFET device and its manufacturing method
By employing multi-level trench and superjunction structure design, the reliability and short-circuit capability issues of trench-type SiC MOSFET devices under extreme environments are resolved, achieving a balance between on-resistance and saturation current, and improving the overall performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
- Filing Date
- 2023-01-30
- Publication Date
- 2026-06-05
AI Technical Summary
Trench SiC MOSFET devices suffer from gate dielectric layer reliability issues and insufficient short-circuit capability under extreme environments, and it is difficult to balance the on-resistance and saturation current.
A multi-level trench structure is adopted, including first and second trenches, which are connected to form a longitudinal conductive channel. Combined with a superjunction structure and split gate design, the on-resistance is reduced and the short-circuit performance is enhanced.
It improves the reliability and short-circuit withstand time of the device, while maintaining good forward conduction capability, reducing gate-drain capacitance, and improving dynamic characteristics.
Smart Images
Figure CN116154000B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor device technology, specifically disclosing a multi-level trench SiC MOSFET device and its manufacturing method, belonging to the technical field of basic electrical components. Background Technology
[0002] The development of power electronic systems has placed higher demands on the performance of semiconductor devices in areas such as high temperature, high frequency, radiation resistance, and high voltage. While traditional silicon-based devices have mature fabrication processes, the inherent properties of the material limit their application in extreme operating environments. Compared to silicon, SiC (SiC) offers a wider bandgap, higher electron saturation drift velocity, stronger radiation resistance, higher critical breakdown electric field, and higher thermal conductivity, making it one of the most important semiconductor materials for fabricating high-power devices capable of withstanding extreme environments.
[0003] Conventional planar SiC MOSFET devices exhibit a parasitic junction field-effect transistor structure, increasing the device's on-resistance. In contrast, trench SiC MOSFET devices, by forming channels on the trench sidewalls, improve channel mobility and eliminate the JFET effect, significantly reducing on-resistance, shrinking cell size, and increasing power density. However, trench SiC MOSFET devices face two main challenges in practical fabrication and application: firstly, the gate dielectric layer at the trench corners must withstand a large electric field, affecting device reliability; secondly, the relatively low on-resistance of trench MOSFETs results in a relatively large saturation current, leading to a higher short-circuit current and shorter short-circuit withstand time, thus making their short-circuit capability weaker than that of planar MOSFETs.
[0004] To address the aforementioned issues, the primary solution currently involves adding a high concentration of doped P at the bottom of the trench. + Region, using P + The location of the concentrated electric field in the region is shifted, thereby protecting the gate dielectric layer, while utilizing P + The JFET effect generated by the trench and P-well regions reduces the saturation current of the device and enhances its short-circuit capability. However, this approach increases the on-resistance of the trench MOSFET device, impairing its forward conduction capability.
[0005] In summary, the present invention aims to provide a multi-level trench SiC MOSFET device and its manufacturing method to overcome the defects of existing trench MOSFET devices. Summary of the Invention
[0006] The purpose of this invention is to address the shortcomings of the aforementioned background technology by providing a multi-level trench SiC MOSFET device and its manufacturing method. This invention solves the technical problems of the gate dielectric layer at the trench corner affecting the reliability of trench MOSFET devices and the trade-off between high on-resistance and low saturation current in the performance of trench MOSFET devices. The invention aims to improve the reliability of trench SiC MOSFET devices and enhance their short-circuit performance while ensuring forward conduction capability.
[0007] To achieve the above-mentioned objectives, the present invention employs the following technical solution:
[0008] Multi-level trench SiC MOSFET devices, including,
[0009] Drain electrode;
[0010] The first conductivity type substrate is located above the drain electrode;
[0011] A first conductivity type epitaxial layer is located on a first conductivity type substrate;
[0012] At least two second conductivity type pillar regions are located in the first conductivity type epitaxial layer;
[0013] At least two second trenches, each second trench being located inside a pillar region of a second conductivity type;
[0014] The second conductivity type well region is located in the well region epitaxial layer on the surface of the first conductivity type epitaxial layer;
[0015] At least two first conductivity type source regions, each first conductivity type source region being located in a second conductivity type well region above a second conductivity type pillar region;
[0016] The second conductivity type heavily doped region is located between two adjacent first conductivity type source regions;
[0017] At least two first trenches, each first trench is located in the well region epitaxial layer above a second conductivity type pillar region, and longitudinal channels are formed on both sides of each first trench. Each first trench is connected to the second trench in the second conductivity type pillar region below it to form a multi-level trench structure.
[0018] A gate dielectric layer covers the surface of a multi-level trench structure formed by the first trench and the second trench;
[0019] The gate electrode is located inside the gate dielectric layer and covers the first trench;
[0020] At least two insulating dielectric layers are located above the epitaxial layer of the well region; and,
[0021] The source electrode is located between two adjacent insulating dielectric layers;
[0022] As a further optimization of multi-level trench SiC MOSFET devices, the gate dielectric layer can be made of silicon oxide or high dielectric constant materials such as aluminum oxide.
[0023] As a further optimization of multi-level trench SiC MOSFET devices, the gate electrode can be metal or doped polysilicon.
[0024] As a further optimization scheme for multi-level trench SiC MOSFET devices, the doping concentration of the second conductivity type pillar region is 1e. 16 cm -3 ~2e 18 cm -3 The width of the second conductive type pillar region differs from the width of the second trench by no more than 1µm.
[0025] As a further optimization scheme for multi-level trench SiC MOSFET devices, the doping concentration of the epitaxial layer of the first conductivity type is 1e. 16 cm -3 ~2e 17 cm -3 .
[0026] As a further optimization of the multi-level trench SiC MOSFET device, the depth of the first trench is 0.5~1.5µm and the width is 0.5~1.5µm, and the depth of the first trench is greater than the thickness of the epitaxial layer of the well region.
[0027] As a further optimization of the multi-level trench SiC MOSFET device, the depth of the second trench is 0.3~1.5µm, the width of the second trench is 1.1~4.5µm, and the width of the second trench is greater than the width of the first trench.
[0028] As a further optimization of multi-level trench SiC MOSFET devices, the isolation dielectric layer can be silicon dioxide, nitride, or a composite.
[0029] As a further optimization of multi-level trench SiC MOSFET devices, the material of the drain ohmic contact layer can be Al, Au, or Pt.
[0030] As a further optimization of multi-level trench SiC MOSFET devices, the source ohmic contact layer can be made of Al, Au, or Pt.
[0031] A method for fabricating a multi-level trench SiC MOSFET device includes the following steps:
[0032] S1. An epitaxial layer of the first conductivity type is formed on a substrate of the first conductivity type by epitaxial growth technology;
[0033] S2. An etching mask layer is grown on the first conductivity type epitaxial layer prepared in step 1 by chemical vapor deposition. The etching mask layer is patterned by photolithography. The first conductivity type epitaxial layer is inductively coupled plasma etched using the patterned etching mask layer. The first conductivity type epitaxial layer in the region where the second conductivity type pillar is located is removed by deep trench etching.
[0034] S3. Remove the etching mask layer prepared in step 2, and smooth the surface through epitaxial backfill and CMP process to form a second type of conductive pillar region;
[0035] S4. The SiC MOSFET device prepared in step 3 is epitaxially grown with SiC of the first conductivity type to form a first conductivity type epitaxial layer covering the top of the second conductivity type pillar region. An ion implantation mask layer is grown on the surface of the first conductivity type epitaxial layer covering the top of the second conductivity type pillar region by chemical vapor deposition. The ion implantation mask layer is patterned by photolithography. A large dose of ions is implanted into the first conductivity type epitaxial layer covering the top of the second conductivity type pillar region using the ion implantation mask layer until the first conductivity type doped SiC in the region of the first conductivity type epitaxial layer covering the top of the second conductivity type pillar region is amorphous.
[0036] S5. The SiC MOSFET device prepared in step 4 is epitaxially doped with SiC of the first conductivity type to form a well region epitaxial layer. A second conductivity type well region is formed in the well region epitaxial layer by photolithography and ion implantation. A first conductivity type source region is formed in the second conductivity type well region above each second conductivity type pillar region. A second conductivity type heavily doped region is formed between two adjacent first conductivity type source regions.
[0037] S6. A patterned etching mask layer is formed on the surface of the well region epitaxial layer prepared in step 5. The patterned etching mask layer is used to perform inductively coupled plasma etching on the well region epitaxial layer to form a first trench with longitudinal channels on both sidewalls in the well region epitaxial layer above each second conductivity type pillar region.
[0038] S7. Then, the amorphous SiC in the region where the second trench is formed in the first conductivity type epitaxial layer covering the top of the second conductivity type pillar region is removed by wet etching to form a second trench that connects the first trench.
[0039] S8. Remove the etching mask layer prepared in step 6, and perform passivation and high-temperature annealing on the multi-level trench structure formed by connecting the first trench and the second trench.
[0040] S9. A silicon dioxide layer is deposited on the surface of the multi-level trench structure after passivation and high-temperature annealing in step S8 through thermal oxidation and chemical vapor deposition processes. The silicon dioxide layer is then subjected to high-temperature annealing to form a gate dielectric layer. Polysilicon is grown inside the gate dielectric layer through chemical vapor deposition and polysilicon implantation is performed. Polysilicon etching is then performed to remove the polysilicon outside the first trench and the polysilicon on the surface of the epitaxial layer of the well region to form the gate electrode.
[0041] S10. An isolation dielectric layer is deposited on the surface of the well region epitaxial layer of the SiC MOSFET device prepared in step 9, and a source window is formed by photolithography and etching. A source ohmic contact layer is formed through this source window, a drain ohmic contact layer is formed on the surface of the first conductivity type substrate, a source electrode is formed on the surface of the source ohmic contact layer, and a drain electrode is formed on the surface of the drain ohmic contact layer.
[0042] As a further optimization of the fabrication method for multi-level trench SiC MOSFET devices, the method for forming the second trench is high-dose ion implantation followed by wet etching. The implanted ions can be Al or B ions, and the implantation dose is not less than 5e⁻¹. 14 cm -3 The injected target peak concentration is not less than 2e 20 cm -3 The proportion of HNO3 in the wet etching solution shall not be less than 2%.
[0043] The present invention, by adopting the above technical solution, has the following beneficial effects:
[0044] (1) The multi-level trench SiC MOSFET device proposed in this invention has a first trench for forming a longitudinal conductive channel and a second trench for reducing the saturation current of the trench SiC MOSFET device in each cell. The first trench and the second trench are connected to form a multi-level trench structure. The width of the second trench is significantly larger than that of the first trench, which is beneficial to reducing the saturation current of the device, thereby increasing the short-circuit withstand time of the device and improving the short-circuit characteristics of the device. Compared with introducing an additional P + For trench-type SiC MOSFET devices that reduce saturation current, the JFET effect is avoided. At the same time, the superjunction structure formed by the second conductivity type pillar region and the first conductivity type epitaxial layer protects the gate dielectric and significantly reduces the on-resistance of the device while ensuring that the breakdown characteristics do not degrade. This avoids the second trench affecting the forward conduction characteristics of the device, achieving a better trade-off between reducing the dielectric layer electric field and enhancing the forward conduction capability of the device.
[0045] (2) In the SiC MOSFET device proposed in this invention, the position and depth of the second trench can be designed according to the actual application requirements to reduce the area of the drift region, thereby reducing the gate-drain overlap area of the first trench sidewall, and thus reducing the gate-drain capacitance and improving the dynamic characteristics of the device. Attached Figure Description
[0046] Figure 1 This is a schematic diagram of the cross-section of the trench-type SiC MOSFET device along the A-A' direction in Example 1.
[0047] Figure 2 This is a three-dimensional structural schematic diagram of the trench-type SiC MOSFET device of Example 1.
[0048] Figure 3 This is a schematic diagram of the trench-type SiC MOSFET device in Example 2.
[0049] Figure 4 This is a schematic diagram of the trench-type SiC MOSFET device in Example 3.
[0050] Figure 5 This is a schematic diagram of the trench-type SiC MOSFET device in Example 4.
[0051] Figure 6 This is a schematic diagram of the trench-type SiC MOSFET device in Example 5.
[0052] Figure 7 This is a schematic diagram of the trench-type SiC MOSFET device in Example 6.
[0053] Figure 8 This is a schematic diagram of the trench-type SiC MOSFET device in Example 7.
[0054] Figure 9 This is a schematic diagram of the trench-type SiC MOSFET device in Example 8.
[0055] Figures 10-21 This is a schematic diagram of the structure of the SiC MOSFET device formed by each process step in the fabrication of the trench-type SiC MOSFET device in Example 1.
[0056] The markings in the figure are as follows: 1. Drain electrode; 2. Substrate of the first conductivity type; 3. Epitaxial layer of the first conductivity type; 4. Pillar region of the second conductivity type; 5. Second trench; 6. First trench; 7. Gate dielectric; 8. Well region of the second conductivity type; 9. Heavily doped region of the second conductivity type; 10. Source region of the first conductivity type; 11. Source electrode; 12. Gate electrode; 13. Isolation dielectric layer; 14. Vertical channel. Detailed Implementation
[0057] The present invention will be further described below with reference to embodiments. The embodiments are only used to illustrate the present invention and do not constitute a limitation on the scope of the claims. Other alternative means that can be conceived by those skilled in the art are all within the scope of the claims of the present invention.
[0058] Furthermore, in the description of this invention, it should be noted that the terms "central," "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Example 1
[0059] The three-dimensional structure of a multi-level trench SiC MOSFET device is as follows: Figure 2 As shown, the cross-sectional structure of this multi-level trench SiC MOSFET device along the A-A' direction is as follows: Figure 1As shown, the multi-level trench SiC MOSFET device includes: a drain electrode 1; a first conductivity type substrate 2 located above the drain electrode 1, the first conductivity type substrate 2 being a first conductivity type SiC substrate; a first conductivity type epitaxial layer 3 located on the first conductivity type substrate 2, the first conductivity type epitaxial layer 3 being a first conductivity type doped SiC epitaxial layer; a second conductivity type pillar region 4 located in the first conductivity type epitaxial layer 3, the first conductivity type epitaxial layer 3 having at least two second conductivity type pillar regions 4, the second conductivity type pillar regions 4 being fabricated by implanting second conductivity type doped SiC; a second trench 5 located on top of the second conductivity type pillar regions 4; a second conductivity type well region 8 located in the well region epitaxial layer on the surface of the first conductivity type epitaxial layer 3; and a second conductivity type well region 8 located above each second conductivity type pillar region 4. The system comprises: a first conductivity type source region 10; a second conductivity type heavily doped region 9 located between two adjacent first conductivity type source regions 10; a first trench 6 located in the well region epitaxial layer above each second conductivity type pillar region 4; a gate dielectric layer 7 covering the first trench 6 and the second trench 5; a gate electrode 12 located inside the gate dielectric layer 7, which controls the longitudinal channels on the sidewalls of the first trench after being energized; an isolation dielectric layer 13 located above the well region epitaxial layer, which may be silicon dioxide, nitride, or a composite; a source electrode 11 located between two adjacent isolation dielectric layers 13; the source electrode 11 is located on the surface of the first conductivity type source region 10 on both sides of the second conductivity type heavily doped region 9 and the second conductivity type heavily doped region 9; and the gate electrode 12 may be metal or doped polysilicon. The first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type.
[0060] The fabrication method of the above-mentioned multi-level trench SiC MOSFET device, such as Figures 10-20 As shown, it includes the following 10 steps.
[0061] Step S1, as follows Figure 10 , Figure 11 As shown, a first conductivity type epitaxial layer 3 is formed on a first conductivity type substrate 2 through an epitaxial growth process. The doping concentration of the first conductivity type epitaxial layer 3 is 1e. 16 cm -3 ~2e 17 cm -3 .
[0062] Step S2, as follows Figure 12 As shown, an etching mask layer is grown on the surface of the first conductive epitaxial layer 3 prepared in step S1 by chemical vapor deposition, and then the etching mask layer is patterned by photolithography. The patterned etching mask layer is used to perform inductively coupled plasma etching on the first conductive epitaxial layer 3 to remove the first conductive epitaxial layer 3 in the region where the second conductive pillar region 4 is located.
[0063] Step S3, as follows Figure 13 As shown, the etch mask layer obtained in step S2 is removed, and the surface is smoothed by epitaxial backfilling and CMP processes to form a second conductivity type pillar region 4. The depth-to-width ratio of the second conductivity type pillar region 4 is greater than 2:1; the doping concentration of the second conductivity type pillar region 4 is 1e. 16 cm -3 ~2e 18 cm -3 The distance between the second conductivity type pillar regions 4 in two adjacent cells is not less than 0.5µm.
[0064] Step S4, as follows Figure 14 As shown, the surface of the SiC MOSFET device prepared in step S3 is epitaxially doped with N-type SiC to form a first conductivity type epitaxial layer 3 covering the top of the second conductivity type pillar region 4; as Figure 15 As shown, an ion implantation mask layer is grown on the surface of the first conductivity type epitaxial layer 3 using chemical vapor deposition. The ion implantation mask layer is then patterned using photolithography. A high-dose ion implantation process is used to amorphize the conductive material (SiC) in the region forming the second trench 5 in the first conductivity type epitaxial layer 3, which covers the top of the second conductivity type pillar region 4. The implanted ions can be Al or B ions, and the implantation dose is not less than 5e⁻¹. 14 cm -3 The injected target peak concentration is not less than 2e 20 cm -3 .
[0065] Step S5, as follows Figure 16 As shown, the SiC MOSFET device prepared in step S4 has an epitaxial N-type doped SiC layer on its surface to form a well region epitaxial layer; as Figure 17 As shown, a second conductivity type well region 8 is formed in the well region epitaxial layer through photolithography and ion implantation processes. A first conductivity type source region 10 is formed in the second conductivity type well region 8 above each second conductivity type pillar region 4. A second conductivity type heavily doped region 9 is formed between two adjacent first conductivity type source regions 10.
[0066] Step S6, as follows Figure 18As shown, a patterned etching mask layer is formed on the surface of the well region epitaxial layer prepared in step S5. Inductively coupled plasma etching (ICP-C) is performed on the well region epitaxial layer using the patterned etching mask layer. A first trench 6 with longitudinal channels on both sidewalls is formed in the well region epitaxial layer above each second conductivity type pillar region 4. The etching depth of the first trench can be adjusted as needed. When the etching depth exceeds the well region epitaxial layer, the second conductivity type pillar region 4 is etched to form the bottom of the first trench. The depth of the first trench 6 is 0.5~1.5µm, the width of the first trench 6 is 0.5~1.5µm, and the depth of the first trench 6 is greater than the thickness of the well region epitaxial layer.
[0067] Step S7, as follows Figure 19 As shown, for the SiC MOSFET device prepared in step S6, the amorphous SiC in the region forming the second trench 5 in the first conductivity type epitaxial layer 3 covering the top of the second conductivity type pillar region 4 is removed by wet etching, forming a second trench 5 that communicates with the first trench 6. Each second trench in the second conductivity type pillar region forms a multi-level trench structure with the first trench above that second conductivity type pillar region, and the proportion of HNO3 in the wet etching solution is not less than 2%. The depth of the second trench 5 is 0.3~1.5µm, the width of the second trench 5 is 1.1~4.5µm, the width of the second trench 5 is greater than the width of the first trench 6, and the difference between the width of the second trench 5 and the width of the first trench 6 is not less than 0.2µm; the distance between the top of the second trench 5 and the bottom of the second conductivity type well region 8 is not less than 0.2µm; the distance w1 between the second trenches 5 in two adjacent cells is between 0.5µm and 3µm; the difference between the width of the second trench 5 and the width of the second conductivity type pillar region 4 does not exceed 1µm; the depth of the second trench 5 is 0.2µm~1.5µm.
[0068] Step S8: Remove the etching mask layer of the SiC MOSFET device prepared in step S6, and passivate and anneal the multi-level trench structure formed by connecting the first trench 6 and the second trench 5.
[0069] Step S9, as follows Figure 20 As shown, a silicon dioxide layer is formed on the surface of the multi-level trench structure after passivation and high-temperature annealing in step S8 by thermal oxidation and chemical vapor deposition processes. The silicon dioxide layer formed on the surface of the multi-level trench structure is the gate dielectric layer 7, and the silicon dioxide layer is subjected to high-temperature annealing. Polysilicon is grown inside the gate dielectric layer 7 by chemical vapor deposition process, and polysilicon implantation is performed. Then, polysilicon etching is performed to remove the polysilicon outside the first trench and the polysilicon on the surface of the well region epitaxial layer to form the gate electrode 12.
[0070] Step S10, as follows Figure 21As shown, an isolation dielectric layer 13 is deposited on the surface of the well region epitaxial layer of the SiC MOSFET device prepared in step S9 to form a source window. A source ohmic contact layer is formed through this source window, and a drain ohmic contact layer is formed on the bottom surface of the first conductivity type substrate 2. A source electrode 11 is formed on the surface of the source ohmic contact layer, and a drain electrode 1 is formed on the surface of the drain ohmic contact layer. After the gate electrode 12 is energized, it controls the longitudinal channels 14 on both sides of the first trench. The material of the drain ohmic contact layer can be Al, Au, or Pt. The material of the source ohmic contact layer can be Al, Au, or Pt. Example 2
[0071] A multi-level trench SiC MOSFET device, such as Figure 3 As shown, the device is basically the same as in Example 1, except that the depth of the second trench 5 is much greater than that in Example 1, ranging from 1.5µm to 5µm. Below the second trench 5 is still the second conductivity type pillar region 4, but the difference is that, in order to maintain the charge balance of the superjunction structure, the concentration of the second conductivity type pillar region 4 is much greater than that in Example 1, being 2 to 3 times the doping concentration of the second conductivity type pillar region in Example 1. Increasing the depth of the second trench 5 helps to further reduce the gate-drain capacitance and improve the dynamic characteristics of the device. Example 3
[0072] A multi-level trench SiC MOSFET device, such as Figure 4 As shown, the difference from Embodiment 1 is that the first trench 6 extends close to the bottom of the first conductivity type epitaxial layer 3, the bottom of the second trench 5 contacts the first conductivity type substrate 2, and the second conductivity type pillar region 4 is located above the second trench 5. The contact between the bottom of the second trench 5 and the first conductivity type substrate 2 helps to reduce the electric field strength experienced by the gate dielectric at the bottom of the second trench 5. The second conductivity type pillar region 4, located above the second trench 5, can protect the gate dielectric in the first trench 6. Simultaneously, the second conductivity type pillar region 4 and the second trench 5 can reduce saturation current and improve short-circuit characteristics. Example 4
[0073] A multi-level trench SiC MOSFET device, such as Figure 5 As shown, the difference from Embodiment 1 is that the gate electrode 12 adopts a split gate structure. The split gate structure can reduce the gate-drain overlap area, reduce the gate-drain capacitance, and improve dynamic characteristics. Example 5
[0074] A multi-level trench SiC MOSFET device, such as Figure 6As shown, the difference from Embodiment 1 is that the depth of the second trench 5 is much greater than that of Embodiment 1, and the gate electrode 12 adopts a split gate structure. The second conductivity type pillar region 4 is still under the second trench 5. The difference is that in order to maintain the charge balance of the superjunction structure, the concentration of the second conductivity type pillar region 4 is much greater than that of Embodiment 1. The split gate structure can reduce the gate-drain overlap area, reduce the gate-drain capacitance, and improve the dynamic characteristics. Example 6
[0075] A multi-level trench SiC MOSFET device, such as Figure 7 As shown, the difference from Embodiment 1 is that the first trench 6 extends close to the bottom of the first conductivity type epitaxial layer 3, the bottom of the second trench 5 contacts the first conductivity type substrate 2, the second conductivity type pillar region 4 is above the second trench 5, and the gate electrode 12 adopts a split gate structure. The second conductivity type pillar region 4 is located above the second trench 5, which can protect the gate dielectric in the first trench 6. At the same time, the second conductivity type pillar region 4 and the second trench 5 can reduce the saturation current and improve the short-circuit characteristics. The split gate structure can reduce the gate-drain overlap area, reduce the gate-drain capacitance, and improve the dynamic characteristics. Example 7
[0076] A multi-level trench SiC MOSFET device, such as Figure 8 As shown, the difference from Embodiment 1 is that the second trench 5 adopts a V-shaped structure, which can reduce the electric field strength borne by the gate dielectric in the second trench 5. Example 8
[0077] A multi-level trench SiC MOSFET device, such as Figure 9 As shown, the difference from Embodiment 1 is that the second trench 5 adopts a V-shaped structure, and the gate electrode 12 adopts a split gate structure. This can reduce the electric field strength borne by the gate dielectric in the second trench 5, while the split gate structure can reduce the gate-drain overlap area, reduce the gate-drain capacitance, and improve dynamic characteristics.
[0078] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A multi-level trench SiC MOSFET device, characterized in that, include: Drain electrode; A substrate of the first conductivity type is located above the drain electrode; A first conductivity type epitaxial layer is located on a first conductivity type substrate; At least two second conductivity type pillar regions are located in the first conductivity type epitaxial layer; At least two second trenches, each second trench being located inside a pillar region of a second conductivity type; The second conductivity type well region is located in the well region epitaxial layer on the surface of the first conductivity type epitaxial layer; At least two first conductivity type source regions, each first conductivity type source region being located in a second conductivity type well region above a second conductivity type pillar region; The second conductivity type heavily doped region is located between two adjacent first conductivity type source regions; At least two first trenches, each first trench is located in the well region epitaxial layer above a second conductivity type pillar region, and longitudinal channels are formed on both sides of each first trench. Each first trench is connected to the second trench in the second conductivity type pillar region below it to form a multi-level trench structure. A gate dielectric layer covers the surface of the multi-level trench structure formed by the first trench and the second trench; The gate electrode is located inside the gate dielectric layer and covers the first trench; At least two isolation dielectric layers are located above the epitaxial layer of the well region; and, The source electrode is located between two adjacent insulating dielectric layers.
2. The multi-level trench SiC MOSFET device according to claim 1, characterized in that, The first conductivity type substrate is a first conductivity type SiC substrate, the first conductivity type epitaxial layer is a first conductivity type SiC epitaxial layer, the second conductivity type pillar region is a second conductivity type SiC pillar region, the second conductivity type well region is a second conductivity type SiC well region, the second conductivity type heavily doped region is a second conductivity type heavily doped region, the first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type.
3. The multi-level trench SiC MOSFET device according to claim 1, characterized in that, The depth-to-width ratio of the second conductivity type pillar region is greater than 2:1, and the distance between the second conductivity type pillar regions in two adjacent cells is greater than or equal to 0.5µm.
4. The multi-level trench SiC MOSFET device according to claim 1, characterized in that, The depth of the first trench is greater than the thickness of the epitaxial layer of the well region.
5. The multi-level trench SiC MOSFET device according to claim 1, characterized in that, The width of the second trench is greater than the width of the first trench, and the difference between the width of the second trench and the width of the first trench is greater than or equal to 0.2µm. The distance between the top of the second trench and the bottom of the second conductivity type well region is greater than or equal to 0.2µm. The distance between the second trenches in two adjacent cells is 0.5µm to 3µm. The difference between the width of the second trench and the width of the second conductivity type pillar region is less than or equal to 1µm.
6. The multi-level trench SiC MOSFET device according to claim 1, characterized in that, Each second trench is located at the top of a second conductivity type pillar region, the depth of the second trench is 0.2µm to 1.5µm, and the doping concentration of the second conductivity type pillar region is 1e. 16 cm -3 ~2e 18 cm -3 .
7. The multi-level trench SiC MOSFET device according to claim 1, characterized in that, When the depth of the second trench is 1.5µm to 5µm, the doping concentration of the second conductivity type pillar region is 2A to 3A, where A = 1e 16 cm -3 ~2e 18 cm -3 .
8. The multi-level trench SiC MOSFET device according to claim 1, characterized in that, The bottom of the first trench extends close to the bottom of the first conductivity type epitaxial layer, and the bottom of the second trench connected to the first trench, which extends close to the bottom of the first conductivity type epitaxial layer, is in contact with the first conductivity type substrate.
9. The method for manufacturing the multi-level trench SiC MOSFET device according to claim 1, characterized in that, Includes the following steps: Step 1: Epitaxially grow an epitaxial layer of the first conductivity type on a substrate of the first conductivity type; Step 2: An etching mask layer is grown on the first conductivity type epitaxial layer prepared in step 1 by chemical vapor deposition. The etching mask layer is patterned by photolithography. The patterned etching mask layer is used to perform inductively coupled plasma etching on the first conductivity type epitaxial layer to remove the first conductivity type epitaxial layer in the region where the second conductivity type pillar is located. Step 3: Remove the etching mask layer prepared in Step 2, and form a second type of conductive pillar region by epitaxial backfilling and CMP process to flatten the surface. Step 4: On the surface of the SiC MOSFET device prepared in Step 3, SiC of the first conductivity type is epitaxially doped to form a first conductivity type epitaxial layer covering the top of the second conductivity type pillar region. An ion implantation mask layer is grown on the surface of the first conductivity type epitaxial layer covering the top of the second conductivity type pillar region by chemical vapor deposition. The ion implantation mask layer is patterned by photolithography. A large dose of ions is implanted into the first conductivity type epitaxial layer covering the top of the second conductivity type pillar region using the ion implantation mask layer until the first conductivity type doped SiC in the region of the first conductivity type epitaxial layer covering the top of the second conductivity type pillar region forms an amorphous state. Step 5: On the surface of the SiC MOSFET device prepared in step 4, SiC of the first conductivity type is epitaxially doped to form a well region epitaxial layer. Through photolithography and ion implantation, a second conductivity type well region is formed in the well region epitaxial layer. A first conductivity type source region is formed in the second conductivity type well region above each second conductivity type pillar region. A second conductivity type heavily doped region is formed between two adjacent first conductivity type source regions. Step 6: A patterned etching mask layer is formed on the surface of the well region epitaxial layer prepared in step 5. The patterned etching mask layer is used to perform inductively coupled plasma etching on the well region epitaxial layer to form a first trench with longitudinal channels on both sidewalls in the well region epitaxial layer above each second conductivity type pillar region. Step 7: Remove the amorphous SiC in the region where the second trench is formed in the first conductivity type epitaxial layer covering the top of the second conductivity type pillar region by wet etching, and form a second trench that communicates with the first trench; Step 8: Remove the etching mask layer prepared in step 6, and perform passivation and high-temperature annealing on the multi-level trench structure formed by connecting the first trench and the second trench. Step 9: A silicon dioxide layer is deposited on the surface of the multi-level trench structure after passivation and high-temperature annealing in step S8 by thermal oxidation and chemical vapor deposition. The silicon dioxide layer is then subjected to high-temperature annealing to form a gate dielectric layer. Polysilicon is grown inside the gate dielectric layer by chemical vapor deposition and polysilicon implantation is performed. Then, polysilicon etching is performed to remove the polysilicon outside the first trench and the polysilicon on the surface of the epitaxial layer of the well region to form the gate electrode. Step 10: An isolation dielectric layer is deposited on the surface of the well region epitaxial layer of the SiC MOSFET device prepared in step 9 to form a source window. A source ohmic contact layer is formed through the source window. A drain ohmic contact layer is formed on the bottom surface of the first conductivity type substrate. A source electrode is formed on the surface of the source ohmic contact layer. A drain electrode is formed on the surface of the drain ohmic contact layer.
10. The method for manufacturing the multi-level trench SiC MOSFET device according to claim 9, characterized in that, In step 4, the injected high-dose ions are aluminum ions or boron ions, and the injected dose is greater than or equal to 5e. 14 cm -3 The injected target peak concentration is greater than or equal to 2e 20 cm -3 .