Driving thin film transistor and display device including the same

Abstract

A driving thin film transistor and a display device including the same. A driving thin film transistor includes an insulating layer disposed on a substrate and including a first trench, a first active layer corresponding to the first trench and including a channel region and a source region and a drain region on both sides of the channel region, a first source electrode and a first drain electrode spaced apart from each other and respectively in contact with the source region and the drain region, and a gate electrode overlapping the channel region, wherein the channel region is disposed on a bottom surface and an inner side surface of the first trench, and the source region and the drain region are disposed on a top surface of the insulating layer.

Description

Technical Field

[0001] This disclosure relates to a driving thin-film transistor and a display device including the driving thin-film transistor, and more specifically, to a driving thin-film transistor capable of ensuring more stable driving characteristics and a display device including the driving thin-film transistor. Background Technology

[0002] Recently, LED display devices using LEDs (light-emitting diodes) as light-emitting elements have been proposed. For example, miniature LEDs or ultra-small LEDs, such as micro LEDs, can be used in LED display devices.

[0003] Micro LED display devices are display devices that generate images by setting micro LEDs (μLEDs) with a size of 100 micrometers or smaller in each pixel area, and have great advantages in terms of low power consumption and miniaturization.

[0004] Meanwhile, in order to control the on / off state of each pixel area, the display device must include a TFT substrate that serves as a switching element, a thin-film transistor (TFT).

[0005] Here, high-performance LED display devices (e.g., high-resolution display devices) require driving TFTs to ensure more stable driving characteristics in order to drive LEDs. For this purpose, research has been actively conducted on channels that improve electron mobility.

[0006] However, as the resolution of display devices has increased in recent years, the size of the pixel area has also decreased, which has led to the problem that the driving TFT cannot ensure the required channel configuration. Summary of the Invention

[0007] Therefore, this disclosure relates to a display device that can achieve stable driving characteristics by ensuring that the channel driving the TFT has an improved electron mobility.

[0008] Additional features and aspects will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practicing the disclosure provided herein. Other features and aspects of the inventive concept may be realized and obtained by means of structures specifically pointed out in the written description or from which they may be derived, the claims, and the drawings.

[0009] To achieve these and other aspects of this disclosure, as embodied and broadly described herein, a driving thin-film transistor includes: an insulating layer disposed on a substrate and including a first trench; a first active layer corresponding to the first trench and including a channel region and source and drain regions located on opposite sides of the channel region; a first source electrode and a first drain electrode spaced apart from each other and respectively contacting the source and drain regions; and a gate electrode overlapping the channel region, wherein the channel region is disposed on a bottom surface and an inner surface of the first trench, and the source and drain regions are disposed on a top surface of the insulating layer.

[0010] The active layer can be formed from an oxide semiconductor.

[0011] The gate electrode can be disposed above the bottom surface and inner surface of the first trench and above the top surface of the insulating layer.

[0012] The gate electrode may be disposed only above the bottom surface and the inner surface of the first trench.

[0013] The driving thin-film transistor may further include: a second active layer and a third active layer; a second source electrode and a third source electrode, which are respectively in contact with the source regions of the second active layer and the third active layer; and a second drain electrode and a third drain electrode, which are respectively in contact with the drain regions of the second active layer and the third active layer, wherein the insulating layer further includes a second trench and a third trench corresponding to the second active layer and the third active layer, respectively.

[0014] The insulating layer may also include a second trench and a third trench, wherein the trench region includes a first trench region, a second trench region and a third trench region, and wherein the first trench region, the second trench region and the third trench region are configured to correspond to the first trench, the second trench and the third trench respectively.

[0015] The driving thin-film transistor may also include a dummy region located between the first channel region, the second channel region, and the third channel region and the source region, and between the first channel region, the second channel region, and the third channel region and the drain region.

[0016] On the other hand, a display device includes: a light-emitting element disposed on a substrate; and a driving thin-film transistor disposed on the substrate and electrically connected to the light-emitting element, wherein the driving thin-film transistor includes: an insulating layer disposed on the substrate and including a first trench; a first active layer corresponding to the first trench and including a channel region and a source region and a drain region located on both sides of the channel region; a first source electrode and a first drain electrode spaced apart from each other and respectively contacting the source region and the drain region; and a gate electrode overlapping the channel region, wherein the channel region is disposed on the bottom surface and inner surface of the first trench, and the source region and the drain region are disposed on the top surface of the insulating layer.

[0017] The light-emitting element can be a miniature LED.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0019] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate aspects of this disclosure and, together with the description, serve to explain the various principles of this disclosure.

[0020] In the attached diagram:

[0021] Figure 1 This is a schematic plan view of the TFT substrate of the display device according to the first embodiment of the present disclosure;

[0022] Figure 2 It is shown schematically. Figure 1 The equivalent circuit diagram of the pixel area;

[0023] Figure 3 This is a schematic view showing the planar structure of the driving TFT in the pixel region of the display device according to the first embodiment of the present disclosure;

[0024] Figure 4 It is along Figure 3 A cross-sectional view taken from line IV-IV';

[0025] Figure 5 It is along Figure 3 A cross-sectional view taken from line V-V';

[0026] Figure 6A This is a view showing a planar structure of a driven TFT according to the prior art;

[0027] Figure 6B This is a view showing the planar structure of the driving TFT according to an embodiment of the present disclosure;

[0028] Figure 7 This is a schematic view illustrating the planar structure of the driving TFT in the pixel region of a display device according to another configuration of the first embodiment of this disclosure;

[0029] Figure 8A and Figure 8B This is a schematic view illustrating the planar structure of the driving TFTs in the pixel region of a display device according to a second embodiment of the present disclosure; and

[0030] Figure 9 This is a schematic view illustrating the planar structure of the driving TFT in another pixel region according to a second embodiment of the present disclosure. Detailed Implementation

[0031] Reference will now be made in detail to various aspects of this disclosure, examples of which are shown in the accompanying drawings.

[0032] -First Implementation Method-

[0033] Figure 1 This is a schematic plan view of the TFT substrate of the display device according to the first embodiment of the present disclosure, and Figure 2 It is shown schematically. Figure 1 The equivalent circuit diagram of the pixel area. Here, the TFT substrate can also be referred to as the array substrate.

[0034] exist Figure 1 and Figure 2 In the first embodiment of the present disclosure, a display area AA, which serves as an active area for realizing an image, and a non-display area NA, which surrounds the display area AA, can be defined on the TFT substrate 10 of the display device 100.

[0035] In the display area AA, multiple pixel areas P can be arranged in a matrix. For example, the multiple pixel areas P may include R, G, and B pixel areas P that display red, green, and blue respectively. The R, G, and B pixel areas P can be arranged alternately along one direction.

[0036] Many elements for driving pixel region P can be formed in each pixel region P. For example, multiple TFTs ST, DT1, DT2 and DT3, as well as light-emitting element OD, can be formed in each pixel region P.

[0037] In the non-display area NA, a driving circuit for driving the elements of the pixel area P of the display area AA can be provided. For example, an output scan signal (e.g., a strobe signal) can be provided in the non-display area NA and supplied to the scan driving circuit SDC of the pixel area P. The scan driving circuit SDC can be directly formed on the TFT substrate 10.

[0038] The scan drive circuit SDC, which is directly formed on the TFT substrate 10, is a so-called gated-in-board (GIP) type drive circuit and can be formed during the manufacturing process of the TFT substrate 10 (specifically, the element in the display area AA). The GIP type scan drive circuit SDC may include multiple drive circuit TFTs having the same or similar structure as the TFT of the pixel area P.

[0039] Reference Figure 2The configuration of pixel region P will be described in more detail. Pixel region P may include switching TFT ST, driving TFTs DT1, DT2 and DT3, and may also include light-emitting element OD and storage capacitor Cst.

[0040] The switching TFT ST can be connected to a gate line GL and a data line DL that intersect to define a pixel area P. For example, the gate of the switching TFT ST can be connected to the gate line GL, and the drain of the switching TFT ST can be connected to the data line DL.

[0041] The switching TFT ST can be turned on in response to the gating voltage applied through the gating line GL of the corresponding row line, so the data voltage provided through the data line DL can be applied to the driving TFTs DT1, DT2 and DT3.

[0042] The driving TFTs DT1, DT2, and DT3 can be configured to connect to the switching TFT ST and the light-emitting element OD. For example, the gate electrodes of the driving TFTs DT1, DT2, and DT3 can be electrically connected to the source electrodes of the switching TFT ST, and the source electrodes of the driving TFTs DT1, DT2, and DT3 can be electrically connected to the light-emitting element OD.

[0043] The drain electrodes of driving TFTs DT1, DT2, and DT3 can be configured to receive a first power supply voltage Vdd. Here, when driving TFTs DT1, DT2, and DT3 are configured as N-type transistors, the first power supply voltage Vdd can be a high-potential voltage.

[0044] As described above, the driving TFTs DT1, DT2 and DT3 control the emission current applied to the light-emitting element OD according to the voltage applied to the gate electrode, and the light-emitting element OD emits light through the emission current provided by the driving TFTs DT1, DT2 and DT3.

[0045] The light-emitting element OD can be configured such that the anode electrode is connected to the source electrode of the driving TFTs DT1, DT2 and DT3, and the cathode electrode receives a low potential voltage Vss as a second power supply voltage Vss.

[0046] Here, the light-emitting element OD can be an organic light-emitting diode (OLED), but in some cases, it can be a light-emitting diode (LED), a micro light-emitting diode (μLED), etc.

[0047] The storage capacitor Cst is connected to the gate electrode of the driving TFTs DT1, DT2, and DT3 to maintain the voltage applied to it until the next frame. The storage capacitor Cst can be configured such that one electrode of the storage capacitor Cst is connected to the gate electrode of the driving TFTs DT1, DT2, and DT3, and the other electrode of the storage capacitor Cst is connected to the drain electrode or source electrode of the driving TFTs DT1, DT2, and DT3.

[0048] According to the first embodiment of this disclosure, the driving TFTs DT1, DT2 and DT3 can be configured to be connected in parallel.

[0049] The driving TFTs DT1, DT2, and DT3 may include a first driving TFT DT1 disposed on the substrate 10, a second driving TFT DT2 disposed on one side of the first driving TFT DT1, and a third driving TFT DT3 disposed on one side of the second driving TFT DT3. Here, the first driving TFT DT1, the second driving TFT DT2, and the third driving TFT DT3 may be connected in parallel with each other and may share a gate electrode.

[0050] As described above, by connecting multiple driving TFTs DT1, DT2 and DT3 in parallel, the excessive current flow applied to the driving TFTs DT1, DT2 and DT3 is dispersed to distribute the stress caused by the current.

[0051] In other words, as the current increases, the TFT deteriorates due to the increased stress caused by the current, thus exacerbating the changes in operating characteristics. However, the driving TFTs DT1, DT2, and DT3 according to the first embodiment of this disclosure allow for the dispersion of excessive current applied thereto while possessing sufficient driving capability to drive the light-emitting element OD.

[0052] This can extend the lifespan of the drive components.

[0053] Specifically, since the display device 100 according to the present disclosure can increase the channel width of driving TFTs DT1, DT2 and DT3 in a limited area of ​​pixel region P, the stable driving characteristics of light-emitting element OD can also be ensured.

[0054] Figure 3 This is a schematic view illustrating the planar structure of the driving TFT in the pixel region of the display device according to the first embodiment of the present disclosure. Figure 4 It is along Figure 3 The cross-sectional view taken from line IV-IV', and Figure 5 It is along Figure 3 A cross-sectional view taken from line V-V'.

[0055] Figure 6A This is a view showing the planar structure of a driven TFT according to the prior art, and Figure 6B This is a view showing the planar structure of the driving TFT according to an embodiment of the present disclosure. Figure 7 This is a schematic view illustrating the planar structure of the driving TFT in the pixel region of a display device according to another configuration of the first embodiment of the present disclosure.

[0056] Before the description, for ease of explanation, the length direction of the gate electrode 150, which is a component driving TFTs DT1, DT2 and DT3, is defined as the first direction, and the separation direction between the source electrodes 170a, 170b and 170c, which are perpendicular to the first direction, and the drain electrodes 180a, 180b and 180c is defined as the second direction.

[0057] exist Figure 3 In the figure, a first driving TFT DT1, a second driving TFT DT2, and a third driving TFT DT3 are arranged side by side on a substrate 10. The first driving TFT DT1, the second driving TFT DT2, and the third driving TFT DT3 are spaced apart from each other along a first direction (horizontal direction) defined in the figure.

[0058] In the first driving TFT DT1, the first source electrode 170a and the first drain electrode 180a are spaced apart from each other along a second direction (which is vertical) defined in the figure, and the first active layer 130a is disposed in the region between the first source electrode 170a and the first drain electrode 180a.

[0059] Furthermore, a second driving TFT DT2 is disposed on one side of the first driving TFT DT1 along a first direction. In the second driving TFT DT2, a second source electrode 170b and a second drain electrode 180b are spaced apart from each other along a second direction, and a second active layer 130b is disposed between the second source electrode 170b and the second drain electrode 180b.

[0060] Furthermore, a third driving TFT DT3 is disposed on one side of the second driving TFT DT2 along a first direction. In the third driving TFT DT3, a third source electrode 170c and a third drain electrode 180c are spaced apart from each other along a second direction, and a third active layer 130c is disposed between the third source electrode 170c and the third drain electrode 180c.

[0061] The first driving TFT DT1, the second driving TFT DT2, and the third driving TFT DT3 are connected in parallel.

[0062] The gate electrode 150 overlaps with the first active layer 130a, the second active layer 130b, and the third active layer 130c, and is disposed along a first direction. The first driving TFT DT1, the second driving TFT DT2, and the third driving TFT DT3 share the gate electrode 150.

[0063] The first interlayer insulating layer 140 is inserted between the gate electrode 150 and the first active layer 130a, the second active layer 130b, and the third active layer 130c. The first interlayer insulating layer 140 and the second interlayer insulating layer 160 are inserted between the first active layer 130a, the second active layer 130b, and the third active layer 130c and the first source electrode 170a, the second source electrode 170b, and the third source electrode 170c, and are also inserted between the first active layer 130a, the second active layer 130b, and the third active layer 130c and the first drain electrode 180a, the second drain electrode 180b, and the third drain electrode 180c.

[0064] The first active layer 130a is electrically connected to the first source electrode 170a and the first drain electrode 180a through first semiconductor contact holes 161a and 161b disposed in the first interlayer insulating layer 140 and the second interlayer insulating layer 160, respectively. The second active layer 130b is electrically connected to the second source electrode 170b and the second drain electrode 180b through third semiconductor contact holes 163a and 163b disposed in the first interlayer insulating layer 140 and the second interlayer insulating layer 160, respectively. The third active layer 130c is electrically connected to the third source electrode 170c and the third drain electrode 180c through fifth semiconductor contact holes 165a and 165b disposed in the first interlayer insulating layer 140 and the second interlayer insulating layer 160, respectively.

[0065] Here, according to the first embodiment of this disclosure Figure 1 The display device 100 is characterized in that an active insulating layer 110 is also provided on the substrate 10, and a first trench 120a, a second trench 120b and a third trench 120c are provided in the active insulating layer 110.

[0066] Although the first groove 120a, the second groove 120b, and the third groove 120c are shown as rectangles in the plan view, this disclosure is not limited thereto. In another embodiment, the first groove 120a, the second groove 120b, and the third groove 120c can be formed in various shapes, such as hexagons, quadrilaterals, triangles, circles, etc., as shown in the plan view.

[0067] The first trench 120a, the second trench 120b, and the third trench 120c expose the substrate 10 through the bottom surface 110a. The inner surface 110b and the top surface 110c connected to the adjacent inner surface 110b are provided in the active insulating layer 110 due to the first trench 120a, the second trench 120b, and the third trench 120c.

[0068] The first trench 120a, the second trench 120b, and the third trench 120c are configured to correspond to the respective interval regions between the first source electrode 170a, the second source electrode 170b, and the third source electrode 170c and the first drain electrode 180a, the second drain electrode 180b, and the third drain electrode 180c. The first active layer 130a, the second active layer 130b, and the third active layer 130c are configured to correspond to the first trench 120a, the second trench 120b, and the third trench 120c, respectively.

[0069] In this configuration, the first trench 120a, the second trench 120b, and the third trench 120c are formed to have planar areas smaller than those of the first active layer 130a, the second active layer 130b, and the third active layer 130c, respectively. Therefore, the first active layer 130a, the second active layer 130b, and the third active layer 130c respectively cover the inner surface 110b of the first trench 120a, the second trench 120b, and the third trench 120c, and each extends to a portion of the top surface 110c of the active insulating layer 110 surrounding the first trench 120a, the second trench 120b, and the third trench 120c. That is, the first active layer 130a, the second active layer 130b and the third active layer 130c are in contact with the top surface 110c of the active insulating layer 110.

[0070] As a result, the first active layer 130a, the second active layer 130b, and the third active layer 130c are respectively formed in the first trench 120a, the second trench 120b, and the third trench 120c, which includes the bottom surface 110a, on the top surface 110c of the active insulating layer 110, and on the inner surface 110b of the first trench 120a, the second trench 120b, and the third trench 120c, thereby forming in three dimensions.

[0071] As described above, the first active layer 130a, the second active layer 130b, and the third active layer 130c are formed in three dimensions, thereby increasing the channel width.

[0072] That is, a channel region overlapping with the gate electrode 150 is defined in the first active layer 130a, the second active layer 130b and the third active layer 130c on the plane, and a channel length (which is the length between the source electrodes 170a, 170b and 170c and the drain electrodes 180a, 180b and 180c) is defined in the channel region.

[0073] In addition, when the width direction is defined to be substantially perpendicular to the channel length, the channel width is designed to be greater than the channel length.

[0074] When the channel width is greater than the channel length, the electron mobility can be improved because more electrons can flow simultaneously, and the driving TFTs DT1, DT2, and DT3 can have switching capabilities for supplying electrons. Figure 2 The high current structure of the light-emitting element OD is more advantageous.

[0075] Therefore, it can also ensure Figure 2 The stable driving characteristics of the light-emitting element OD.

[0076] For more specific reference Figure 4 and Figure 5 Substrate 10 supports Figure 1 The various components of the display device 100, and the substrate 10 may be formed of glass or a flexible plastic material.

[0077] For example, when the substrate 10 is formed of a plastic material, the substrate 10 can be formed of polyimide (PI). In this case, moisture components can penetrate the substrate 10 formed of polyimide (PI), and moisture penetration can proceed to... Figure 2 The driving TFTs DT1, DT2, and DT3 or the light-emitting element OD are damaged. Figure 1 The display device 100.

[0078] Therefore, in order to prevent Figure 1 The performance of the display device 100 is degraded due to moisture infiltration, and the substrate 10 can be configured as a double polyimide. Furthermore, an inorganic layer is formed between the two polyimides to prevent moisture components from penetrating the lower polyimide, thereby improving the reliability of the product performance. The inorganic layer can be a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0079] An active insulating layer 110 is disposed on the substrate 10, and a first trench 120a, a second trench 120b, and a third trench 120c are disposed in the active insulating layer 110 and spaced apart from each other. A first active layer 130a, a second active layer 130b, and a third active layer 130c are respectively disposed in the first trench 120a, the second trench 120b, and the third trench 120c.

[0080] Here, the first active layer 130a, the second active layer 130b, and the third active layer 130c are configured to cover the inner surface 110b of the first trench 120a, the inner surface 110b of the second trench 120b, and the inner surface 110b of the third trench 120c, respectively, and each extends to a portion of the top surface 110c of the active insulating layer 110 surrounding the first trench 120a, the second trench 120b, and the third trench 120c.

[0081] The first active layer 130a, the second active layer 130b, and the third active layer 130c may include: a first channel region CH1, a second channel region CH2, and a third channel region CH3; a first source region SD1, a second source region SD2, and a third source region SD3; and a first drain region DD1, a second drain region DD2, and a third drain region DD3. When the first driving TFT DT1, the second driving TFT DT2, and the third driving TFT DT3 are driven, corresponding channels are formed in the first channel region CH1, the second channel region CH2, and the third channel region CH3. The first source region SD1, the second source region SD2, and the third source region SD3, as well as the first drain region DD1, the second drain region DD2, and the third drain region DD3, are respectively disposed on both sides of the first channel region CH1, the second channel region CH2, and the third channel region CH3.

[0082] The first active layer 130a, the second active layer 130b, and the third active layer 130c can be formed of at least one metal oxide selected from various metal oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), indium gallium oxide (IGO), etc.

[0083] The first active layer 130a, the second active layer 130b, and the third active layer 130c are formed of oxide semiconductors, such that, according to the first embodiment of this disclosure... Figure 1 The display device 100 can have high mobility and uniformity characteristics.

[0084] Alternatively, the first active layer 130a, the second active layer 130b, and the third active layer 130c may be formed of, for example, low-temperature polycrystalline silicon (LTPS) or polycrystalline silicon (a-Si).

[0085] A first interlayer insulating layer 140 is disposed on a first active layer 130a, a second active layer 130b, and a third active layer 130c. The first interlayer insulating layer 140 may be configured as a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0086] The gate electrode 150 is disposed on the first interlayer insulating layer 140, thereby overlapping with the channel regions CH1, CH2 and CH3 of the first active layer 130a, the second active layer 130b and the third active layer 130c. The first driving TFT DT1, the second driving TFT DT2 and the third driving TFT DT3 may share the gate electrode 150.

[0087] The gate electrode 150 may be formed of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (nd) or an alloy thereof, and may be a single layer or multiple layers.

[0088] Here, the first channel region CH1, the second channel region CH2, and the third channel region CH3, the first source region SD1, the second source region SD2, and the third source region SD3, and the first drain region DD1, the second drain region DD2, and the third drain region DD3 of the first active layer 130a, the second active layer 130b, and the third active layer 130c can be defined by ion doping (impurity doping). The first channel region CH1, the second channel region CH2, and the third channel region CH3 are defined by using the gate electrode 150 as a mask to block ion doping.

[0089] Therefore, the gate electrode 150 overlaps with the first channel region CH1, the second channel region CH2, and the third channel region CH3 of the first active layer 130a, the second active layer 130b, and the third active layer 130c. Thus, impurities are doped in the first source region SD1, the second source region SD2, and the third source region SD3, as well as the first drain region DD1, the second drain region DD2, and the third drain region DD3, while impurities are not doped in the first channel region CH1, the second channel region CH2, and the third channel region CH3.

[0090] Then, a second interlayer insulating layer 160 is formed on the gate electrode 150. The second interlayer insulating layer 160 may be configured as a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0091] A first semiconductor contact hole 161a, a second semiconductor contact hole 161b, a third semiconductor contact hole 163a, a fourth semiconductor contact hole 163b, a fifth semiconductor contact hole 165a, and a sixth semiconductor contact hole 165b are provided in the first interlayer insulating layer 140 and the second interlayer insulating layer 160. The first semiconductor contact hole 161a and the second semiconductor contact hole 161b expose the first source region SD1 and the first drain region DD1 of the first active layer 130a, respectively. The third semiconductor contact hole 163a and the fourth semiconductor contact hole 163b expose the second source region SD2 and the second drain region DD2 of the second active layer 130b, respectively. The fifth semiconductor contact hole 165a and the sixth semiconductor contact hole 165b expose the third source region SD3 and the third drain region DD3 of the third active layer 130c, respectively. Each of the first semiconductor contact hole 161a, the second semiconductor contact hole 161b, the third semiconductor contact hole 163a, the fourth semiconductor contact hole 163b, the fifth semiconductor contact hole 165a, and the sixth semiconductor contact hole 165b may include two contact holes.

[0092] The first source electrode 170a, the second source electrode 170b, and the third source electrode 170c, as well as the first drain electrode 180a, the second drain electrode 180b, and the third drain electrode 180c, are disposed on the second interlayer insulating layer 160. The first source electrode 170a, the second source electrode 170b, and the third source electrode 170c, as well as the first drain electrode 180a, the second drain electrode 180b, and the third drain electrode 180c, are connected to the first source region SD1, the second source region SD2, and the third source region SD3, and the first drain region DD1, the second drain region DD2, and the third drain region DD3 of the first active layer 130a, the second active layer 130b, and the third active layer 130c through the first semiconductor contact hole 161a, the second semiconductor contact hole 161b, the third semiconductor contact hole 163a, the fourth semiconductor contact hole 163b, the fifth semiconductor contact hole 165a, and the sixth semiconductor contact hole 165b.

[0093] Specifically, the first source electrode 170a and the first drain electrode 180a are connected to the first source region SD1 and the first drain region DD1 of the first active layer 130a, respectively, through the first semiconductor contact hole 161a and the second semiconductor contact hole 161b. The second source electrode 170b and the second drain electrode 180b are connected to the second source region SD2 and the second drain region DD2 of the second active layer 130b, respectively, through the third semiconductor contact hole 163a and the fourth semiconductor contact hole 163b. The third source electrode 170c and the third drain electrode 180c are connected to the third source region SD3 and the third drain region DD3 of the third active layer 130c, respectively, through the fifth semiconductor contact hole 165a and the sixth semiconductor contact hole 165b.

[0094] The first source electrode 170a, the second source electrode 170b, and the third source electrode 170c, as well as the first drain electrode 180a, the second drain electrode 180b, and the third drain electrode 180c, are formed of one or more of aluminum (Al), aluminum alloys such as aluminum-neodymium (AlNd), copper (Cu), copper alloys, molybdenum (Mo), molybdenum-titanium (MoTi), chromium (Cr), and titanium (Ti) having low resistivity.

[0095] A first source electrode 170a and a first drain electrode 180a, a first active layer 130a including a first source region SD1 and a first drain region DD1 in contact with electrodes 170a and 180a, and a gate electrode 150 disposed on the first active layer 130a constitute a first driving TFT DT1. A second source electrode 170b and a second drain electrode 180b, a second active layer 130b including a second source region SD2 and a second drain region DD2 in contact with electrodes 170b and 180b, and a gate electrode 150 disposed on the second active layer 130b constitute a second driving TFT DT2.

[0096] The third source electrode 170c and the third drain electrode 180c, the third active layer 130c including the third source region SD3 and the third drain region DD3 in contact with the electrodes 170c and 180c, and the gate electrode 150 disposed on the third active layer 130c constitute the second driving TFT DT3.

[0097] According to the first embodiment of this disclosure Figure 1 In the display device 100, a first trench 120a, a second trench 120b, and a third trench 120c are formed in an active insulating layer 110, and a first active layer 130a, a second active layer 130b, and a third active layer 130c are configured to correspond to the first trench 120a, the second trench 120b, and the third trench 120c, respectively. Specifically, the first active layer 130a, the second active layer 130b, and the third active layer 130c cover the inner surface 110b of the first trench 120a, the second trench 120b, and the third trench 120c of the active insulating layer 110, and extend to a portion of the top surface 110c of the active insulating layer 110 surrounding the first trench 120a, the second trench 120b, and the third trench 120c, thereby widening the channel width of the first active layer 130a, the second active layer 130b, and the third active layer 130c.

[0098] More specifically, the operating characteristics of TFTs DT1, DT2, and DT3 can be improved by increasing the mobility of electrons flowing through the active layers 130a, 130b, and 130c. The mobility is affected by the length (i.e., channel length) between the source electrodes 170a, 170b, and 170c and the drain electrodes 180a, 180b, and 180c, and the channel width.

[0099] The data current I flowing through TFTs DT1, DT2 and DT3 data This is represented by Equation 1 below.

[0100] Equation 1

[0101]

[0102] Here, μ is the electron mobility of TFTs DT1, DT2, and DT3, Cox is the capacitance per unit area of ​​the capacitor formed by the gate electrode 150 and the channel regions CH1, CH2, and CH3 of TFTs DT1, DT2, and DT3, W is the width of the channel regions CH1, CH2, and CH3 of TFTs DT1, DT2, and DT3, L is the length of the channel regions CH1, CH2, and CH3 of TFTs DT1, DT2, and DT3, Vth is the threshold voltage of TFTs DT1, DT2, and DT3, and Vdata is due to the voltage from... Figure 2 The data line DL provides the data current I data And stored in Figure 2 The voltage in the storage capacitor Cst. In this case, μ and Cox may vary due to the manufacturing process.

[0103] In Equation 1 above, when driving TFTs DT1, DT2, and DT3, the data current I... data This corresponds to the conduction current flowing through the channel. It can be seen that the conduction current is inversely proportional to the length L of the channel regions CH1, CH2, and CH3, and directly proportional to the width W of the channel regions CH1, CH2, and CH3.

[0104] Therefore, if the width W of the channel regions CH1, CH2 and CH3 is very wide and the length L of the channel regions CH1, CH2 and CH3 is very short, more electrons can flow in simultaneously, thus improving electron mobility and further enhancing the operating characteristics of TFTDT1, DT2 and DT3.

[0105] Therefore, in accordance with the first embodiment of this disclosure Figure 1In the display device 100, the first active layer 130a, the second active layer 130b and the third active layer 130c are configured to correspond to the first trench 120a, the second trench 120b and the third trench 120c respectively, such that the width W of the trench is wider than the length L of the trench defined on the plane.

[0106] As a result, the operating characteristics of TFTs DT1, DT2, and DT3 were improved, thus ensuring... Figure 2 The stable driving characteristics of the light-emitting element OD.

[0107] That is to say, in accordance with the first embodiment of this disclosure Figure 1 In the display device 100, in order to achieve high resolution, although Figure 1 The size of pixel region P is reduced and Figure 1 The area of ​​TFTs DT1, DT2, and DT3 in each pixel region P is also reduced, but the channel width W driving TFTs DT1, DT2, and DT3 can be... Figure 1 Increase within a limited area of ​​pixel region P.

[0108] As mentioned above, when the channel width W is greater than the channel length L, the electron mobility can be increased because more electrons can flow in the same amount of time. Therefore, the driving TFTs DT1, DT2, and DT3 can have the ability to switch the electrons supplied to the channel. Figure 2 The high current structure of the light-emitting element OD is more advantageous.

[0109] Therefore, driving TFTs DT1, DT2, and DT3 can ensure more stable driving characteristics, thereby also ensuring... Figure 2 The stable driving characteristics of the light-emitting element OD.

[0110] Figure 6A This is a view showing the planar structure of a driven TFT according to the prior art, and Figure 6B This is a view showing the planar structure of the driving TFT according to an embodiment of the present disclosure. Figure 6A and Figure 6B In the driving TFT, the first active layer 130a, the second active layer 130b, and the third active layer 130c have similar channel widths W. That is, due to the presence of... Figure 5 The grooves 120a, 120b and 120c, therefore Figure 6B The channel width W of the first active layer 130a, the second active layer 130b, and the third active layer 130c of the driving TFT is... Figure 6A The channel widths W of the first active layer 130a, the second active layer 130b, and the third active layer 130c of the driving TFT are similar.

[0111] Here, it can be seen that in order to ensure the channel width W, Figure 6B The driving TFT requires a very large area on a plane. On the other hand, although... Figure 6A Compared to the driving TFT, Figure 6B The driving TFT is implemented in a very narrow area on a plane, but because the channel width W is along... Figure 5 The bottom surface 110a and inner surface 110b of the grooves 120a, 120b and 120c are formed, so Figure 6B The driving TFT can be formed to have the same characteristics as... Figure 6A The channel width W is similar to that of the driving TFT.

[0112] Therefore, in accordance with the embodiments of this disclosure Figure 1 In the display device 100, the channel width W driving TFTs DT1, DT2, and DT3 can be... Figure 1 Increase the pixel area P in a limited region.

[0113] As a result, in accordance with the first embodiment of this disclosure Figure 1 In the display device 100, in order to achieve high resolution, although Figure 1 The size of pixel region P is reduced and Figure 1 The area of ​​TFTs DT1, DT2, and DT3 in each pixel region P is also reduced, but the channel width W driving TFTs DT1, DT2, and DT3 can be... Figure 1 The increase within a limited area of ​​pixel region P can also ensure Figure 2 The stable driving characteristics of the light-emitting element OD.

[0114] According to the first embodiment of this disclosure Figure 1 In the display device 100, a gate electrode 150 disposed across a first active layer 130a, a second active layer 130b, and a third active layer 130c is shown, completely covering the first trench 120a, the second trench 120b, and the third trench 120c. Alternatively, as... Figure 7 As shown, the gate electrode 150 can be formed in the first trench 120a, the second trench 120b, and the third trench 120c of the active insulating layer 110. That is, along the vertical direction in the context of the figure, the length of the gate electrode 150 can be shorter than the lengths of the trenches 120a, 120b, and 120c.

[0115] When the gate electrode 150 is disposed in the first trench 120a, the second trench 120b, and the third trench 120c, the channel width W can be partially reduced, and the channel length L can also be reduced. Therefore, power consumption can be further reduced, and the size of the driving TFTs DT1, DT2, and DT3 can also be reduced, thereby achieving high resolution.

[0116] -Second Implementation Method-

[0117] Figure 8A and Figure 8B This is a schematic view illustrating the planar structure of the driving TFT in the pixel region of the display device according to the second embodiment of the present disclosure, and Figure 9 This is a schematic view illustrating the planar structure of the driving TFT in another pixel region of the second embodiment of this disclosure.

[0118] The same reference numerals are given to the parts that are the same as in the first embodiment, and the explanations of the same parts will be shortened or omitted.

[0119] Although the first driving TFT DT1, the second driving TFT DT2 and the third driving TFT DT3 are provided in the first embodiment, a single driving TFT DT is provided in the second embodiment.

[0120] As shown in the figure, the active layer 130 is set Figure 5 On the substrate 10. The active layer 130 may include a source region SD and a drain region DD arranged substantially parallel to each other along a first direction defined in the figure, and a first channel region CH1, a second channel region CH2, and a third channel region CH3 spaced apart from each other and connected to the source region SD and the drain region DD along a second direction defined in the figure, so as to realize a multi-channel. Figure 3 The first active layer 130a, the second active layer 130b and the third active layer 130c are connected to each other to form a single unit, and each can have two openings located between two adjacent channel regions in the first channel region CH1, the second channel region CH2 and the third channel region CH3.

[0121] The gate electrode 150 is disposed on the active layer 130. Figure 5 The first interlayer insulating layer 140 is inserted therebetween along the second direction defined in the figure. The gate electrode 150 is disposed across and overlaps with the first channel region CH1, the second channel region CH2 and the third channel region CH3.

[0122] Figure 5 The second interlayer insulating layer 160 is disposed on the gate electrode 150, and the source electrode 170 and the drain electrode 180 are disposed on... Figure 5 The second interlayer insulating layer 160. The source electrode 170 and drain electrode 180 are respectively connected to the second interlayer insulating layer 160. Figure 5 The source region SD and drain region DD of the active layer 130 are exposed by the first semiconductor contact hole 161a and the second semiconductor contact hole 161b disposed in the first interlayer insulating layer 140 and the second interlayer insulating layer 160.

[0123] Here, the display device according to the second embodiment of this disclosure is characterized in that, Figure 5 The active insulation layer 110 is also set in Figure 5 On the substrate 10, the first trench 120a, the second trench 120b and the third trench 120c are disposed. Figure 5 In the active insulating layer 110.

[0124] Furthermore, the first trench region CH1, the second trench region CH2, and the third trench region CH3 are configured to correspond to the first trench 120a, the second trench 120b, and the third trench 120c, respectively. The first trench 120a, the second trench 120b, and the third trench 120c are formed to have planar areas smaller than those of the first trench region CH1, the second trench region CH2, and the third trench region CH3, respectively. Therefore, the first trench region CH1, the second trench region CH2, and the third trench region CH3 respectively cover... Figure 5 The inner surface 110b of the first trench 120a, the inner surface 110b of the second trench 120b, and the inner surface 110b of the third trench 120c, respectively, and each extends to the inner surface 110b of the third trench 120c. Figure 5 Around the first trench 120a, the second trench 120b and the third trench 120c Figure 5 A portion of the top surface 110c of the active insulating layer 110.

[0125] As a result, the first trench region CH1, the second trench region CH2, and the third trench region CH3 are formed in the first trench 120a, the second trench 120b, and the third trench 120c, respectively. Figure 5 On a portion of the top surface 110c of the active insulating layer 110, and formed on Figure 5 The first groove 120a is formed in three dimensions on the inner surface 110b of the first groove 120a, the inner surface 110b of the second groove 120b, and the inner surface 110b of the third groove 120c.

[0126] As described above, the first channel region CH1, the second channel region CH2, and the third channel region CH3 are formed in three dimensions, thereby increasing the channel width W.

[0127] like Figure 8A As shown, the gate electrode 150 overlapping with the first channel region CH1, the second channel region CH2, and the third channel region CH3 can be configured to completely cover the channel region. Figure 5 The active insulating layer 110 has a first trench 120a, a second trench 120b, and a third trench 120c. Alternatively, such as Figure 8B As shown, the gate electrode 150 can be formed as disposed in Figure 5In the first trench 120a, the second trench 120b and the third trench 120c of the active insulating layer 110.

[0128] In addition, such as Figure 9 As shown, the active layer 130 may further include a dummy region D located between the source region SD and the first channel region CH1, the second channel region CH2 and the third channel region CH3, and between the drain region DD and the first channel region CH1, the second channel region CH2 and the third channel region CH3.

[0129] Therefore, the electric field can be distributed throughout the entire active layer 130, thus minimizing the difference in current intensity at each location of the active layer 130. Consequently, the intensity of the current output from the driving TFT DT can be more uniform, making the current from... Figure 2 The brightness of the light generated by the light-emitting element OD can also be more uniform.

[0130] Meanwhile, in the description to date, the driving TFTs DT1, DT2, and DT3, or the driving TFT DT, have a top gate structure. However, this disclosure is not limited thereto, and the driving TFTs DT1, DT2, and DT3, or the driving TFT DT, may have a bottom gate structure.

[0131] Furthermore, in the description to date, the first driving TFT DT1, the second driving TFT DT2, and the third driving TFT DT3 have been shown and described in parallel connection with each other, or multiple channels have been configured in a single driving TFT DT. Alternatively, a single-channel driving TFT may be provided. However, this disclosure is not limited thereto.

[0132] Furthermore, even when the first driving TFT DT1, the second driving TFT DT2, and the third driving TFT DT3 are connected in parallel, the channel can be configured as a single channel. That is, the first driving TFT DT1, the second driving TFT DT2, and the third driving TFT DT3 can share a single active layer 130. In this case, multiple trenches 120a, 120b, and 120c can be disposed in a single channel region of the active layer 130.

[0133] As described above, according to this disclosure, an active insulating layer including a first trench, a second trench, and a third trench is disposed on a substrate, and the first active layer, the second active layer, and the third active layer are configured to correspond to the first trench, the second trench, and the third trench respectively, such that the first active layer, the second active layer, and the third active layer can have an increased channel width.

[0134] Therefore, while reducing the pixel size and the area of ​​the TFT in each pixel region, the channel width of the driving TFT can be increased within the limited area of ​​the pixel region when achieving high resolution. This allows for more stable driving characteristics of the driving TFT, thereby ensuring stable driving characteristics of the light-emitting element.

[0135] It will be apparent to those skilled in the art that various modifications and variations can be made to the display device of this disclosure without departing from the technical spirit or scope thereof. Therefore, this disclosure is intended to cover any modifications and variations made to this disclosure that fall within the scope of the appended claims and their equivalents.

[0136] Cross-reference to related applications

[0137] This application claims priority to Korean Patent Application No. 10-2021-0161104, filed on November 22, 2021, which is incorporated herein by reference in its entirety.

Claims

1. A driving thin-film transistor, the driving thin-film transistor comprising: An insulating layer is disposed on a substrate and includes a first trench, a second trench, and a third trench; The first active layer, the second active layer, and the third active layer correspond to the first trench, the second trench, and the third trench, respectively. Each of the first active layer, the second active layer, and the third active layer includes a channel region and source and drain regions on both sides of the channel region. A first source electrode and a first drain electrode, the first source electrode and the first drain electrode being spaced apart from each other and respectively in contact with the source region and the drain region; The second source electrode and the third source electrode are respectively in contact with the source regions of the second active layer and the third active layer; The second drain electrode and the third drain electrode are respectively in contact with the drain regions of the second active layer and the third active layer; A gate electrode is continuously formed in the first trench, the second trench, and the third trench, and the gate electrode overlaps with the channel regions of the first active layer, the second active layer, and the third active layer. The channel region is disposed on the bottom surface and inner surface of each of the first trench, the second trench, and the third trench, and the source region and the drain region are disposed on the top surface of the insulating layer. The first active layer, the second active layer, and the third active layer share the gate electrode.

2. The driving thin-film transistor according to claim 1, wherein, The first active layer, the second active layer, and the third active layer are formed of oxide semiconductor.

3. The driving thin-film transistor according to claim 1, wherein, The gate electrode is disposed above the bottom and inner surfaces of each of the first trench, the second trench, and the third trench, as well as above the top surface of the insulating layer.

4. The driving thin-film transistor according to claim 1, wherein, The gate electrode is disposed above the bottom surface and inner surface of each of the first trench, the second trench and the third trench.

5. The driving thin-film transistor according to claim 1, wherein the driving thin-film transistor further comprises a first interlayer insulating layer disposed on the first active layer, the second active layer and the third active layer.

6. The driving thin-film transistor according to claim 5, wherein, The channel area includes a first channel area, a second channel area, and a third channel area, and The gate electrode is disposed on the first interlayer insulating layer, thereby overlapping with the first channel region, the second channel region and the third channel region.

7. The driving thin-film transistor according to claim 1, in, The channel area includes a first channel area, a second channel area, and a third channel area, and The first channel area, the second channel area, and the third channel area are configured to correspond to the first trench, the second trench, and the third trench, respectively.

8. The driving thin-film transistor according to claim 7, wherein, The first trench, the second trench, and the third trench are disposed in the insulating layer and spaced apart from each other.

9. The driving thin-film transistor according to claim 7, wherein the driving thin-film transistor further comprises a dummy region located between the first channel region, the second channel region, and the third channel region and the source region, and between the first channel region, the second channel region, and the third channel region and the drain region.

10. A display device, the display device comprising: A light-emitting element, wherein the light-emitting element is disposed above the substrate; as well as The driving thin-film transistor according to any one of claims 1 to 9 is disposed above the substrate and electrically connected to the light-emitting element.

11. The display device according to claim 10, wherein, The light-emitting element is a miniature LED.

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