Method for removing offset of integrated circuit and integrated circuit

Abstract

A method for removing offset of an integrated circuit and the integrated circuit, the method comprising: determining digital codes of differential input voltages of an amplifier in a first receive channel of the integrated circuit, the first receive channel of the integrated circuit comprising a plurality of amplifiers; comparing the digital codes with a digital code corresponding to an optimal common mode voltage of the integrated circuit; determining a bias code for adjusting the differential input voltages to match the optimal common mode voltage according to the comparison result; and inputting the bias code to a bias circuit of the integrated circuit.

Description

Technical Field

[0001] This invention relates to common mode correction in an analog-based receiver, and more particularly to common mode correction in an analog-based receiver using an analog-to-digital converter (ADC), which can correct for all input modes of the receiver and process-voltage-temperature (PVT) variations across all channels. Background Technology

[0002] The input common-mode voltage range of a circuit or component is the range of input voltages at which the circuit / component can operate correctly when the same signal is applied to both inputs. Receiver components (such as sense amplifiers (SA) and continuous-time linear equalizers (CTLEs)) operate at a rate that is a function of their common-mode voltage (VCM). The optimal VCM for these components is the input voltage at which they achieve their best performance.

[0003] However, due to variations in process-voltage-temperature (PVT), the input signals to these components may differ (relative to the optimal VCM). Furthermore, there may be offsets between the input signals themselves. Due to the inherent gain of the components, any common-mode offset in the amplifier's input signal will be amplified at the output, meaning subsequent components will receive input signals with even greater offsets.

[0004] Among the various existing related techniques for correcting or reducing offset in a receiver, U.S. Patent 10,931,381 teaches the removal of any differential offset in the input signal that may be due to an error in a reference voltage of the circuit. The corrected offset is then used to remove the offset in the output signal. However, the reference voltage itself is not corrected and may still vary due to PVT variations. Furthermore, a significant offset may still remain relative to the optimal common-mode voltage.

[0005] U.S. Patent 9,780,737 employs a digital method to correct any DC offset. As with the prior art described above, the reference voltage is not corrected, and the technique does not teach common-mode correction.

[0006] Please refer to Figure 1The figure shows a standard integrated circuit (IC) 100, as illustrated. This IC has multiple receive (Rx) channels, each coupled to multiple bias circuits. By design, each channel needs to operate in a similar manner to ensure only minor variations in signal speed. Even with corresponding bias circuits to correct for the offset of each channel, manufacturing variations mean that the DC operating point of each Rx channel may differ, resulting in different operating speeds. Furthermore, different types of IC chips may have different performance characteristics. For example, FF corner chips typically have low gain, while SS corner chips typically have high gain and narrow bandwidth. Therefore, even when offsets within the chip are corrected, performance differences still exist between different types of chips.

[0007] Therefore, it is necessary to correct the common-mode offset and PVT variation in the receiver, which can also correct the variation between different types of chips and between different channels. Summary of the Invention

[0008] Therefore, one object of the present invention is to provide a method for correcting receiver offset, wherein input variations of individual elements and speed variations between different channels can be corrected, and wherein the performance of the receiver can approach the performance of receivers in different types of chips.

[0009] A method for removing offset from an integrated circuit (IC) includes: determining multiple digital codes for multiple differential input voltages of an amplifier in a first receiving channel of the IC, the first receiving channel of the IC including multiple amplifiers; comparing the multiple digital codes with a digital code corresponding to an optimal common-mode voltage (VCM) of the IC; determining a bias code based on the comparison result to adjust the multiple differential input voltages to match the optimal common-mode voltage; and inputting the bias code into a bias circuit of the IC. These steps are repeated for each amplifier in the first receiving channel of the IC, and then repeated for all receiving channels of the IC.

[0010] The multiple digital codes of the multiple differential input voltages are determined by the following steps: inputting all differential input voltages to an analog probe acting as a multiplexer, and sequentially outputting each differential input voltage; inputting a first differential input voltage from the multiple differential input voltages to a first input of a comparator; sequentially inputting multiple reference voltages to a second input of the comparator; and setting the first differential input voltage as the current input reference voltage when the output of the comparator undergoes a level shift. Furthermore, inputting the first differential input voltage to the second input of the comparator; sequentially inputting the multiple reference voltages to the first input of the comparator; setting the second differential input voltage as the current input reference voltage when the output of the comparator undergoes a level shift; and finally setting the final differential input voltage to the average of the set first differential input voltage and the set second differential input voltage.

[0011] The multiple reference voltages are generated based on a resistor ladder and scaled according to a scaling factor. A bandgap voltage is input to the analog-to-digital converter to generate a scaling factor based on the offset in the analog-to-digital converter.

[0012] The step of determining the bias code for adjusting the plurality of differential input voltages to match the optimal common-mode voltage further includes: increasing the bias code when all the plurality of digital codes of the plurality of differential input voltages are less than the digital code of the optimal common-mode voltage; and decreasing the bias code when all the plurality of digital codes of the plurality of differential input voltages are greater than the digital code of the optimal common-mode voltage. The method further includes: determining a plurality of digital codes of a plurality of bias-adjusted differential input voltages of the amplifier located in the first receiving channel of the integrated circuit; comparing the plurality of digital codes of the plurality of bias-adjusted differential input voltages with the digital code corresponding to the optimal common-mode voltage of the integrated circuit; adjusting the bias code based on the comparison result; and inputting the adjusted bias code to the bias circuit of the integrated circuit.

[0013] The step of inputting the bias code into the bias circuit of the integrated circuit is performed either on-chip or off-chip.

[0014] Furthermore, an integrated circuit is disclosed, comprising multiple receiving channels, each receiving channel comprising multiple amplifiers, and an offset removal circuit comprising: an analog-to-digital converter (ADC) for determining multiple digital codes of multiple differential input voltages of an amplifier in a first receiving channel of the integrated circuit; and an adaptive algorithm circuit based on the ADC for comparing the multiple digital codes with a digital code corresponding to an optimal common-mode voltage of the integrated circuit, determining a bias code based on the comparison result to adjust the multiple differential input voltages to match the optimal common-mode voltage, and inputting the bias code to a bias circuit of the integrated circuit.

[0015] The analog-to-digital converter and the adaptive algorithm circuit based on the analog-to-digital converter determine the digital code of each pair of differential input voltages and determine the bias code of each of the plurality of amplifiers in the first receiving channel, further determining the digital code of each pair of differential input voltages and determining the bias code of all receiving channels of the integrated circuit.

[0016] The offset removal circuit also includes an analog probe, which is a multiplexer that receives all differential input voltages and sequentially outputs each differential input voltage. A first differential input voltage is input to a first input of the analog-to-digital converter (ADC), and multiple reference voltages are input to a second input of the ADC. When the output of the ADC changes, the first differential input voltage is set as the current input reference voltage. The first differential input voltage is then input to the second input of the ADC, and the multiple reference voltages are sequentially input to the first input. When the output of the ADC changes, the second differential input voltage is set as the current input reference voltage, and finally, the differential input voltage is set to the average of the set first and second differential input voltages.

[0017] The integrated circuit also includes a resistor ladder for generating the plurality of reference voltages. A bandgap voltage is input to the analog-to-digital converter to generate a scaling factor based on the offset in the analog-to-digital converter, and the plurality of reference voltages are scaled according to the scaling factor.

[0018] When all the digital codes of the multiple differential input voltages are less than the digital code of the optimal common-mode voltage, the adaptive algorithm circuit based on the analog-to-digital converter increases the bias code; and when all the digital codes of the multiple differential input voltages are greater than the digital code of the optimal common-mode voltage, the adaptive algorithm circuit based on the analog-to-digital converter decreases the bias code.

[0019] Bias control can be performed on-chip or off-chip. The bias code adjusts a source current or voltage of the amplifier. 5. The integrated circuit of claim 14, wherein the bias code adjusts the diode size of a current mirror of the amplifier, or the bias code adjusts a tail current source of the amplifier. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the receiving channel of an integrated circuit chip.

[0021] Figure 2A This is a schematic diagram of offset correction based on existing technology.

[0022] Figure 2B This is a schematic diagram of a correction offset according to an exemplary embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of an integrated circuit chip according to the present invention, which includes circuitry for generating common-mode voltage and generating digital codes.

[0024] Figure 4 This is a flowchart of the offset correction according to the present invention.

[0025] Figure 5 This is a flowchart for generating digital codes according to the present invention.

[0026] Figure 6 This is for Figure 3 The circuit diagram shown illustrates how an integrated circuit chip generates and adjusts a bias code.

[0027] Figure 7 This is a flowchart of generating and adjusting a bias code according to the present invention.

[0028] Figure 8 This is a schematic diagram of the bias correction method of the present invention.

[0029] Figure 9A This is a schematic diagram of a method for correcting bias voltage on-chip.

[0030] Figure 9B This is a schematic diagram of a method for correcting bias voltage off-chip.

[0031] [Symbol Explanation]

[0032] 100, 900, 970: Integrated Circuits (ICs)

[0033] 300: Receiver

[0034] 350: Simulated probe

[0035] 370: Analog-to-Digital Converter (ADC)

[0036] 390: Resistance ladder

[0037] 400, 500, 700: Flowchart

[0038] 410~470, 501~539, 701~733: Steps

[0039] 600: Circuit Diagram

[0040] 630: Continuous Time Linear Equalizer (CTLE)

[0041] 650:CTLE bias circuit

[0042] 800: Amplifier

[0043] 930: Digital Control Circuit

[0044] 950: Test board

[0045] 980: Post-Silicon Verification Environment

[0046] VCM_p, VCM_n: Differential input Detailed Implementation

[0047] As described above, existing technologies aim to remove the offset between the differential inputs of the receiver, but do not correct the offset between the differential inputs and the optimal common mode voltage (VCM) or correct the reference voltage. This means that any residual offset caused by process-voltage-temperature (PVT) variations will be amplified by each subsequent component. Therefore, this invention employs the following method: first, an optimal VCM is determined for each component within the receiver; the differential input of each component is compared to the optimal VCM; and an algorithm is determined to bias each differential input to match the optimal VCM. In this way, both differential offset and VCM offset can be corrected in a single step, and the two inputs are matched to the optimal VCM. Furthermore, this invention uses a bandgap voltage as a golden reference for the entire integrated circuit (IC) to correct the reference voltage.

[0048] Please refer to Figure 2A , Figure 2A This is a schematic diagram illustrating the correction of offset based on existing technology. For example... Figure 2A As shown in the left section, there is an offset between the differential inputs VCM_p and VCM_n. Additionally, there is an offset between these inputs and the optimal VCM. Figure 2A The middle section shows the effect of this differential offset on the swing quality. Figure 2A The right side shows the oscillating mass after correcting for differential offset.

[0049] Figure 2B This diagram illustrates a correction offset according to an embodiment of the present invention. Figure 2B The left side shows the relationship with Figure 2A The same differential offset and VCM offset, Figure 2B The middle section shows that each input moves towards the optimal VCM, which also corrects for differential offset. Figure 2B The right side shows the effect on the oscillating mass. (Compared to...) Figure 2A In comparison, it can be seen that the swing / gain is greater because the differential input operation is at or near the optimal VCM.

[0050] Please refer to Figure 3 , Figure 3 This is a receiver 300 according to an exemplary embodiment of the present invention. As shown, the receiver 300 includes multiple components, including a sense amplifier and a continuous-time linear equalizer (CTLE). As described in the prior art, any offset at the input of a component will be amplified at the output due to gain. Therefore, the present invention corrects the offset of all input signals by sequentially inputting all input signals to an analog probe 350, which can be implemented by a multiplexer. The analog probe 350 is coupled to an analog-to-digital converter (ADC) 370 to generate a digital code corresponding to each input signal. An ADC / resistor ladder 390 is illustrated to generate VCM and a reference voltage, although these voltages can be generated in various ways and the resistor ladder is only one example.

[0051] This VCM is the optimal VCM for each component operation. By generating a digital code for the optimal VCM, generating a digital code for the average of these input signals, and comparing the two, the offset can be determined, and an algorithm can be generated accordingly. This algorithm provides the corresponding component bias to remove the offset. The analog probe 350 is further used to first determine any inherent offset in the resistor ladder 390 and generate a scaling factor for correcting the offset.

[0052] Figure 4 A method 400 of the present invention is shown. First, a bandgap voltage is used to correct the ADC resistance gradient 390. Since this bandgap voltage is unaffected by PVT variations, it can be used as a gold reference for generating a scaling factor.

[0053] The optimal VCM is then input to an analog probe, generating a corresponding digital code, and the digital code of the optimal VCM is scaled using the digital code of the bandgap voltage. The analog probe can receive all differential inputs for each element and generate multiple corresponding digital codes, which are also scaled using a scaling factor. By comparing the multiple digital codes of each pair of differential inputs with the digital code of the optimal VCM, a bias code is generated for each element. These steps are then repeated for each channel of the receiver.

[0054] The steps of method 400 are as follows:

[0055] Step 410: Use a bandgap voltage on an analog probe to correct the internal offset of an ADC resistor ladder;

[0056] Step 420: Store a digital code of the bandgap voltage as a scaling factor;

[0057] Step 430: Input the desired common-mode voltage (VCM) to the analog probe;

[0058] Step 440: Use the scaling factor to generate the digital code for the VCM;

[0059] Step 450: Input the net analog voltage of an amplifier to the analog probe to generate a digital code, and adjust the bias code based on the difference between the digital code and the digital code of the VCM;

[0060] Step 460: Repeat step 450 for each major node of the receiver;

[0061] Step 470: Repeat the calibration process for all channels of this IC.

[0062] Figure 5 A flowchart 500 illustrates how a digital code is generated for each input signal. The ADC 350 includes a comparator that receives a first signal at a first input and a reference signal (generated by resistor ladder 390) at a second input. When the comparator's output undergoes a level shift (i.e., from "0" to "1" or from "1" to "0"), it means that the first input matches the reference signal, and the input is then switched to cancel any inherent offset. First, the first input is selected to receive the input signal, and the second input receives the reference signal, which is initially the lowest reference. The output is sampled multiple times, and when the output stabilizes, it is determined whether it equals the digit "0". If so, the digital code (reference code) is incremented, and the same comparison steps are performed. Once the output switches to the digit "1", the other input is tested to cancel any inherent offset between the ADC's two inputs. Once the digital code for each input is determined, their average is calculated to determine the final digital code output.

[0063] These steps are as follows:

[0064] Step 501: Process begins:

[0065] Step 503: Select the first input of the comparator;

[0066] Step 505: Set the other input of the comparator to the digital code corresponding to the lowest reference voltage;

[0067] Step 507: Wait;

[0068] Step 509: Sample the output of the comparator N times;

[0069] Step 511: Is the output stable? If yes, proceed to step 513; if no, proceed to step 517.

[0070] Step 513: Is the comparator output equal to "0"? If yes, proceed to step 515; if no, proceed to step 519.

[0071] Step 515: Set the digital code of the first input to the current input reference voltage;

[0072] Step 517: Add the numeric code and return to step 507;

[0073] Step 519: Set the final digital code of the first input to the current input reference voltage;

[0074] Step 521: Select the second input of the comparator;

[0075] Step 523: Set the other input of the comparator to the digital code corresponding to the lowest reference voltage;

[0076] Step 525: Wait 0.5 microseconds;

[0077] Step 527: Sample the comparator output 16 times at a rate of 0.1 microseconds;

[0078] Step 529: Is the output stable? If yes, proceed to step 531; if no, proceed to step 533.

[0079] Step 531: Is the comparator output equal to "1"? If yes, proceed to step 533; if no, proceed to step 537.

[0080] Step 533: Set the second input digital code to the current input reference voltage;

[0081] Step 535: Add the numeric code and return to step 525;

[0082] Step 537: Set the final digital code of the second input to the current input reference voltage;

[0083] Step 539: Determine the average of the final numeric codes of the first input and the second input.

[0084] Once all the input digital codes are determined, these codes can be compared with the digital codes of the optimal VCM to determine an algorithm that can be used to provide bias for each component. Figure 6 This is a circuit diagram 600 used to correct the bias of a single component. Each component is corrected individually, so that any remaining offset is not propagated to the next component. Figure 6 A CTLE 630 and a CTLE bias circuit 650 are shown. The input signal of the CTLE 630 is input to an analog probe 350, which is coupled to an ADC 370. The ADC 370 generates a digital code for the input signal of the CTLE 630, such as... Figure 5 As shown. The resulting code is input to the ADC-based adaptation algorithm circuit 610, which compares the differential code of the input signal with the digital code of the optimal VCM and generates subsequent code / algorithm for biasing CTLE. This algorithm shifts each differential input toward the optimal VCM, which also removes the differential offset between inputs.

[0085] Figure 7This is a detailed flowchart 700 of the above process. The up and down counters in the ADC 370 are initialized, the first input of the analog probe is turned on and allowed to settle, and the digital code of this input is as follows: Figure 5 The simulation probe's second input is then turned on and allowed to stabilize, generating digital codes. Each input code is compared to the optimal VCM. In a first step, it is determined whether both input codes are less than the optimal VCM. If so, it is determined whether any generated bias code is less than the maximum code; if not, meaning the bias code has reached its maximum value and the input cannot be increased further to approach the optimal VCM, the process ends. If the bias code is less than the maximum code, the bias code is incremented, which also causes the upcounter to increment.

[0086] If both input codes are greater than or equal to the reference code, then it is checked whether both codes are greater than the reference code. If so, it is checked whether the bias code is greater than zero. If the bias code is not greater than zero, it means that the input cannot be reduced further to approach the optimal VCM and the process ends. If the bias code is greater than zero, the bias code can be reduced / decreasing downwards, which also causes the down counter to increase.

[0087] After the increment or decrement counter increases (i.e., after the bias code increases or decreases), it is determined whether both the increment and decrement counters have reached their maximum counts; that is, whether the bias code has been incremented and decremented. This is to ensure that any noise region has been passed. If yes, the process ends; if not, the bias-corrected input signal is re-inputted to analog probe 350. When both digital codes are neither greater than nor less than the optimal VCM's digital code, process 700 determines whether the average of the two digital codes is less than the optimal VCM's digital code. If yes, this method determines whether the generated bias code is less than the maximum value; if not, this method determines whether the generated bias code is greater than zero.

[0088] The steps of method 700 are as follows:

[0089] Step 701: Process begins;

[0090] Step 703: Set both the increment counter and the decrement counter to zero;

[0091] Step 705: Enable the positive input of the amplifier probe;

[0092] Step 707: Wait for a settling time;

[0093] Step 709: Generate the numeric code for the positive input;

[0094] Step 711: Enable the negative input of the amplifier probe;

[0095] Step 713: Wait for the set time;

[0096] Step 715: Generate the numeric code for the negative input;

[0097] Step 717: Are both numeric codes less than the numeric code of the optimal VCM? If yes, proceed to step 723; if no, proceed to step 719.

[0098] Step 719: Are both numeric codes greater than the numeric code of the optimal VCM? If yes, proceed to step 727; if no, proceed to step 721.

[0099] Step 721: Is the average of the two numeric codes less than the numeric code of the optimal VCM? If yes, proceed to step 723; if no, proceed to step 727.

[0100] Step 723: Is the generated bias code less than the maximum bias code? If yes, proceed to step 725; if no, proceed to step 733.

[0101] Step 725: Perform bias control and increment the counter; proceed to step 731;

[0102] Step 727: Is the generated bias code greater than zero? If yes, proceed to step 729; if no, proceed to step 733.

[0103] Step 729: Perform bias control and increment the decrement counter;

[0104] Step 731: Have both the increment counter and the decrement counter reached their maximum values? If not, return to step 705; if yes, proceed to step 733.

[0105] Step 733: Process stopped.

[0106] Figure 8 This illustrates how bias control can be implemented within each component (e.g., within a sensing amplifier in circuit 300). Bias control can be implemented in several ways. In a first embodiment, bias control can be achieved by adjusting the source current or voltage of amplifier 800 (indicated by digit 1). In a second embodiment, bias control can be achieved by adjusting the target diode size of the current mirror of amplifier 800 (indicated by digit 2). In a third embodiment, bias control can be achieved by adjusting the target tail current source of amplifier 800 (indicated by digit 3).

[0107] Bias control can be performed on-chip or off-chip, as follows: Figure 9A as well as Figure 9B As shown. Figure 9A As shown, the digital control circuit 930 is coupled to all receive channels of IC 900. Each receive channel contains an analog probe, the operation of which is detailed above. The common-mode (CMM) channel also contains an ADC coupled to all analog probes and provides the comparison result to the digital control circuit 930, which can then provide a bias voltage to each channel.

[0108] Figure 9B The IC 970 is shown and coupled to a post-silicon verification environment 980. By placing the two components on a test board 950, the ADC in the common-mode channel can output the comparison result to the post-silicon verification environment 980 via a debug port, and then input the bias control to each channel.

[0109] In summary, the method and circuitry of this invention provide a means for bias control in a receiver that can reduce offset relative to the optimal common-mode voltage. This invention can also correct offsets in all channels of the receiver and further correct offsets in different chips.

[0110] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A method for removing the offset of an integrated circuit (IC), comprising: Multiple digital codes determine multiple differential input voltages of amplifiers in the first receiving channel of the integrated circuit, which contains multiple amplifiers; The multiple digital codes are compared with the digital codes corresponding to the optimal common mode voltage (VCM) of the integrated circuit; Based on the comparison results, a bias code is determined to adjust the multiple differential input voltages to match the optimal common-mode voltage; as well as Input the bias code into the bias circuit of the integrated circuit.

2. The method of claim 1, further comprising: For each of the plurality of amplifiers in the first receiving channel of the integrated circuit, all steps of the method are repeated.

3. The method of claim 2, further comprising: Repeat all steps of this method for all receiving channels of the integrated circuit.

4. The method of claim 1, wherein the plurality of digital codes of the plurality of differential input voltages are determined by the following steps: All differential input voltages are input to the analog probes that act as a multiplexer, and each differential input voltage is output sequentially. The first differential input voltage from the plurality of differential input voltages is input to the first input of the comparator; Multiple reference voltages are sequentially input to the second input of the comparator; as well as When the output of the comparator undergoes a level shift, the first differential input voltage is set to the current input reference voltage.

5. The method of claim 4, further comprising: The first differential input voltage is input to the second input of the comparator; The multiple reference voltages are sequentially input to the first input of the comparator; When the comparator's output changes, the second differential input voltage is set to the current input reference voltage; and The final differential input voltage is set to the average of the set first differential input voltage and the set second differential input voltage.

6. The method of claim 4, wherein the plurality of reference voltages are generated based on a resistor ladder.

7. The method of claim 6, further comprising: Input the bandgap voltage to the comparator; A scaling factor is generated based on the offset in the comparator; and The multiple reference voltages are scaled according to the scaling factor.

8. The method of claim 1, wherein the step of determining the bias code for adjusting the plurality of differential input voltages to match the optimal common-mode voltage further comprises: When all the digital codes of the multiple differential input voltages are less than the digital code of the optimal common-mode voltage, the bias code is increased; and When all the digital codes of the multiple differential input voltages are greater than the digital code of the optimal common-mode voltage, the bias code is reduced. The method also includes: Multiple digital codes determine the multiple bias-adjusted differential input voltages of the amplifier located in the first receiving channel of the integrated circuit; The multiple digital codes of the multiple bias-adjusted differential input voltages are compared with the digital code corresponding to the optimal common-mode voltage of the integrated circuit; Adjust the bias code based on the comparison results; as well as The adjusted bias code is input into the bias circuit of the integrated circuit.

9. The method of claim 3, wherein the step of inputting the bias code into the bias circuit of the integrated circuit is performed on-chip.

10. The method of claim 3, wherein the step of inputting the bias code into the bias circuit of the integrated circuit is performed off-chip.

11. The method of claim 1, wherein the bias code adjusts the source current or voltage of the amplifier.

12. The method of claim 1, wherein the bias code adjusts the diode size of the current mirror of the amplifier.

13. The method of claim 1, wherein the bias code adjusts the tail current source of the amplifier.

14. An integrated circuit (IC) comprising multiple receiving channels, each receiving channel comprising multiple amplifiers, the integrated circuit further comprising an offset removal circuit, the offset removal circuit comprising: An analog-to-digital converter (ADC) is used to determine multiple digital codes of the differential input voltages of the amplifier in the first receiving channel of the integrated circuit; and An adaptive algorithm circuit based on an analog-to-digital converter is used to compare the multiple digital codes with the digital codes corresponding to the optimal common mode voltage (VCM) of the integrated circuit. Based on the comparison results, a bias code is determined to adjust the multiple differential input voltages to match the optimal common mode voltage, and the bias code is input to the bias circuit of the integrated circuit.

15. The integrated circuit of claim 14, wherein the analog-to-digital converter and the adaptive algorithm circuit based on the analog-to-digital converter determine the digital code for each pair of differential input voltages and determine the bias code for each of the plurality of amplifiers in the first receiving channel.

16. The integrated circuit of claim 15, wherein the analog-to-digital converter and the adaptive algorithm circuit based on the analog-to-digital converter determine the digital code for each pair of differential input voltages and determine the bias code for all receiving channels of the integrated circuit.

17. The integrated circuit of claim 14, wherein the offset removal circuit further comprises an analog probe, the analog probe being a multiplexer that receives all differential input voltages and sequentially outputs each differential input voltage; The first differential input voltage of the plurality of differential input voltages is input to the first input of the analog-to-digital converter, the plurality of reference voltages are input to the second input of the analog-to-digital converter, and when the output of the analog-to-digital converter is converted, the first differential input voltage is set as the current input reference voltage.

18. The integrated circuit of claim 17, wherein the first differential input voltage is input to the second input of the analog-to-digital converter, the plurality of reference voltages are sequentially input to the first input of the analog-to-digital converter, and when the output of the analog-to-digital converter is switched, the second differential input voltage is set to the current input reference voltage, and the final differential input voltage is set to the average of the set first differential input voltage and the set second differential input voltage.

19. The integrated circuit of claim 17, further comprising: A resistor ladder is used to generate these multiple reference voltages.

20. The integrated circuit of claim 19, wherein the bandgap voltage is input to the analog-to-digital converter to generate a scaling factor based on an offset in the analog-to-digital converter, and the plurality of reference voltages are scaled based on the scaling factor.

21. The integrated circuit of claim 14, wherein when all the digital codes of the plurality of differential input voltages are less than the digital code of the optimal common-mode voltage, the adaptive algorithm circuit based on the analog-to-digital converter increases the bias code, and when all the digital codes of the plurality of differential input voltages are greater than the digital code of the optimal common-mode voltage, the adaptive algorithm circuit based on the analog-to-digital converter decreases the bias code.

22. The integrated circuit of claim 16, wherein the bias control is performed on-chip.

23. The integrated circuit of claim 16, wherein the bias control is performed off-chip.

24. The integrated circuit of claim 14, wherein the bias code adjusts the source current or voltage of the amplifier.

25. The integrated circuit of claim 14, wherein the bias code adjusts the diode size of the current mirror of the amplifier.

26. The integrated circuit of claim 14, wherein the bias code adjusts the tail current source of the amplifier.

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