A dynamic latch

Abstract

The application relates to the field of integrated circuits, and discloses a dynamic latch, which can control the working level of NMOS tubes and PMOS tubes respectively, improves the performance and working speed of the dynamic latch, and enables the whole circuit to work under a lower power supply voltage. The dynamic latch comprises an amplification stage, a first regeneration stage and a second regeneration stage. Each regeneration stage comprises two cross-coupled inverters, and each inverter comprises one NMOS tube and one PMOS tube. The output of the amplification stage is coupled to the input of the first regeneration stage and the second regeneration stage, the output of the first regeneration stage provides bias and signals for the NMOS tube of the second regeneration stage, and the output of the second regeneration stage provides bias and signals for the PMOS tube of the first regeneration stage.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and specifically to a dynamic latch. Background Technology

[0002] Strongarm latches are widely used in high-sensitivity, high-precision comparators, amplifiers, or latches. Their advantages include: no static power consumption, direct output of 0 / 1 signals for easy subsequent digital processing and integration, and the ability to achieve high-gain amplification and high-precision comparison functionality.

[0003] Current dynamic latches typically employ an amplification stage and a latching regeneration stage to sample and amplify the input signal. For the inverter circuit in the regeneration stage, Vgsn + |Vgsp| = Vdd, where Vgsn is the gate-to-source voltage of the NMOS transistor, Vgsp is the gate-to-source voltage of the PMOS transistor, and Vdd is the power supply voltage. Therefore, when Vdd is low, or the threshold voltage of the MOSFET is high, the overdrive voltages of the NMOS transistor (Vgsn - Vthn) and the PMOS transistor (|Vgsp - Vthp|) are both relatively small, where Vthn is the threshold voltage of the NMOS transistor and Vthp is the threshold voltage of the PMOS transistor. Consequently, the on-resistance of the NMOS and PMOS transistors in the inverter is very high, resulting in a very slow inverter speed in the regeneration stage. Therefore, the time for the output to be amplified to the 0 / 1 level is very long, limiting the dynamic latch's operation to large signal inputs or low-speed applications. Summary of the Invention

[0004] The purpose of this application is to provide a dynamic latch that can reduce the on-resistance of NMOS and PMOS transistors, thereby improving the performance and operating speed of the dynamic latch.

[0005] This application discloses a dynamic latch, including: an amplification stage, a first regeneration stage, and a second regeneration stage;

[0006] Each of the regenerative stages includes two cross-coupled inverters, each of which includes one NMOS transistor and one PMOS transistor;

[0007] The output of the amplification stage is coupled to the inputs of the first regenerator stage and the second regenerator stage;

[0008] The output of the first regenerative stage provides bias and signal to the NMOS transistor of the second regenerative stage, and the output of the second regenerative stage provides bias and signal to the PMOS transistor of the first regenerative stage.

[0009] In a preferred embodiment, the first regeneration stage includes PMOS transistors M102, M104, M105 and M106, and NMOS transistors M101 and M103; the second regeneration stage includes PMOS transistors M202 and M204, and NMOS transistors M201, M203, M205 and M206.

[0010] The output of the amplification stage is coupled to the gates of PMOS transistors M105 and M106 in the first regeneration stage and the gates of NMOS transistors M205 and M206 in the second regeneration stage, respectively; the drains of PMOS transistors M105 and M102, the gate of PMOS transistor M104, and the drain of NMOS transistor M101 are coupled at the first node P1; the gate of PMOS transistor M102, the drains of PMOS transistors M104 and M106, and the drain of NMOS transistor M103 are coupled at the second node P2.

[0011] The drain of PMOS transistor M202, the drains of NMOS transistors M205 and M201, and the gate of NMOS transistor M203 are coupled at the third node P3, and the drain of PMOS transistor M204, the drains of NMOS transistors M203 and M206, and the gate of NMOS transistor M201 are coupled at the fourth node P4.

[0012] In a preferred embodiment, the drain of the PMOS transistor M102 is coupled to the gate of the PMOS transistor M204; the drain of the PMOS transistor M104 is coupled to the gate of the PMOS transistor M202.

[0013] The gate of the NMOS transistor M101 is coupled to the drain of the NMOS transistor M203, and the gate of the NMOS transistor M103 is coupled to the drain of the PMOS transistor M201.

[0014] In a preferred embodiment, the output of the first regenerator or the second regenerator is used as the output of the dynamic latch.

[0015] In a preferred embodiment, the sources of the NMOS transistors M101, M103, M205, M201, M203, and M206 are grounded or grounded through a switch.

[0016] In a preferred embodiment, the sources of the PMOS transistors M105, M102, M104, M106, M202, and M204 are coupled to the power supply voltage or are coupled to the power supply voltage through a switch.

[0017] In a preferred embodiment, the output of the amplification stage includes a forward differential output and a reverse differential output;

[0018] The forward differential output is coupled to the gate of the PMOS transistor M105 and the gate of the NMOS transistor M206, and the reverse differential output is coupled to the gate of the PMOS transistor M106 and the gate of the NMOS transistor M205.

[0019] In a preferred embodiment, the amplification stage includes NMOS transistors M3, M4, and M5, and PMOS transistors M6 and M7;

[0020] The gates of NMOS transistors M4 and M5 are connected to the positive and negative terminals of the input, respectively. The sources of NMOS transistors M4 and M5 are coupled to the drain of NMOS transistor M3. The gate of NMOS transistor M3 is connected to the clock signal, and the source of NMOS transistor M3 is grounded. The drains of NMOS transistors M4 and M5 are coupled to the drains of PMOS transistors M6 and M7. The gates of PMOS transistors M6 and M7 are connected to the clock signal, and the sources of PMOS transistors M6 and M7 are coupled to the power supply voltage.

[0021] In a preferred embodiment, a PMOS transistor M8 is provided between the source of the PMOS transistors M105, M102, M104, M106, M202, and M204 and the power supply voltage.

[0022] In a preferred embodiment, the sources of the PMOS transistors M105, M102, M104, M106, M202, and M204 are coupled to the drain of the PMOS transistor M8, the source of the PMOS transistor M8 is coupled to the power supply voltage, and the gate of the PMOS transistor M8 is connected to an inverted clock signal.

[0023] In this embodiment, a two-stage regenerative stage circuit is used. Through signal coupling, the NMOS transistor and PMOS transistor are biased respectively, which can control the operating level of the NMOS transistor and PMOS transistor respectively, and ensure that there is an input signal on both the NMOS transistor and PMOS transistor at the same time. This reduces the on-resistance of the NMOS transistor and PMOS transistor, thereby improving the performance and operating speed of the dynamic latch. In addition, it can also enable the entire circuit to operate at a lower power supply voltage.

[0024] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a circuit structure according to an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of a circuit structure according to another embodiment of this application;

[0027] Figure 3 This is a schematic diagram of a circuit structure according to yet another embodiment of this application. Detailed Implementation

[0028] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0029] Explanation of terms:

[0030] NMOS transistor: NMOS stands for N-Metal-Oxide-Semiconductor, which is a type of field-effect transistor that can be widely used in analog and digital circuits.

[0031] PMOS transistor: PMOS stands for Positive channel Metal Oxide Semiconductor, which means P-type metal oxide semiconductor field-effect transistor.

[0032] The specific implementation of the present invention will be described in detail below with reference to specific embodiments and accompanying drawings:

[0033] Figure 1 The diagram shows a circuit structure of a dynamic latch, which includes an amplification stage, a first regenerative stage, and a second regenerative stage. Each regenerative stage includes two cross-coupled inverters, each of which includes one NMOS transistor and one PMOS transistor. The output of the amplification stage is coupled to the inputs of the first and second regenerative stages. The output of the first regenerative stage provides bias and signal to the NMOS transistor of the second regenerative stage, and the output of the second regenerative stage provides bias and signal to the PMOS transistor of the first regenerative stage. The output of either the first or second regenerative stage can be selected as the output of the dynamic latch.

[0034] The first regeneration stage includes PMOS transistors M102, M104, M105, and M106, and NMOS transistors M101 and M103. The second regeneration stage includes PMOS transistors M202 and M204, and NMOS transistors M201, M203, M205, and M206. Optionally, in another embodiment, M105 and M106 can also be NMOS transistors, and M205 and M206 can also be PMOS transistors.

[0035] The output of the amplification stage is coupled to the gates of PMOS transistors M105 and M106 in the first regeneration stage and the gates of NMOS transistors M205 and M206 in the second regeneration stage, respectively. The drains of PMOS transistors M105 and M102, the gate of PMOS transistor M104, and the drain of NMOS transistor M101 are coupled at the first node P1. The gate of PMOS transistor M102, the drains of PMOS transistors M104 and M106, and the drain of NMOS transistor M103 are coupled at the second node P2. The drains of PMOS transistor M202, the drains of NMOS transistors M205 and M201, and the gate of NMOS transistor M203 are coupled at the third node P3. The drains of PMOS transistors M204, M203, and M206, and the gate of NMOS transistor M201 are coupled at the fourth node P4. The drain of PMOS transistor M102 is coupled to the gate of PMOS transistor M204, and the drain of PMOS transistor M104 is coupled to the gate of PMOS transistor M202. The gate of NMOS transistor M101 is coupled to the drain of NMOS transistor M203, and the gate of NMOS transistor M103 is coupled to the drain of PMOS transistor M201. The sources of NMOS transistors M101, M103, M205, M201, M203, and M206 are grounded or grounded through a switch. The sources of PMOS transistors M105, M102, M104, M106, M202, and M204 are coupled to the power supply voltage or coupled to the power supply voltage through a switch.

[0036] The output of the amplifier stage includes a forward differential output and a reverse differential output. The forward differential output is coupled to the gate of PMOS transistor M105 and the gate of NMOS transistor M206, and the reverse differential output is coupled to the gate of PMOS transistor M106 and the gate of NMOS transistor M205.

[0037] The amplification stage may include NMOS transistors M3, M4, and M5, and PMOS transistors M6 and M7. The gates of NMOS transistors M4 and M5 are connected to the positive and negative terminals of the input, respectively. The sources of NMOS transistors M4 and M5 are coupled to the drain of NMOS transistor M3. The gate of NMOS transistor M3 is connected to the clock signal, and the source of NMOS transistor M3 is grounded. The drains of NMOS transistors M4 and M5 are coupled to the drains of PMOS transistors M6 and M7. The gates of PMOS transistors M6 and M7 are connected to the clock signal, and the sources of PMOS transistors M6 and M7 are coupled to the power supply voltage.

[0038] Optionally, a PMOS transistor M8 can be provided between the source of PMOS transistors M105, M102, M104, M106, M202, and M204 and the power supply voltage. The source of PMOS transistors M105, M102, M104, M106, M202, and M204 is coupled to the drain of PMOS transistor M8, the source of PMOS transistor M8 is coupled to the power supply voltage, and the gate of PMOS transistor M8 is connected to the inverting clock signal.

[0039] An intermediate stage can be added between the amplification stage and the regeneration stage to drive the amplification. Multiple regeneration stages can share a single amplification stage, or separate amplification stages can be used to drive the regeneration stages respectively.

[0040] Figure 1 The circuit structure can also have other variations. For example... Figure 2 and Figure 3 Two variations of the embodiments are shown. Figure 2 Two amplification stages are used, each coupled to one of the two regenerator stages.

[0041] Figure 2 and Figure 3 The amplification stage can be implemented in various ways, and the connection between the amplification stage and the regenerator stage can also be implemented in various ways.

[0042] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0043] In this application, the terms “connection,” “coupling,” or any variations thereof mean any direct or indirect connection or coupling between elements, and may encompass the presence of an intermediate element between two elements that are “connected” or “coupled” together via the intermediate element. Coupling and / or connection between elements can be physical, logical, or a combination thereof. As adopted herein, elements can be “connected” or “coupled” together by using one or more wires, cables, and / or printed circuits, and by using electromagnetic energy. Electromagnetic energy can have wavelengths in the radio frequency region, microwave region, and / or light (both visible and invisible) region. The examples above are non-limiting and non-exhaustive.

[0044] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A dynamic latch, characterized in that, include: Amplification stage, first regeneration stage, and second regeneration stage; Each of the regeneration stages includes two cross-coupled inverters, each of which includes one NMOS transistor and one PMOS transistor; the first regeneration stage includes PMOS transistors M102, M104, M105, and M106, and NMOS transistors M101 and M103; the second regeneration stage includes PMOS transistors M202 and M204, and NMOS transistors M201, M203, M205, and M206; The output of the amplification stage includes a forward differential output and a reverse differential output; the forward differential output is coupled to the gate of the PMOS transistor M105 and the gate of the NMOS transistor M206, and the reverse differential output is coupled to the gate of the PMOS transistor M106 and the gate of the NMOS transistor M205. The output of the amplification stage is coupled to the inputs of the first regenerator stage and the second regenerator stage; The output of the first regenerative stage provides bias and signal to the PMOS transistor of the second regenerative stage, and the output of the second regenerative stage provides bias and signal to the NMOS transistor of the first regenerative stage. The drain of PMOS transistor M102 is coupled to the gate of PMOS transistor M204; the drain of PMOS transistor M104 is coupled to the gate of PMOS transistor M202; the gate of NMOS transistor M101 is coupled to the drain of NMOS transistor M203; and the gate of NMOS transistor M103 is coupled to the drain of PMOS transistor M201. The drains of PMOS transistors M105 and M102, the gate of PMOS transistor M104, and the drain of NMOS transistor M101 are coupled at the first node P1; the gate of PMOS transistor M102, the drains of PMOS transistors M104 and M106, and the drain of NMOS transistor M103 are coupled at the second node P2; the drains of PMOS transistor M202, the drains of NMOS transistors M205 and M201, and the gate of NMOS transistor M203 are coupled at the third node P3; and the drains of PMOS transistor M204, the drains of NMOS transistors M203 and M206, and the gate of NMOS transistor M201 are coupled at the fourth node P4.

2. The dynamic latch as described in claim 1, characterized in that, The output of the first regeneration stage or the second regeneration stage serves as the output of the dynamic latch.

3. The dynamic latch as described in claim 1, characterized in that, The sources of the NMOS transistors M101, M103, M205, M201, M203, and M206 are grounded or grounded through a switch.

4. The dynamic latch as described in claim 1, characterized in that, The sources of the PMOS transistors M105, M102, M104, M106, M202, and M204 are connected to the power supply voltage or connected to the power supply voltage via a switch.

5. The dynamic latch as described in claim 1, characterized in that, The amplification stage includes NMOS transistors M3, M4, and M5, and PMOS transistors M6 and M7; The gates of NMOS transistors M4 and M5 are connected to the positive and negative terminals of the input, respectively. The sources of NMOS transistors M4 and M5 are coupled to the drain of NMOS transistor M3. The gate of NMOS transistor M3 is connected to the clock signal, and the source of NMOS transistor M3 is grounded. The drains of NMOS transistors M4 and M5 are coupled to the drains of PMOS transistors M6 and M7. The gates of PMOS transistors M6 and M7 are connected to the clock signal, and the sources of PMOS transistors M6 and M7 are coupled to the power supply voltage.

6. The dynamic latch as described in claim 1, characterized in that, A PMOS transistor M8 is provided between the source of the PMOS transistors M105, M102, M104, M106, M202, and M204 and the power supply voltage.

7. The dynamic latch as described in claim 6, characterized in that, The sources of PMOS transistors M105, M102, M104, M106, M202, and M204 are coupled to the drain of PMOS transistor M8, the source of PMOS transistor M8 is coupled to the power supply voltage, and the gate of PMOS transistor M8 is connected to an inverted clock signal.

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