Ethercat slave device and electronic equipment

Abstract

The embodiment of the application discloses an EtherCAT slave station device and electronic equipment, which comprises a slave station control chip, at least two PHY chips, network transformers corresponding to the PHY chips one by one, at least one first signal pin and an outer shell. The first end of the outer shell is provided with network interfaces which are the same in number as the network transformers, and the second end of the outer shell is provided with at least one pin through hole. The slave station control chip, the at least two PHY chips and the at least two network transformers are arranged in the outer shell. Each network interface is connected with a corresponding network transformer, each network transformer is connected with a corresponding PHY chip, and each PHY chip is connected with the first end of the slave station control chip. The second end of the slave station control chip is connected with the at least one first signal pin, and the first signal pin extends to the outside of the outer shell through the corresponding pin through hole, so that the problem of high cost of designing the EtherCAT slave station device can be solved, the cost investment of designing the EtherCAT slave station device is reduced, and the working efficiency of designing the EtherCAT slave station device is improved.

Description

Technical Field

[0001] This application relates to the field of Ethernet bus communication technology, and in particular to an EtherCAT slave device and electronic equipment. Background Technology

[0002] With the advancement of electronic and communication technologies, industrial automation control has gradually shifted from the traditional point-to-point centralized control mode to a networked fieldbus communication control mode. Fieldbus control systems integrate control and monitoring equipment in the industrial field into a communication network via serial signals, offering advantages such as full digital capabilities, bidirectional communication, and serial multi-node functionality. Fieldbus communication systems based on industrial Ethernet can achieve high-speed and low-jitter control at 100 Mbps Ethernet speeds and are widely used in various high-speed, high-precision operating control systems.

[0003] EtherCAT is a fieldbus protocol based on industrial Ethernet. Due to its wide applicability, short refresh cycle, and good synchronization performance, it has been widely recognized and applied in various control systems. An EtherCAT system is a high-performance industrial Ethernet fieldbus system. A complete EtherCAT system consists of one EtherCAT master device and at least one EtherCAT slave device. The core of the EtherCAT slave device has three layers: the physical layer, the data link layer, and the application layer. The physical layer is implemented using a standard Ethernet PHY chip, the data link layer is implemented using a slave control chip, and the application layer is implemented using a microcontroller.

[0004] Existing EtherCAT slave devices require separate peripheral circuits built on a microcontroller for the application layer and on a slave control chip for the data link layer. Therefore, building an EtherCAT slave device necessitates considering the communication methods between the slave control chip and the microcontroller, the communication methods between the slave controller and the PHY chip, and the configuration of the slave control chip, resulting in significant financial costs. Furthermore, configuration errors pose a risk of requiring redesign, greatly extending the development cycle of EtherCAT slave devices, leading to low development efficiency and substantial labor costs. Summary of the Invention

[0005] This application provides an EtherCAT slave device and electronic device, which can solve the problem of high design cost of EtherCAT slave devices, reduce the cost investment in designing EtherCAT slave devices, and improve the work efficiency of designing EtherCAT slave devices.

[0006] In a first aspect, embodiments of this application provide an EtherCAT slave device, including a slave control chip, at least two PHY chips, a network transformer corresponding to each of the PHY chips, at least one first signal header, and a housing;

[0007] The first end of the housing is provided with the same number of network interfaces as the network transformer, and the second end of the housing is provided with at least one pin header through hole;

[0008] The slave control chip, at least two PHY chips, and at least two network transformers are housed within the housing.

[0009] Each network interface is connected to a corresponding network transformer, each network transformer is connected to a corresponding PHY chip, and each PHY chip is connected to the first end of the slave control chip.

[0010] The second end of the slave control chip is connected to at least one first signal pin header, and the first signal pin header extends out of the housing through a corresponding pin header through-hole.

[0011] Furthermore, the first signal header includes a first SPI signal header, a first reset signal header, a first distributed clock signal header, and a first EEPROM signal header.

[0012] Furthermore, the slave control chip, the PHY chip, and the second signal header are placed on the first circuit board, and the network transformer is placed on the second circuit board;

[0013] Each network transformer is connected to the corresponding PHY chip via a second signal header.

[0014] Furthermore, the second signal header includes a second SPI signal header, a second reset signal header, a second distributed clock signal header, a second EEPROM signal header, and a MDI signal header.

[0015] Furthermore, the first end of the slave control chip is provided with an MII and / or MD IO interface;

[0016] Each of the PHY chips is connected to the MII and / or MD IO interface corresponding to the first end of the slave control chip.

[0017] Furthermore, the slave control chip is an AS IC integrated chip.

[0018] Furthermore, each network interface is connected to the corresponding network transformer via an MD I signal line.

[0019] Furthermore, the network interface is an RJ45 interface.

[0020] Furthermore, the device also includes a network connection indicator and a data transmission indicator;

[0021] Both the network connection indicator and the data transmission indicator are mounted on the second circuit board and connected to the PHY chip.

[0022] The outer casing has light outlets corresponding to the network connection indicator and the data transmission indicator.

[0023] This application also provides an electronic device, including the EtherCAT slave device and electronic device described above.

[0024] This embodiment of the application provides network interfaces at the first end of the housing, the same number as the number of network transformers, and at least one pin header through-hole at the second end of the housing. The slave control chip, at least two PHY chips, and at least two network transformers are housed within the housing. Each network interface is connected to its corresponding network transformer, and each network transformer is connected to its corresponding PHY chip. Each PHY chip is connected to the first end of the slave control chip. This eliminates the need to consider the circuit design between the slave control chip and the PHY chip, as well as the related hardware configuration of the slave control chip, when designing an EtherCAT slave device. This reduces the design difficulty and cost of EtherCAT slave devices, shortens the product development cycle, and improves the efficiency of designing EtherCAT slave devices. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of an EtherCAT slave device provided in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the housing of an EtherCAT slave device provided in an embodiment of this application;

[0027] Figure 3 This is a schematic diagram illustrating the connection between an EtherCAT slave device and an external control chip, as provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0029] EtherCAT is a fieldbus protocol based on industrial Ethernet. Due to its wide applicability, short refresh cycle, and good synchronization performance, it has been widely recognized and applied in various control systems. An EtherCAT system is a high-performance industrial Ethernet fieldbus system. A complete EtherCAT system consists of one EtherCAT master device and at least one EtherCAT slave device. The core of the EtherCAT slave device has three layers: the physical layer, the data link layer, and the application layer. The physical layer is implemented using a standard Ethernet PHY chip, the data link layer is implemented using a slave control chip, and the application layer is implemented using a microcontroller.

[0030] Figure 1 This is a schematic diagram of the structure of an EtherCAT slave device provided in an embodiment of this application. Figure 2 This is a schematic diagram of the housing of an EtherCAT slave device provided in an embodiment of this application, with reference to... Figure 1 and Figure 2 The EtherCAT slave device 10 includes a slave control chip 11, at least two PHY chips 12, network transformers 13 corresponding to each PHY chip 12, at least one first signal header 14, and a housing 15. The first end of the housing 15 has network interfaces 16, the same number as the network transformers 13, and the second end of the housing 15 has at least one pin header through-hole. The slave control chip 11, at least two PHY chips 12, and at least two network transformers 13 are housed within the housing 15. Each network interface 16 is connected to its corresponding network transformer 13, and each network transformer 13 is connected to its corresponding PHY chip 12. Each PHY chip 12 is connected to the first end of the slave control chip 11. Each network interface 16 is connected to its corresponding network transformer 13 via an MII signal line. The first end of the slave control chip 11 has an MII and / or MDIO interface, and each PHY chip 12 is connected to the corresponding MII and / or MDIO interface at the first end of the slave control chip 11. The second end of the slave control chip 11 is connected to at least one first signal pin header 14, which extends to the outside of the housing 15 through a corresponding pin header through hole.

[0031] It should be noted that the slave control chip 11 can be an AS IC integrated chip.

[0032] It should be noted that network interface 16 can be an RJ45 interface.

[0033] By providing network interfaces 16 at the first end of the housing 15 in the same number as the network transformers 13, and at least one pin header through-hole at the second end of the housing 15, the slave control chip 11, at least two PHY chips 12, and at least two network transformers 13 are placed inside the housing 15. Each network interface 16 is connected to the corresponding network transformer 13, and each network transformer 13 is connected to the corresponding PHY chip 12. Each PHY chip 12 is connected to the first end of the slave control chip 11. This eliminates the need to consider the circuit design between the slave control chip 11 and the PHY chip 12, as well as the related hardware configuration of the slave control chip 11, when designing the EtherCAT slave device 10. This reduces the design difficulty and cost of the EtherCAT slave device 10, shortens the product development cycle, and improves the working efficiency of the EtherCAT slave device 10. In addition, the housing 15 makes the EtherCAT slave device 10 modular, improves the electromagnetic interference immunity of the internal circuit, and suppresses the electromagnetic interference radiation of the internal circuit to the outside, thereby improving the safety of the EtherCAT slave device 10.

[0034] Reference Figure 1 and Figure 2 The first signal header 14 includes a first SP1 signal header, a first reset signal header, a first distributed clock signal header, and a first EEPROM signal header.

[0035] The slave control chip 11, PHY chip 12, and second signal header 17 are located on the first circuit board PCB1, and the network transformer 13 is located on the second circuit board PCB2. Each network transformer 13 is connected to the corresponding PHY chip 12 through the second signal header 17. The second signal header 17 includes a second SPI signal header, a second reset signal header, a second distributed clock signal header, a second EEPROM signal header, and a MDI signal header.

[0036] In one embodiment, the EtherCAT slave device 10 further includes a network connection indicator (not shown) and a data transmission indicator (not shown). Both the network connection indicator and the data transmission indicator are mounted on the second circuit board PCB2 and connected to the PHY chip 12. The housing 15 has light outlets corresponding to the network connection indicator and the data transmission indicator.

[0037] In one embodiment, the EtherCAT slave device 10 further includes a network connection indicator (not shown) and a data transmission indicator (not shown). Both the network connection indicator and the data transmission indicator are mounted on the first circuit board PCB1 and connected to the PHY chip 12. The housing 15 has light outlets corresponding to the network connection indicator and the data transmission indicator.

[0038] Figure 3 This is a schematic diagram illustrating the connection between an EtherCAT slave device and an external control chip, as provided in an embodiment of this application. Figure 3 The EtherCAT slave device 10 is connected to the external control chip 20 via a first signal header 14, which includes a first SPI signal header, a first reset signal header, a first distributed clock signal header, and a first EEPROM signal header. The slave control chip 11, network transformer 13, and PHY chip 12 are integrated to form the EtherCAT slave device 10, achieving complete encapsulation from the data link layer to the physical layer. The EtherCAT slave device 10 internally completes all hardware design from the data link layer to the physical layer. When developing and designing using the EtherCAT slave device 10 provided in this application embodiment, there is no need to consider the hardware design issues from the data link layer to the physical layer; only the connection between the external control chip 20 and the EtherCAT slave device 10 needs to be addressed. The external control chip 20 and the EtherCAT slave device 10 are connected via a first signal header 14. The first signal header 14 includes a first SPI signal header, a first reset signal header, a first distributed clock signal header, and a first EEPROM signal header. The first SPI signal header includes an SPI communication clock header, an SPI communication chip select header, an SPI communication data input header, an SPI communication data output header, and an SPI communication data interrupt header. Therefore, when using the EtherCAT slave device 10 provided in this embodiment for development and design, the design difficulty is greatly reduced, the probability of design errors is lowered, and the product development cycle is shortened.

[0039] In one embodiment, the EtherCAT slave device 10 is highly integrated, with dimensions of only 38.5*32.42*13.5 (mm), which reduces the size of the circuit board (PCB) and thus lowers material costs. Furthermore, the EtherCAT slave device 10 is encased in a metal shielding shell 15, which improves its electromagnetic interference immunity and reduces external electromagnetic interference, thereby enhancing its safety.

[0040] As described above, by providing network interfaces at the first end of the housing equal to the number of network transformers, and at least one pin header through-hole at the second end of the housing, the slave control chip, at least two PHY chips, and at least two network transformers are housed within the housing. Each network interface is connected to its corresponding network transformer, each network transformer is connected to its corresponding PHY chip, and each PHY chip is connected to the first end of the slave control chip. This eliminates the need to consider the circuit design between the slave control chip and the PHY chip, as well as the related hardware configuration of the slave control chip, when designing an EtherCAT slave device. This reduces the design difficulty and cost of EtherCAT slave devices, shortens the product development cycle, and improves the efficiency of EtherCAT slave device design. Furthermore, the modular design of the EtherCAT slave device through the housing improves the electromagnetic interference immunity of the internal circuitry and suppresses electromagnetic interference radiation from the internal circuitry to the external environment, thereby enhancing the safety of the EtherCAT slave device.

[0041] This application also provides an electronic device, including the EtherCAT slave device described above.

[0042] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0043] In this application, unless otherwise expressly specified and limited, the terms "set," "install," "connect," "link," and "fix" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0045] It should be noted that, in this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0046] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in this application, based on the technical solution and application concept of this application, should be included within the scope of protection of this application.

Claims

1. An EtherCAT slave device, characterized in that, include: The system comprises a slave control chip, at least two PHY chips, a network transformer corresponding to each PHY chip, at least one first signal header, at least one second signal header, a housing, a network connection indicator, and a data transmission indicator. The first end of the housing is provided with the same number of network interfaces as the network transformer, and the second end of the housing is provided with at least one pin header through hole; The slave control chip, at least two PHY chips, and at least two network transformers are housed within the housing. Each network interface is connected to a corresponding network transformer, each network transformer is connected to a corresponding PHY chip, and each PHY chip is connected to the first end of the slave control chip. The second end of the slave control chip is connected to the at least one first signal pin header, and the first signal pin header extends to the outer casing through a corresponding pin header through-hole. The slave control chip, the PHY chip, and the second signal header are placed on the first circuit board, and the network transformer is placed on the second circuit board. Each network transformer is connected to the corresponding PHY chip through the second signal header. Both the network connection indicator and the data transmission indicator are mounted on the second circuit board and connected to the PHY chip. The outer casing has light outlets corresponding to the network connection indicator and the data transmission indicator.

2. The EtherCAT slave device according to claim 1, characterized in that, The first signal header includes a first SPI signal header, a first reset signal header, a first distributed clock signal header, and a first EEPROM signal header.

3. The EtherCAT slave device according to claim 1, characterized in that, The second signal header includes a second SPI signal header, a second reset signal header, a second distributed clock signal header, a second EEPROM signal header, and an MDI signal header.

4. The EtherCAT slave device according to claim 1, characterized in that, The first end of the slave control chip is provided with MII and / or MDIO interfaces; Each of the PHY chips is connected to the MII and / or MDIO interface corresponding to the first terminal of the slave control chip.

5. The EtherCAT slave device according to claim 1, characterized in that, The slave control chip is an ASIC integrated chip.

6. The EtherCAT slave device according to claim 1, characterized in that, Each network interface is connected to the corresponding network transformer via an MDI signal line.

7. The EtherCAT slave device according to claim 1, characterized in that, The network interface is an RJ45 interface.

8. An electronic device, characterized in that, Includes the EtherCAT slave device as described in any one of claims 1-7.

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