Flexible wiring board and method for manufacturing the same

Abstract

A flexible circuit board and a manufacturing method thereof are provided. The flexible circuit board includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes a plurality of circuit layers and a plurality of insulating layers stacked alternately. The plurality of insulating layers are made of a photosensitive dielectric material and have a Young's modulus between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.

Description

Technical Field

[0001] This invention relates to a circuit board and its manufacturing method, and more particularly to a flexible circuit board and its manufacturing method. Background Technology

[0002] With the advancement of technology, various electronic products are trending towards thinner and smaller designs, and flexible electronic products (such as display devices, wearable devices, and communication devices) are increasingly being used in daily life. Currently, flexible circuit boards (PCBs) used in flexible electronic products are typically composed of alternating layers of polyimide and copper. Because the polyimide layer does not easily bond with the copper layer, adhesive is generally required to bond them together, which may make it difficult to reduce the overall thickness of the PCB. Furthermore, the current flexible circuit board wiring layers are manufactured using a subtractive process, resulting in a relatively large linewidth, which may be unfavorable for manufacturing fine or high-density lines. Summary of the Invention

[0003] This invention relates to a flexible circuit board and its manufacturing method, which can form a flexible circuit board with a high density circuit design and significantly reduce the overall thickness of the flexible circuit board.

[0004] According to an embodiment of the present invention, the flexible circuit board of the present invention includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite the top surface, wherein the circuit structure includes a plurality of staggered stacked circuit layers and a plurality of insulating layers, the plurality of insulating layers being made of a photosensitive dielectric material and having a Young's modulus between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.

[0005] In the flexible circuit board according to an embodiment of the present invention, the elongation of the plurality of insulating layers is greater than 20%.

[0006] In the flexible circuit board according to an embodiment of the present invention, the circuit structure described above has conductive through holes, and the first cover layer and the second cover layer respectively expose the two ends of the conductive through holes.

[0007] In a flexible circuit board according to an embodiment of the present invention, the aforementioned conductive through-hole includes a first opening, a second opening, and a portion of the circuit layer plated on the sidewalls of the first opening and the second opening, wherein the first opening and the second opening overlap in a direction perpendicular to the top surface.

[0008] In the flexible printed circuit board according to an embodiment of the present invention, the plurality of circuit layers include a first circuit layer, a second circuit layer, and a third circuit layer. The first circuit layer is located near the bottom surface of the circuit structure. The second circuit layer is disposed on the first circuit layer. The third circuit layer is disposed on the second circuit layer and is located near the top surface of the circuit structure. The plurality of insulating layers include a first insulating layer and a second insulating layer. The first insulating layer is disposed between the first circuit layer and the second circuit layer. The second insulating layer is disposed between the second circuit layer and the third circuit layer.

[0009] In a flexible circuit board according to an embodiment of the present invention, the bottom end of the aforementioned conductive through hole is flush with the bottom surface of the first insulating layer.

[0010] In a flexible circuit board according to an embodiment of the present invention, the first opening penetrates the first insulating layer and the first circuit layer, and the second circuit layer extends to the sidewall of the first opening to be electrically connected to the first circuit layer, wherein the second opening penetrates the second insulating layer, and the third circuit layer extends to the sidewall of the second opening to be electrically connected to the second circuit layer.

[0011] In a flexible circuit board according to an embodiment of the present invention, the second opening described above exposes a portion of the second circuit layer.

[0012] In the flexible circuit board according to an embodiment of the present invention, the bottom surface of the first circuit layer is flush with the bottom surface of a portion of the first insulating layer and the bottom surface of the second circuit layer.

[0013] In the flexible circuit board according to an embodiment of the present invention, the number of the plurality of circuit layers is 3 to 10.

[0014] In the flexible circuit board according to an embodiment of the present invention, there is no adhesive layer between the adjacent plurality of circuit layers and the plurality of insulating layers.

[0015] According to another embodiment of the present invention, a method for manufacturing a flexible printed circuit board includes the following steps: Providing a carrier board. Forming a circuit structure on the carrier board, wherein the circuit structure includes a plurality of staggered stacked circuit layers and a plurality of insulating layers, the plurality of insulating layers being made of a photosensitive dielectric material and having a Young's modulus between 0.36 GPa and 8 GPa. Forming a first cover layer on the circuit structure. Removing the carrier board, and then forming a second cover layer on the side of the circuit structure opposite to the first cover layer.

[0016] In the manufacturing method according to an embodiment of the present invention, the step of forming a circuit structure on a carrier board includes forming a first circuit layer on the carrier board; forming a first insulating layer on the first circuit layer; forming a first opening through the first insulating layer; forming a second circuit layer on the first insulating layer and extending to the sidewall of the first opening for electrical connection with the first circuit layer; forming a second insulating layer on the second circuit layer; forming a second opening through the second insulating layer, and the second opening overlapping the first opening; and forming a third circuit layer on the second insulating layer and extending to the sidewall of the second opening for electrical connection with the second circuit layer.

[0017] In the manufacturing method according to an embodiment of the present invention, the aperture of the second opening is greater than or equal to the aperture of the first opening.

[0018] In the manufacturing method according to an embodiment of the present invention, the adhesive layer is not included between the first circuit layer and the first insulating layer, or between the second circuit layer and the second insulating layer.

[0019] In the manufacturing method according to an embodiment of the present invention, the above-described method for forming the first circuit layer, the second circuit layer, or the third circuit layer is a semi-additive method.

[0020] In the manufacturing method according to an embodiment of the present invention, the method for forming the first opening or the second opening described above includes a photolithography process.

[0021] Based on the above, the flexible circuit board of the present invention includes multiple staggered circuit layers and multiple insulating layers. The insulating layers are made of a photosensitive dielectric material and have a Young's modulus of 0.36 GPa to 8 GPa. Therefore, the insulating layers exhibit good flexibility and adhesion to the circuit layers without the need for additional adhesives between them, thereby reducing the overall thickness of the flexible circuit board and facilitating miniaturization in subsequent electronic applications. Furthermore, since the circuit layers are formed using a semi-additive process, and the openings or blind vias in the insulating layers can be formed using photolithography, the circuit structure allows for highly dense wiring designs, further reducing the overall size of the flexible circuit board. Attached Figure Description

[0022] Figure 1A This is a cross-sectional schematic diagram of a flexible circuit board according to an embodiment of the present invention;

[0023] Figure 1B yes Figure 1A A magnified cross-sectional view of the central region R;

[0024] Figures 2A to 2G This is a cross-sectional schematic diagram of a manufacturing process of a flexible circuit board according to an embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures

[0026] 10: Flexible Circuit Board

[0027] 100: Circuit Structure

[0028] 100a: Top surface

[0029] 100b: Bottom surface

[0030] 101: Carrier board

[0031] 102: Release layer

[0032] 110: Line Layer

[0033] 112: First Line Layer

[0034] 112a: First seed layer

[0035] 112b: First plating layer

[0036] 114: Second Line Layer

[0037] 114a: Second seed layer

[0038] 114b: Second coating layer

[0039] 116: Third Line Layer

[0040] 116a: Third seed layer

[0041] 116b: Third coating layer

[0042] 120: Insulation layer

[0043] 122: First insulating layer

[0044] 124: Second insulating layer

[0045] 130: First Covering Layer

[0046] 140: Second Covering Layer

[0047] b1, b2, b3: Bottom surface

[0048] OP1: First opening

[0049] OP1',OP1”: Opening

[0050] OP2: Second opening

[0051] OP3: Third opening

[0052] OP4: Fourth opening

[0053] OP5: Fifth opening

[0054] OP6: Sixth opening

[0055] R: Region

[0056] s1, s2, s3: Inner wall

[0057] TH: Conductive Through Hole

[0058] T, T1, T2, T3, T4, T5, T6, T7: Thickness

[0059] V1, V2: Blind holes Detailed Implementation

[0060] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0061] Figure 1A This is a cross-sectional schematic diagram of a flexible circuit board according to an embodiment of the present invention. Figure 1B yes Figure 1A A magnified cross-sectional view of the central region R.

[0062] Please refer to Figure 1A and Figure 1B The flexible circuit board 10 includes a circuit structure 100, a first cover layer 130, and a second cover layer 140.

[0063] The circuit structure 100 has a top surface 100a and a bottom surface 100b opposite to the top surface 100a. The circuit structure 100 includes a plurality of staggered circuit layers 110 and a plurality of insulating layers 120. For example, the plurality of circuit layers 110 may include a first circuit layer 112, a second circuit layer 114, and a third circuit layer 116, and the plurality of insulating layers 120 may include a first insulating layer 122 and a second insulating layer 124. The first circuit layer 112 is located adjacent to the bottom surface 100b of the circuit structure 100. The second circuit layer 114 is disposed on the first circuit layer 112, and the first insulating layer 122 is disposed between the first circuit layer 112 and the second circuit layer 114. In some embodiments, a portion of the second circuit layer 114 may penetrate the first insulating layer 122 and be electrically connected to the first circuit layer 112. The third circuit layer 116 is disposed on the second circuit layer 114, and the second insulating layer 124 is disposed between the second circuit layer 114 and the third circuit layer 116. In some embodiments, a portion of the third wiring layer 116 may penetrate the second insulating layer 124 and be electrically connected to the second wiring layer 114. The third wiring layer 116 is located near the top surface 100a of the wiring structure 100. In some embodiments, the top surface of the third wiring layer 116 may be considered as the top surface 100a of the wiring structure 100.

[0064] This embodiment schematically illustrates three circuit layers 110 and two insulating layers 120, but is not intended to limit the invention. The number of circuit layers and insulating layers, as well as the wiring design of the circuit layers, can be adjusted according to actual needs. In some embodiments, the number of circuit layers 110 can be between 3 and 10, which is beneficial for reducing the size of the flexible circuit board.

[0065] The material of the circuit layer 110 may include copper, silver, gold, or alloys of the above materials, or other suitable metallic materials. The material of the insulating layer 120 may be a photosensitive dielectric material with a Young's modulus between 0.36 GPa and 8 GPa. In this way, the insulating layer 120 can have good flexibility and good adhesion to the circuit layer 110, eliminating the need for an adhesive layer between the insulating layer 120 and the circuit layer 110, thereby reducing the overall thickness of the flexible circuit board. In other words, adjacent circuit layers 110 and insulating layers 120 can be in direct contact without the need for an adhesive layer.

[0066] In some embodiments, the thickness of the circuit layer 110 (e.g., the thickness T1 of the first circuit layer 112, the thickness T2 of the second circuit layer 114, and the thickness T3 of the third circuit layer 116) can be between 2 μm and 8 μm.

[0067] In some embodiments, the thickness of the insulating layer 120 (e.g., the thickness T4 of the first insulating layer 122 and the thickness T5 of the second insulating layer 124) can be between 2 μm and 8 μm.

[0068] In some embodiments, the insulation layer 120 has an elongation of more than 20%, thus exhibiting good flexibility and bendability.

[0069] A first cover layer 130 is disposed on the top surface 100a of the circuit structure 100, and a second cover layer 140 is disposed on the bottom surface 100b of the circuit structure 100. The materials of the first cover layer 130 and the second cover layer 140 may include polyimide, photosensitive cover material, or other suitable materials. In some embodiments, the Young's modulus of the first cover layer 130 and the second cover layer 140 may be between 0.3 GPa and 3.0 GPa. The first cover layer 130 and the second cover layer 140 have bending resistance, protecting the circuit structure 100 from scratches or contamination by moisture, dust, etc., and providing support for the circuit structure 100.

[0070] In some embodiments, the thickness T6 of the first cover layer 130 and the thickness T7 of the second cover layer 140 can be between 20 μm and 50 μm.

[0071] In some embodiments, the circuit structure 100 has a conductive through-hole TH, and the first cover layer 130 and the second cover layer 140 can respectively expose the two ends of the conductive through-hole TH. In this way, electronic components (not shown) disposed on the top surface 100a and the bottom surface 100b of the circuit structure 100 can be directly connected through the conductive through-hole TH, eliminating the need for additional wiring design, making it easier to assemble electronic components onto the flexible circuit board 10 and helping to reduce the thickness of the circuit structure 100 or the flexible circuit board 10.

[0072] In some embodiments, the diameter of the conductive through-hole TH can be between 15 μm and 25 μm.

[0073] In some embodiments, such as Figure 1B As shown, the conductive via TH may include a first opening OP1, a second opening OP2, and a portion of the wiring layer 110 plated on the sidewalls of the first opening OP1 and the second opening OP2, and the first opening OP1 and the second opening OP2 overlap in a direction perpendicular to the first surface 100a. For example, the first opening OP1 may penetrate the first insulating layer 122 and the first wiring layer 112, that is, the first opening OP1 may be defined by the inner sidewall s1 of the first insulating layer 122 and the inner sidewall s2 of the first wiring layer 112. The second wiring layer 114 may extend to the sidewall of the first opening OP1 (i.e., the inner sidewall s1 of the first insulating layer 122 and the inner sidewall s2 of the first wiring layer 112) to be electrically connected to the first wiring layer 112. The second opening OP2 may penetrate the second insulating layer 124, and the position of the second opening OP2 corresponds to the position of the first opening OP1. That is, the second opening OP2 may be defined by the inner sidewall s3 of the second insulating layer 124, and the first opening OP1 and the second opening OP2 are interconnected. The third circuit layer 116 may extend to the sidewall of the second opening OP2 to be electrically connected to the second circuit layer 114.

[0074] In some embodiments, the aperture of the second opening OP2 may be slightly larger than the aperture of the first opening OP1, but the invention is not limited thereto. In other embodiments, the apertures of the first opening OP1 and the second opening OP2 may be equal.

[0075] In some embodiments, the first circuit layer 112 may include a first seed layer 112a and a first plating layer 112b disposed on the first seed layer 112a. The second circuit layer 114 may include a second seed layer 114a and a second plating layer 114b disposed on the second seed layer 114a. The third circuit layer 116 may include a third seed layer 116a and a third plating layer 116b disposed on the third seed layer 116a.

[0076] In some embodiments, the bottom surface b1 of the first circuit layer 112, the bottom surface b2 of a portion of the first insulating layer 122, and the bottom surface b3 of a portion of the second circuit layer 114 are flush. In other words, the bottom end of the conductive via TH (i.e., the bottom surface b3 of the second circuit layer 114) is flush with the bottom surface b2 of the first insulating layer 122 and the bottom surface b3 of a portion of the second circuit layer 114, meaning that the bottom end of the conductive via TH is coplanar with the bottom surface b2 of the first insulating layer 122 and the bottom surface b3 of a portion of the second circuit layer 114.

[0077] In some embodiments, the bottom surface b1 of a portion of the first circuit layer 112, the bottom surface b2 of a portion of the first insulating layer 122, and the bottom surface b3 of a portion of the second circuit layer 114 may constitute the bottom surface 100b of the circuit structure 100.

[0078] In some embodiments, the first cover layer 130 includes a third opening OP3, and the second cover layer 140 includes a fourth opening OP4. The third opening OP3 and the fourth opening OP4 overlap the conductive through-hole TH, and the aperture of the third opening OP3 and the aperture of the fourth opening OP4 are respectively larger than the maximum aperture of the conductive through-hole TH.

[0079] In some embodiments, the first cover layer 130 further includes a fifth opening OP5 to expose a portion of the third plating layer 116b of the third circuit layer 116. In some embodiments, the second cover layer 140 further includes a sixth opening OP6 to expose a portion of the first seed layer 112a of the first circuit layer 112.

[0080] In some embodiments, the thickness T of the flexible circuit board 10 can be between 60 μm and 100 μm.

[0081] Figures 2A to 2G This is a cross-sectional schematic diagram illustrating the manufacturing process of a flexible printed circuit board according to an embodiment of the present invention. It must be noted that... Figures 2A to 2G The embodiments follow Figures 1A to 1B The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0082] Please refer to Figure 2AA carrier plate 101 is provided. The carrier plate 101 can be glass, steel, or other suitable materials, and the invention is not limited thereto, as long as the carrier plate 101 can support a structure formed thereon or a component disposed thereon. A release layer 102 can then be formed on the carrier plate 101, allowing the carrier plate 101 to be separated from the film layer formed in subsequent process steps through the release layer 102. In some embodiments, the release layer 102 is, for example, composed of a material with weak adhesion. In other embodiments, the adhesion of the material constituting the release layer can be reduced via thermal processes, ultraviolet (UV) processes, laser processes, or other similar processes.

[0083] Please refer to Figures 2A to 2E This forms the circuit structure 100 on the carrier board 101. Specifically, firstly, as... Figure 2A As shown, a first circuit layer 112 can be formed on a carrier substrate 101. The first circuit layer 112 can be formed by a semi-additive process. For example, a first seed layer 112a can be formed on a release layer 102 by sputtering, and then a patterned photoresist layer (not shown) can be formed on the first seed layer 112a to expose the first seed layer 112a corresponding to the circuit pattern. Then, a first plating layer 112b can be formed on the exposed first seed layer 112a by electroplating. Afterward, the patterned photoresist layer and the first seed layer 112a located under the patterned photoresist layer are removed to form the first circuit layer 112, wherein the first circuit layer 112 may include an opening OP1' to expose a portion of the release layer 102.

[0084] Please refer to Figure 2B A first insulating layer 122 is formed on the first circuit layer 112, and a first opening OP1 is formed to penetrate the first insulating layer 122. For example, the first insulating layer 122 can be formed by blade coating, spin coating or other suitable processes, and then the opening OP1” and the blind via V1 can be formed in the first insulating layer 122. Since the material of the first insulating layer 122 is a photosensitive dielectric material, the opening OP1” and the blind via V1 can be formed by photolithography. For example, a photomask (not shown) can be used as a mask, and a portion of the photosensitive dielectric material can be cured by photopolymerization and / or baking. Furthermore, after the photosensitive dielectric material is cured, the remaining uncured photosensitive dielectric material can be removed by wet cleaning or other suitable methods to form a first insulating layer 122 including an opening OP1” and a blind via V1. The first opening OP1 may be formed by an opening OP1' of the first circuit layer 112 and an opening OP1” of the first insulating layer 122, with the position of the opening OP1” corresponding to the opening OP1' and connected to each other. In some embodiments, the blind via V1 may expose a portion of the first circuit layer 112.

[0085] In some embodiments, the apertures of the opening OP1” and the blind via V1 can be between 15 μm and 25 μm. Since the first opening OP1 and the blind via V1 of the first insulating layer 122 can be formed by photolithography, small aperture openings or blind vias can be fabricated, which helps to form a high-density wiring design.

[0086] Please refer to Figure 2C A second circuit layer 114 is formed on the first insulating layer 122 and extends to the sidewall of the first opening OP1 to be electrically connected to the first circuit layer 112. For example, the second circuit layer 114 can be formed in a similar manner to the formation of the first circuit layer 112. Specifically, a second seed layer 114a can be formed on the sidewall of the first insulating layer 122 and the first opening OP1 by sputtering. Then, a patterned photoresist layer (not shown) is formed on the second seed layer 114a to expose the second seed layer 114a with the corresponding circuit pattern. A second plating layer 114b is then formed on the exposed second seed layer 114a by electroplating. Afterward, the patterned photoresist layer and the second seed layer 114a located under the patterned photoresist layer are removed to form the second circuit layer 114.

[0087] In some embodiments, the second circuit layer 114 may be filled with blind vias V1 to be electrically connected to the first circuit layer 112.

[0088] In some embodiments, the second seed layer 114a may also extend to the portion of the release layer 102 exposed by the first opening OP1, but the invention is not limited thereto.

[0089] Please refer to Figure 2D A second insulating layer 124 is formed on the second circuit layer 114, and a second opening OP2 is formed to penetrate the second insulating layer 124, with the second opening OP2 overlapping the first opening OP1. For example, the second insulating layer 124 can be formed in a manner similar to that of the first insulating layer 122, by blade coating, spin coating, or other suitable processes. Then, the second opening OP2 and the blind via V2 can be formed in the second insulating layer 124. Since the material of the second insulating layer 124 is a photosensitive dielectric material, the second opening OP2 and the blind via V2 can be formed by photolithography. The formation methods of the second opening OP2 and the blind via V2 are similar to those of the opening OP1” and the blind via V1, and will not be described in detail here.

[0090] In some embodiments, the blind via V2 may expose a portion of the second circuit layer 114.

[0091] In some embodiments, the second opening OP2 may expose a portion of the second line layer 114 and the first opening OP1.

[0092] In some embodiments, the apertures of the second opening OP2 and the blind via V2 can be between 15 μm and 20 μm. Since the second opening OP2 and the blind via V2 of the second insulating layer 124 can be formed by photolithography, small-diameter openings or blind vias can be fabricated, which helps to implement high-density wiring designs.

[0093] In some embodiments, the aperture of the second opening OP2 may be slightly larger than the aperture of the first opening OP1 to facilitate alignment of the second opening OP2 with the first opening OP1 during the manufacturing process, but the present invention is not limited thereto. In other embodiments, the aperture of the second opening OP2 may be the same as the aperture of the first opening OP1.

[0094] Please refer to Figure 2E A third circuit layer 116 is formed on the second insulating layer 124 and extends to the sidewall of the second opening OP2 for electrical connection with the second circuit layer 114. For example, the third circuit layer 116 can be formed in a similar manner to the formation of the first circuit layer 112. Specifically, a third seed layer 116a can be formed on the sidewall of the second insulating layer 124 and the second opening OP2 by sputtering. Then, a patterned photoresist layer (not shown) is formed on the third seed layer 116a to expose the third seed layer 116a corresponding to the circuit pattern. A third plating layer 116b is then formed on the exposed third seed layer 116a by electroplating. Afterward, the patterned photoresist layer and the third seed layer 116a located under the patterned photoresist layer are removed to form the third circuit layer 114.

[0095] In some embodiments, the third circuit layer 116 may be filled with blind vias V2 for electrical connection with the second circuit layer 114.

[0096] In some embodiments, the third seed layer 116a may also extend to the portion of the second circuit layer 114 exposed by the opening OP2, but the invention is not limited thereto.

[0097] Since the circuit layers (first circuit layer 112, second circuit layer 114, and third circuit layer 116) in this embodiment are manufactured using a semi-additive method, it facilitates the fabrication of fine circuits. In some embodiments, the linewidth of the first circuit layer 112, the linewidth of the second circuit layer 114, and the linewidth of the third circuit layer 116 can be between 5 μm and 8 μm.

[0098] The above steps can roughly complete the manufacturing of a circuit structure 100 with three circuit layers and two insulation layers. However, the present invention is not limited thereto, and the above steps can be repeated according to actual needs to form a circuit structure with more circuit layers and insulation layers.

[0099] In some embodiments, the second opening OP2, with the third circuit layer 116 plated on its sidewall, and the first opening OP1, with the second circuit layer 114 plated on its sidewall, can form a conductive via TH. In this way, electronic components (not shown) subsequently disposed on one side of the circuit structure 100 can be directly connected to electronic components (not shown) disposed on the other side of the circuit structure 100 through the conductive via TH, thereby simplifying the complex wiring design of the circuit structure 100, making the assembly of electronic components easier, and helping to reduce the thickness of the circuit structure 100.

[0100] Please refer to Figure 2F A first cover layer 130 is formed on the circuit structure 100, wherein the first cover layer 130 includes a third opening OP3 and a fifth opening OP5. For example, if the material of the first cover layer is a polyimide cover film, the third opening OP3 and the fifth opening OP5 can be formed first by punching or drilling, and then the polyimide cover film can be placed on the third circuit layer 116 and the second insulating layer 124 by alignment bonding to form the first cover layer 130. If the material of the first cover layer is a liquid photosensitive cover material, it can be placed on the third circuit layer 116 and the second insulating layer 124 by spin coating or blade coating, and then a portion of the photosensitive cover material is cured by photopolymerization and / or baking using a photomask (not shown) as a mask. After curing the portion of the photosensitive cover material, the remaining uncured photosensitive cover material can be removed by wet cleaning or other suitable methods to form the first cover layer 130.

[0101] Please refer to Figure 2G Remove the carrier plate 101. For example, external energy can be applied to the release layer 102 by means of ultraviolet light, laser, visible light or heat to reduce the adhesion of the release layer 102, and then the release layer 102 and the carrier plate 101 can be removed simultaneously. In some embodiments, the carrier plate 101 can also be removed by mechanical peeling or other suitable removal processes, which is not limited to this invention.

[0102] Then, please refer to Figure 1AA second cover layer 140 is formed on the side of the circuit structure 100 opposite to the first cover layer 130, wherein the second cover layer 140 includes a fourth opening OP4 and a sixth opening OP6. The method of forming the second cover layer 140 is similar to the method of forming the first cover layer 130. For example, if the material of the second cover layer 140 is a polyimide cover film, the fourth opening OP4 and the sixth opening OP6 can be formed first by punching or drilling, and then the polyimide cover film can be disposed on the first circuit layer 112 and the first insulating layer 122 by alignment bonding to form the second cover layer 140. If the material of the second cover layer 140 is a liquid photosensitive cover material, it can be disposed on the first circuit layer 112 and the first insulating layer 122 by spin coating or blade coating, and then a portion of the photosensitive cover material can be cured by photopolymerization and / or baking using a photomask (not shown) as a mask. After the photosensitive cover material is cured, the remaining uncured photosensitive cover material can be removed by wet cleaning or other suitable methods to form a second cover layer 140.

[0103] After the above process, the fabrication of the flexible circuit board 10 can be roughly completed.

[0104] In summary, the flexible circuit board of the present invention comprises multiple staggered circuit layers and multiple insulating layers. The insulating layers are made of a photosensitive dielectric material and have a Young's modulus of 0.36 GPa to 8 GPa. Therefore, the insulating layers exhibit good flexibility and adhesion to the circuit layers without the need for additional adhesives between them, thereby reducing the overall thickness of the flexible circuit board and facilitating miniaturization in subsequent electronic applications. Furthermore, since the circuit layers are formed using a semi-additive process, and the openings or blind vias in the insulating layers can be formed using photolithography, the circuit structure allows for highly dense wiring designs, further reducing the overall size of the flexible circuit board.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flexible circuit board, characterized in that, include: A circuit structure having a top surface and a bottom surface relative to the top surface, wherein the circuit structure is composed of multiple circuit layers and multiple insulating layers stacked in an alternating manner, the multiple insulating layers being made of a photosensitive dielectric material and having a Young's modulus between 0.36 GPa and 8 GPa; A first covering layer is disposed on the top surface of the circuit structure and is in direct contact with the top surface; as well as The second cover layer is disposed on the bottom surface of the circuit structure and is in direct contact with the bottom surface. The plurality of line layers include: The first circuit layer is located near the bottom surface of the circuit structure; A second line layer is disposed on top of the first line layer; and The third circuit layer is disposed on the second circuit layer and is close to the top surface of the circuit structure. The plurality of insulating layers include: A first insulating layer is disposed between the first circuit layer and the second circuit layer; and A second insulating layer is disposed between the second circuit layer and the third circuit layer. The circuit structure has conductive through-holes, and the first cover layer and the second cover layer respectively expose the two ends of the conductive through-holes. The conductive through-hole includes: The first opening penetrates the first insulating layer and the first circuit layer; A second opening penetrates the second insulating layer, wherein the first opening and the second opening overlap in a direction perpendicular to the top surface; and A circuit layer plated on the sidewalls of the first opening and the second opening, wherein the circuit layer includes a first portion of the second circuit layer extending from the top surface of the first insulating layer to the sidewall of the first opening and a second portion of the third circuit layer extending from the top surface of the second insulating layer to the sidewall of the second opening, wherein the second portion is electrically connected to the first portion, and the first portion is in direct contact with and electrically connected to the sidewall of the first circuit layer. The bottom surface of the first circuit layer is flush with the bottom surface of part of the first insulation layer and the bottom surface of the first part.

2. The flexible circuit board according to claim 1, characterized in that, The elongation of the plurality of insulating layers is greater than 20%.

3. The flexible circuit board according to claim 1, characterized in that, The bottom end of the conductive through hole is flush with the bottom surface of the first insulating layer.

4. The flexible circuit board according to claim 1, characterized in that, The second opening exposes a portion of the second circuit layer.

5. The flexible circuit board according to claim 1, characterized in that, The number of layers in the multiple line layers is 3 to 10.

6. The flexible circuit board according to claim 1, characterized in that, There is no adhesive layer between the adjacent plurality of line layers and the plurality of insulating layers.

7. A method for manufacturing a flexible printed circuit board, characterized in that, include: Provide carrier board; A circuit structure is formed on the carrier board, wherein the circuit structure consists of multiple circuit layers and multiple insulating layers stacked in an alternating manner, the material of the multiple insulating layers is a photosensitive dielectric material and the Young's modulus of the multiple insulating layers is between 0.36 GPa and 8 GPa; A first cover layer is formed on the top surface of the circuit structure, wherein the first cover layer is in direct contact with the top surface; Remove the carrier plate; as well as A second cover layer is formed on the bottom surface of the circuit structure relative to the top surface, wherein the second cover layer is in direct contact with the bottom surface. The steps of forming the circuit structure on the carrier board include: A first circuit layer is formed on the carrier board, wherein the first circuit layer has an opening; A first insulating layer is formed on the first circuit layer; A first opening is formed to penetrate the first insulating layer and correspond to the opening in the first circuit layer; A second circuit layer is formed on the first insulating layer and extends to the sidewall of the first opening and the sidewall of the opening of the first circuit layer to be electrically connected to the first circuit layer. A second insulating layer is formed on the second circuit layer; A second opening is formed to penetrate the second insulating layer, and the second opening overlaps the first opening; A third circuit layer is formed on the second insulating layer and extends to the sidewall of the second opening for electrical connection with the second circuit layer. The bottom surface of the first circuit layer is flush with the bottom surface of a portion of the first insulation layer and the bottom surface of a portion of the second circuit layer.

8. The manufacturing method according to claim 7, characterized in that, The diameter of the second opening is greater than or equal to the diameter of the first opening.

9. The manufacturing method according to claim 7, characterized in that, There is no adhesive layer between the first circuit layer and the first insulating layer, or between the second circuit layer and the second insulating layer.

10. The manufacturing method according to claim 7, characterized in that, The method for forming the first line layer, the second line layer, or the third line layer is a semi-additive method.

11. The manufacturing method according to claim 7, characterized in that, The method for forming the first opening or the second opening includes a photolithography process.

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