Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method includes: providing a semiconductor substrate and forming a first word line; forming a support layer on the semiconductor substrate, including stacked first oxide layer, first sacrificial layer, second oxide layer, second sacrificial layer, third oxide layer, third sacrificial layer, and fourth oxide layer; forming an active pillar penetrating the support layer at a position corresponding to the first word line; removing the first and third sacrificial layers to form a first trench; removing the circumferential walls of the active pillars to form a first annular trench, wherein the size of the first annular trench is larger than the size of the first trench in the vertical direction; forming a P-type filler in the first annular trench; forming a semiconductor oxide layer in the P-type filler, wherein the size of the semiconductor oxide layer is not smaller than the size of the first trench and smaller than the size of the P-type filler in the vertical direction; forming a word line layer in the first trench; and removing the second sacrificial layer to form a second trench and a drain connection layer. This method can reduce the size of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] As the semiconductor industry develops, the critical dimensions of semiconductor devices continue to shrink. In related technologies, Gate All-Around Field Effect Transistors (GAAFETs) have begun to be used in Dynamic Random Access Memory (DRAM). Although this can reduce the linewidth of semiconductor devices to some extent, capacitors are still required. The presence of capacitors, however, greatly limits the extent to which linewidth can be reduced, and the reduction of critical dimensions of semiconductor devices is still not ideal. Summary of the Invention

[0003] This disclosure provides a method for fabricating a semiconductor structure that enables the semiconductor structure to store charge even without a capacitor, thereby achieving a further reduction in the size of the semiconductor device.

[0004] This disclosure also provides a semiconductor structure that does not have a capacitor, yet is still able to store charge, and has a reduced size.

[0005] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing a semiconductor substrate in which a first bit line is formed; forming a support layer on the semiconductor substrate, the support layer comprising a first oxide layer, a first sacrificial layer, a second oxide layer, a second sacrificial layer, a third oxide layer, a third sacrificial layer, and a fourth oxide layer stacked sequentially on the semiconductor substrate; forming an active pillar penetrating the support layer in a vertical direction at a position corresponding to the first bit line on the support layer; removing the first sacrificial layer and the third sacrificial layer to form first trenches respectively; etching away a portion of the circumferential wall of the active pillar from each first trench to form a first annular trench surrounding the active pillar, wherein the size of the first annular trench is larger than the size of the first trench in the vertical direction; forming a P-type filler in each first annular trench; forming a semiconductor oxide layer in each P-type filler, wherein the size of the semiconductor oxide layer is not smaller than the size of the first trench and smaller than the size of the P-type filler in the vertical direction; forming a word line layer in each first trench; removing the second sacrificial layer to form a second trench; and forming a drain connection layer in the second trench.

[0006] According to an exemplary embodiment of this disclosure, the method further includes: forming a fifth oxide layer at the top of the fourth oxide layer and the active post; forming a dielectric layer on the fifth oxide layer; forming a bit line contact plug hole communicating with the active post in the fifth oxide layer and the dielectric layer, and forming a bit line contact plug in the bit line contact plug hole; forming a second bit line on the dielectric layer, the second bit line being connected to the bit line contact plug.

[0007] According to an exemplary embodiment of this disclosure, there are multiple first bit lines, and the multiple first bit lines are spaced apart in a first horizontal direction, each first bit line extends along a second horizontal direction, and there are multiple active pillars distributed on the first bit lines; wherein the first horizontal direction and the second horizontal direction are not parallel.

[0008] According to an exemplary embodiment of this disclosure, prior to forming the first trench, the method further includes forming an isolation groove extending in the support layer along the first horizontal direction, the isolation groove extending from the fourth oxide layer to the top surface of the first oxide layer, and the isolation groove being located between two adjacent active pillars in the second horizontal direction.

[0009] According to an exemplary embodiment of this disclosure, while forming a word line layer in each of the first trenches, material of the word line layer is also formed in the isolation trench, and then the material of the word line layer located in the isolation trench is removed.

[0010] According to an exemplary embodiment of this disclosure, while the drain connection layer is formed in the second trench, material of the drain connection layer is also formed in the isolation trench, and then the material of the drain connection layer located in the isolation trench is removed.

[0011] According to an exemplary embodiment of this disclosure, the fifth oxide layer is also filled in the isolation trench.

[0012] According to an exemplary embodiment of this disclosure, the materials of the first oxide layer, the second oxide layer, the third oxide layer, the fourth oxide layer, and the fifth oxide layer include at least one of silicon oxide and silicon carbide.

[0013] According to an exemplary embodiment of this disclosure, forming a semiconductor oxide layer in each of the P-type fillers includes: oxidizing each of the P-type fillers to a predetermined thickness to form the semiconductor oxide layer, wherein the orthogonal projection of the first trench in the semiconductor oxide layer completely overlaps with the semiconductor oxide layer or is located in the semiconductor oxide layer.

[0014] According to an exemplary embodiment of this disclosure, the preset thickness is less than the thickness of the P-type filler.

[0015] According to an exemplary embodiment of the present disclosure, forming a semiconductor oxide layer in each of the P-type fillers includes: forming the semiconductor oxide layer on the surface of the P-type filler exposed in the first trench, wherein the size of the semiconductor oxide layer in the vertical direction is equal to the size of the first trench.

[0016] According to an exemplary embodiment of this disclosure, the active pillar is made of N-type silicon pillar, and the P-type filler is made of P-type doped silicon.

[0017] According to an exemplary embodiment of this disclosure, the word line layer and the drain connection layer are made of at least one of tungsten, tantalum, gold, silver and ruthenium.

[0018] According to an exemplary embodiment of this disclosure, the formation process of the active pillar and the P-type filler includes a selective epitaxial growth process.

[0019] According to another aspect of this disclosure, a semiconductor structure is provided, the semiconductor structure being prepared by the method of any of the above embodiments; the semiconductor structure includes: a semiconductor substrate having a first bit line; a functional layer disposed on the semiconductor substrate, the functional layer including a first oxide layer, a word line layer, a second oxide layer, a drain connection layer, a third oxide layer, a word line layer, and a fourth oxide layer stacked in sequence; and semiconductor pillars penetrating the functional layer in a vertical direction at positions corresponding to the first bit line, the semiconductor pillars including: active pillars including two pillars integrally connected in the vertical direction, the connection point of the two pillars being located at the drain connection layer, each pillar having a first annular groove surrounding the pillar between its two ends; a P-type filler disposed in the first annular groove of each pillar; a semiconductor oxide layer disposed in each P-type filler and connected to the corresponding word line layer, wherein in the vertical direction, the size of the semiconductor oxide layer is not less than the size of the corresponding word line layer and is less than the size of the corresponding P-type filler.

[0020] According to an exemplary embodiment of this disclosure, each of the semiconductor oxide layers is disposed in the P-type filler, and the orthogonal projection of each word line layer onto the semiconductor oxide layer completely overlaps with or is located within the semiconductor oxide layer.

[0021] According to an exemplary embodiment of this disclosure, each of the semiconductor oxide layers is disposed between the corresponding word line layer and the P-type filler, and in the vertical direction, the size of the semiconductor oxide layer is equal to the size of the corresponding word line layer.

[0022] According to an exemplary embodiment of this disclosure, the semiconductor structure further includes: a fifth oxide layer disposed on the fourth oxide layer; a dielectric layer disposed on the fifth oxide layer; a bit line contact plug disposed in the fifth oxide layer and the dielectric layer and connected to the top end of the active pillar; and a second bit line disposed on the dielectric layer and connected to the bit line contact plug.

[0023] According to an exemplary embodiment of this disclosure, there are multiple first bit lines, and the multiple first bit lines are spaced apart in a first horizontal direction, each first bit line extends along a second horizontal direction, and there are multiple semiconductor pillars distributed on the first bit lines; wherein the first horizontal direction and the second horizontal direction are not parallel.

[0024] According to an exemplary embodiment of the present disclosure, the functional layer further includes an isolation layer extending along a first horizontal direction, the isolation layer extending from the fourth oxide layer to the top surface of the first oxide layer, and the isolation layer being located between two adjacent semiconductor pillars in the second horizontal direction.

[0025] As can be seen from the above technical solution, this disclosure possesses at least one of the following advantages and positive effects:

[0026] In the semiconductor structure fabrication method disclosed herein, a P-type filler is formed in the first annular groove of the active pillar, and a semiconductor oxide layer is formed between the P-type filler and the word line layer. This allows the P-type filler located between the semiconductor oxide layer and the active pillar in the vertical direction to form a charge storage structure, thus enabling charge storage within this structure and avoiding the need for capacitors. Furthermore, this method achieves a double-layer stacking of this charge storage structure in the vertical direction, increasing charge storage density and further reducing the critical dimensions of the semiconductor device. Attached Figure Description

[0027] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0028] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some exemplary embodiments of the present disclosure;

[0029] Figure 2 A top view of a semiconductor substrate for some exemplary embodiments of this disclosure;

[0030] Figure 2a for Figure 2 Cross-sectional view along the middle AA;

[0031] Figure 2b for Figure 2 Cross-sectional view along the middle BB;

[0032] Figure 3 This is a top view of a support layer formed on a semiconductor substrate according to some embodiments of the present disclosure;

[0033] Figure 3a for Figure 3 Cross-sectional view along the middle AA;

[0034] Figure 3b for Figure 3 Cross-sectional view along the middle BB;

[0035] Figure 4 This is a top view of some embodiments of the present disclosure showing the formation of filling holes in the support layer;

[0036] Figure 4a for Figure 4 Cross-sectional view along the middle AA;

[0037] Figure 4b for Figure 4 Cross-sectional view along the middle BB;

[0038] Figure 5 This is a top view of an active column filling a filling hole according to some embodiments of the present disclosure;

[0039] Figure 5a for Figure 5 Cross-sectional view along the middle AA;

[0040] Figure 5b for Figure 5 Cross-sectional view along the middle BB;

[0041] Figure 6 This is a top view of some embodiments of the present disclosure showing the formation of isolation grooves in the support layer;

[0042] Figure 6a for Figure 6 Cross-sectional view along the middle AA;

[0043] Figure 6b for Figure 6 Cross-sectional view along the middle BB;

[0044] Figure 7a for Figure 6a A schematic diagram showing the formation of the first trench by removing the first and third sacrificial layers from the semiconductor structure.

[0045] Figure 7b for Figure 6b A schematic diagram showing the formation of the first trench by removing the first and third sacrificial layers from the semiconductor structure.

[0046] Figure 8a for Figure 7aA schematic diagram of the semiconductor structure forming the first annular groove;

[0047] Figure 8b for Figure 7b A schematic diagram of the semiconductor structure forming the first annular groove;

[0048] Figure 9a for Figure 8a A schematic diagram of the semiconductor structure forming a P-type filler;

[0049] Figure 9b for Figure 8b A schematic diagram of the semiconductor structure forming a P-type filler;

[0050] Figure 10a for Figure 9a A schematic diagram of the semiconductor structure forming a semiconductor oxide layer;

[0051] Figure 10b for Figure 9b A schematic diagram of the semiconductor structure forming a semiconductor oxide layer;

[0052] Figure 11a for Figure 10a A schematic diagram of the semiconductor structure forming the word line layer;

[0053] Figure 11b for Figure 10b A schematic diagram of the semiconductor structure forming the word line layer;

[0054] Figure 12a for Figure 11a A schematic diagram of removing the word line layer in the isolation trench of a semiconductor structure;

[0055] Figure 12b for Figure 11b A schematic diagram of removing the word line layer in the isolation trench of a semiconductor structure;

[0056] Figure 13a for Figure 12a A schematic diagram of the semiconductor structure with the second sacrificial layer removed;

[0057] Figure 13b for Figure 12b A schematic diagram of the semiconductor structure with the second sacrificial layer removed;

[0058] Figure 14a for Figure 13a A schematic diagram of the semiconductor structure forming the drain connection layer;

[0059] Figure 14b for Figure 13b A schematic diagram of the semiconductor structure forming the drain connection layer;

[0060] Figure 15a for Figure 14a A schematic diagram of removing the drain connection layer in the isolation trench;

[0061] Figure 15b for Figure 14b A schematic diagram of removing the drain connection layer in the isolation trench;

[0062] Figure 16a for Figure 15a A schematic diagram of the semiconductor structure forming the fifth oxide layer;

[0063] Figure 16b for Figure 15b A schematic diagram of the semiconductor structure forming the fifth oxide layer;

[0064] Figure 17 for Figure 16a and Figure 16b A top view of the semiconductor structure forming the dielectric layer and bit line contact plug holes;

[0065] Figure 17a for Figure 17 Cross-sectional view along the middle AA;

[0066] Figure 17b for Figure 17 Cross-sectional view along the middle BB;

[0067] Figure 18a for Figure 17a A schematic diagram of the semiconductor structure forming a bit line contact plug;

[0068] Figure 18b for Figure 17b A schematic diagram of the semiconductor structure forming a bit line contact plug;

[0069] Figure 19 for Figure 18a and Figure 18b A top view of the semiconductor structure forming the second bit line;

[0070] Figure 19a for Figure 19 Cross-sectional view along the middle AA;

[0071] Figure 19b for Figure 19a Enlarged view of point C in the middle;

[0072] Figure 19c for Figure 19 Cross-sectional view along the middle BB;

[0073] Figure 20 This is a schematic cross-sectional view of the semiconductor structure along a second horizontal direction in some other embodiments.

[0074] Explanation of reference numerals in the attached figures:

[0075] 10. Semiconductor substrate; 101. First bit line; 20. Support layer; 201. First oxide layer; 202. First sacrificial layer; 203. Second oxide layer; 204. Second sacrificial layer; 205. Third oxide layer; 206. Third sacrificial layer; 207. Fourth oxide layer; 208. Fifth oxide layer; 209. Dielectric layer; 210. First hard mask layer; 211. Filling via; 212. Second hard mask layer; 30. Active pillar; 301. First annular trench; 302. Pillar; 40. P-type filler; 50, 50'. Semiconductor oxide layer; 60. First trench; 70. Word line layer; 80. Second trench; 90. Drain connection layer; 100. Isolation trench; 110. Bit line contact plug hole; 120. Bit line contact plug; 130. Second bit line; 140. Isolation layer; S. Charge storage structure. Detailed Implementation

[0076] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0077] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.

[0078] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0079] Furthermore, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Above" and "below" are technical terms indicating location, which are used merely for clarity and are not intended to be limiting.

[0080] This disclosure provides a method for fabricating a semiconductor structure. For example... Figures 1 to 20 As shown, where, Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure is shown. Figures 2 to 19c The diagram shows a schematic representation of a semiconductor structure at different fabrication stages in some embodiments of this disclosure. Figure 20 Schematic diagrams of semiconductor structures according to other embodiments of this disclosure are shown. For example... Figure 1 As shown, the method for fabricating the semiconductor structure according to an embodiment of this disclosure includes:

[0081] Step S200: Provide a semiconductor substrate 10, and form a first line 101 in the semiconductor substrate 10.

[0082] Step S400: A support layer 20 is formed on the semiconductor substrate 10. The support layer 20 includes a first oxide layer 201, a first sacrificial layer 202, a second oxide layer 203, a second sacrificial layer 204, a third oxide layer 205, a third sacrificial layer 206 and a fourth oxide layer 207 stacked sequentially on the semiconductor substrate 10.

[0083] Step S600: An active column 30 is formed at the position corresponding to the first line 101 of the support layer 20, penetrating the support layer 20 in the vertical direction Z.

[0084] Step S800: Remove the first sacrificial layer 202 and the third sacrificial layer 206 to form the first trench 60.

[0085] Step S1000: Etch away a portion of the circumferential wall of the active post 30 from each first trench 60 to form a first annular groove 301 surrounding the active post 30, and in the vertical direction Z, the size of the first annular groove 301 is larger than the size of the first trench 60.

[0086] Step S1200: Form a P-type filler 40 in each first annular groove 301.

[0087] Step S1400: A semiconductor oxide layer 50 is formed on each P-type filler 40. In the vertical direction Z, the size of the semiconductor oxide layer 50 is not less than the size of the first trench 60 and is smaller than the size of the P-type filler 40.

[0088] Step S1600: Form word line layer 70 in each first trench 60.

[0089] Step S1800: Remove the second sacrificial layer 204 to form the second trench 80.

[0090] Step S2000: Form a drain connection layer 90 in the second trench 80.

[0091] In the semiconductor structure fabrication method disclosed herein, a P-type filler 40 is formed in the first annular groove 301 of the active pillar 30, and a semiconductor oxide layer 50 is formed between the P-type filler 40 and the word line layer 70. This allows the P-type filler 40 located between the semiconductor oxide layer 50 and the active pillar 30 in the vertical direction Z to form a charge storage structure S. Therefore, charge can be stored in this charge storage structure S, avoiding the need for a capacitor. Furthermore, this method achieves a double-layer stacking of this charge storage structure S in the vertical direction Z, increasing the charge storage density and further reducing the critical dimensions of the semiconductor device.

[0092] The method for fabricating a semiconductor device according to embodiments of this disclosure will now be described in detail.

[0093] Step S200: Provide a semiconductor substrate 10, and form a first line 101 in the semiconductor substrate 10.

[0094] The semiconductor substrate 10 of this embodiment can be made of silicon, silicon carbide, silicon nitride, silicon-on-insulator, silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, or germanium-on-insulator, etc., without any special limitation.

[0095] like Figures 2 to 2b As shown, N-type doping is performed on the semiconductor substrate 10 to form the first first line 101. The first first line 101 can be formed by implanting N-type dopant ions such as P and As into the semiconductor substrate 10 through an ion implantation process. In some embodiments, there can be multiple first first lines 101, and each first first line 101 can extend along the second horizontal direction Y. This can also be understood as forming multiple N-type doped regions extending along the second direction on the semiconductor substrate 10.

[0096] Step S400: A support layer 20 is formed on the semiconductor substrate 10. The support layer 20 includes a first oxide layer 201, a first sacrificial layer 202, a second oxide layer 203, a second sacrificial layer 204, a third oxide layer 205, a third sacrificial layer 206 and a fourth oxide layer 207 stacked sequentially on the semiconductor substrate 10.

[0097] like Figures 3 to 3bAs shown, the first oxide layer 201, the first sacrificial layer 202, the second oxide layer 203, the second sacrificial layer 204, the third oxide layer 205, the third sacrificial layer 206, and the fourth oxide layer 207 are stacked in sequence along the vertical Z direction by a deposition process. The materials of the first oxide layer 201, the second oxide layer 203, the third oxide layer 205, and the fourth oxide layer 207 include at least one of silicon oxide and silicon oxycarbide. The materials of the first sacrificial layer 202 and the third sacrificial layer 206 can be at least one of silicon nitride or silicon oxynitride, meaning that the materials of the first sacrificial layer 202 and the third sacrificial layer 206 can be the same. The material of the second sacrificial layer 204 can include polycrystalline silicon. The material of the second sacrificial layer 204 is different from that of the first sacrificial layer 202 and the third sacrificial layer 206. This allows the second sacrificial layer 204 to have different etch selectivity ratios with the first sacrificial layer 202 and the third sacrificial layer 206, so that the second sacrificial layer 204 can be retained when the first sacrificial layer 202 and the third sacrificial layer 206 are etched in subsequent processes.

[0098] It should be noted that, in the embodiments of this disclosure, "upper" and "lower" refer to the relative positional relationship between different components in the semiconductor structure, for example, in Figure 3a In this embodiment, the first oxide layer 201 is located on the semiconductor substrate 10, and the first sacrificial layer 202 is located on the first oxide layer 201. Therefore, the semiconductor substrate 10 is located below the first oxide layer 201, and the first oxide layer 201 is located below the first sacrificial layer 202. Taking the stacking direction of each layer in the support layer 20 as the vertical direction Z, the technical terms "upper" and "lower" can be understood as their relative positional relationship in the vertical direction Z. Furthermore, in this embodiment, "first horizontal direction X" and "second horizontal direction Y" can be understood as two horizontal directions perpendicular to the vertical direction Z, with an angle between them, meaning the two horizontal directions are not parallel. In some embodiments, the first horizontal direction X and the second horizontal direction Y can be perpendicular to each other. The use of the above-described terms indicating relative positional relationships in this embodiment is merely for ease of explanation and is not intended to be limiting.

[0099] Step S600: An active column 30 is formed at the position corresponding to the first line 101 of the support layer 20, penetrating the support layer 20 in the vertical direction Z.

[0100] Continue to refer to Figure 3a and Figure 3b A first hard mask layer 210 is formed on the fourth oxide layer 207, such as Figures 4 to 4bAs shown, a mask pattern for a filling hole 211 is formed on the first hard mask layer 210. The mask pattern for the filling hole 211 corresponds to the position of the first line 101. The support layer 20 is etched according to the mask pattern to form a filling hole 211 that penetrates the support layer 20 in the vertical direction Z. That is, the filling hole 211 extends from the fourth oxide layer 207 to the surface of the first line 101 in the vertical direction Z.

[0101] like Figures 5 to 5b As shown, the first hard mask layer 210 located on the fourth oxide layer 207 is removed, and an active pillar 30 is formed in the filling hole 211. Therefore, the active pillar 30 penetrates the support layer 20 in the vertical direction Z.

[0102] In some embodiments, the number of active pillars 30 can be multiple, and they are distributed on the first line 101, that is, located above the first line 101 and connected to the first line 101. Therefore, there are multiple active pillars 30 on each first line 101 extending along the second horizontal direction Y, and also multiple spaced active pillars 30 in the first horizontal direction X. The active pillars 30 are arranged in an array.

[0103] In some embodiments, the active pillar 30 is formed by a selective epitaxial growth (SEG) process, and the active pillar 30 is formed by an N-type doped material, such as an N-type silicon pillar, i.e. silicon doped with P or As. The material of the active pillar 30 can be the same as the material of the first line 101, or it can be different, and no special limitation is made here.

[0104] Step S800: Remove the first sacrificial layer 202 and the third sacrificial layer 206 to form the first trench 60.

[0105] like Figure 7a and 7b As shown, the first sacrificial layer 202 and the third sacrificial layer 206 are removed using an etching process to form the first trench 60. In some embodiments, a wet etching process can be used to remove the first sacrificial layer 202 and the third sacrificial layer 206. The wet etching process can use concentrated sulfuric acid and hydrogen peroxide as etchants. By adjusting the concentration of the etchant, the degree of etching can be controlled, thereby controlling the etching precision of the first sacrificial layer 202 and the third sacrificial layer 206. Those skilled in the art can adjust the etching parameters according to the actual situation, and no special limitations are made here.

[0106] Please refer to Figures 6 to 6bBefore step S800, the method for fabricating a semiconductor structure according to the present disclosure further includes step S700: forming an isolation trench 100 extending along a first horizontal direction X in the support layer 20, the isolation trench 100 extending from the fourth oxide layer 207 to the top surface of the first oxide layer 201, and the isolation trench 100 being located between two adjacent active pillars 30 in the second horizontal direction Y.

[0107] Specifically, a second hard mask layer 212 is formed on the fourth oxide layer 207, and a mask pattern of an isolation trench 100 is formed on the second hard mask layer 212. The mask pattern extends along the first horizontal direction X. According to the mask pattern, the support layer 20 can be etched using a wet etching process from the fourth oxide layer 207 to the upper surface of the first oxide layer 201 to form the isolation trench 100, such that the isolation trench 100 is located between two adjacent active pillars 30 in the second horizontal direction Y.

[0108] Step S1000: Etch away a portion of the circumferential wall of the active post 30 from each first trench 60 to form a first annular groove 301 surrounding the active post 30, and in the vertical direction Z, the size of the first annular groove 301 is larger than the size of the first trench 60.

[0109] like Figure 8a and Figure 8b As shown, the circumferential wall of the active pillar 30 exposed in the first trench 60 is etched, so that the portion of the active pillar 30 corresponding to each first trench 60 forms a "U" shape in the cross section along the vertical direction Z. In some embodiments, the circumferential wall etching of the first trench 60 can be performed using wet etching, and the etchant can be tetramethylammonium hydroxide (TMAH). By controlling the amount and concentration of the etchant, the etching depth and its critical dimensions of the first annular groove 301 can be precisely controlled. Those skilled in the art can select the above etching process according to the actual situation, and no special limitation is made here.

[0110] In some embodiments, such as Figure 8a and Figure 8b As shown, in the two first annular grooves 301 formed in each active pillar 30, the two ends of the first annular groove 301 closer to the substrate 10 in the vertical direction Z correspond to the first oxide layer 201 and the second oxide layer 203, respectively, and the two ends of the first annular groove 301 farther from the substrate 10 in the vertical direction Z correspond to the third oxide layer 205 and the fourth oxide layer 207, respectively.

[0111] Step S1200: Form a P-type filler 40 in each first annular groove 301.

[0112] like Figure 9a and Figure 9bAs shown, each active pillar 30 is filled with a P-type filler 40 in its two first annular grooves 301. The material of the P-type filler 40 can be P-type doped silicon, such as silicon material doped with boron. The P-type filler 40 can be formed by a selective epitaxial growth (SEG) process.

[0113] Step S1400: A semiconductor oxide layer 50 is formed on each P-type filler 40. In the vertical direction Z, the size of the semiconductor oxide layer 50 is not less than the size of the first trench 60 and is smaller than the size of the P-type filler 40.

[0114] In some embodiments, such as Figure 10a and Figure 10b As shown, forming a semiconductor oxide layer 50 in each P-type filler 40 may include: oxidizing each P-type filler 40 to a predetermined thickness to form a semiconductor oxide layer 50, wherein the first trench 60, in its orthogonal projection onto the semiconductor oxide layer 50, completely overlaps with or is located within the semiconductor oxide layer 50. That is, the semiconductor oxide layer 50 is formed in situ within the P-type filler 40, improving the stability of the bonding between the P-type filler 40 and the semiconductor oxide layer 50.

[0115] In some embodiments, the predetermined thickness of the semiconductor oxide layer 50 is less than the thickness of the P-type filler 40. This predetermined thickness refers to the dimension of the surface of the semiconductor oxide layer 50 facing the first trench 60 in the direction close to the central axis L of the active pillar 30. That is, a P-type filler 40 is present between the semiconductor oxide layer 50 and the active pillar 30.

[0116] In this method, the size of the semiconductor oxide layer 50 in the vertical direction Z can be equal to or larger than the size of the first trench 60 but smaller than the size of the P-type filler 40. This allows the P-type filler 40, located between the semiconductor oxide layer 50 and the active pillar 30, to form a charge storage structure S in the vertical direction Z. However, the charge storage structure S is not strictly located between the semiconductor oxide layer 50 and the active pillar 30 in the vertical direction Z; it can extend at least partially in the direction closer to the semiconductor oxide layer 50. This charge storage structure S functions similarly to a capacitor in a conventional semiconductor structure, storing and releasing charge. Therefore, the semiconductor structure prepared by this method can be capacitor-free, enabling further miniaturization of semiconductor devices.

[0117] In other embodiments, forming a semiconductor oxide layer 50' in each P-type filler 40 includes forming a semiconductor oxide layer 50' on the surface of the P-type filler 40 exposed in the first trench 60, wherein the size of the semiconductor oxide layer 50' in the vertical direction Z is equal to the size of the first trench 60.

[0118] like Figure 20 As shown, unlike the embodiments described above, the semiconductor oxide layer 50' is not formed in situ through oxidation of the P-type filler 40. Instead, it is formed in each first trench 60 by growing an external material on the surface of the P-type filler 40. This semiconductor oxide layer 50' can be formed using a selective epitaxial growth (SEG) process. Furthermore, the dimension of the semiconductor oxide layer 50' in the vertical direction Z is equal to the dimension of the first trench 60 in the vertical direction Z. This allows for more precise control of the dimensions of the semiconductor oxide layer 50'.

[0119] In the vertical direction Z, the portion of the P-type dopant located between the semiconductor oxide layer 50' and the active pillar 30 also constitutes the charge storage structure S. Of course, the charge storage structure S is not strictly located between the semiconductor oxide layer 50' and the active pillar 30 in the vertical direction Z; it can also extend at least partially in the vertical direction Z towards the semiconductor oxide layer 50', such as... Figure 20 As shown. The function of this charge storage structure S is the same as that in the above embodiments, and will not be repeated here.

[0120] Step S1600: Form word line layer 70 in each first trench 60.

[0121] like Figure 11a and Figure 11b As shown, word line layers 70 are formed in two first trenches 60 using a deposition process. The word line layers 70 are connected to the semiconductor oxide layer 50. The material of the word line layers 70 may include at least one of tungsten, tantalum, gold, silver, and ruthenium.

[0122] Please refer to Figure 11b Since the isolation trench 100 is formed in step S700, when the word line layer 70 is formed using the deposition process, the material of the word line layer 70 will also be formed in the isolation trench 100 and on the fourth oxide layer 207. For example... Figure 12a and Figure 12b After the word line layer 70 is formed, the material of the word line layer 70 deposited on the surface of the fourth oxide layer 207 and the material of the word line layer 70 in the isolation trench 100 are removed by etching process.

[0123] Step S1800: Remove the second sacrificial layer 204 to form the second trench 80.

[0124] like Figure 13a and Figure 13b As shown, the second sacrificial layer 204 is removed by an etching process to expose the active pillar 30 in the second trench 80. This etching process can be a wet etching process.

[0125] Step S2000: Form a drain connection layer 90 in the second trench 80.

[0126] like Figure 14a and Figure 14b As shown, a drain connection layer 90 is formed in the second trench 80 using a deposition process. The drain connection layer 90 is connected to the active pillar 30. The material of the drain connection layer 90 may include at least one of tungsten, tantalum, gold, silver, and ruthenium. Figure 14b As shown, since the drain connection layer 90 is formed in the second trench 80, conductive material of the drain connection layer 90 is also deposited in the isolation trench 100 and on the fourth oxide layer 207, therefore, as Figure 15a and 15b As shown, after the drain connection layer 90 is formed, the conductive material of the drain connection layer 90 located in the isolation trench 100 and the fourth oxide layer 207 is removed.

[0127] Step S2200: A fifth oxide layer 208 is formed on the top of the fourth oxide layer 207 and the active pillar 30.

[0128] like Figure 16a and Figure 16b As shown, a fifth oxide layer 208 can be formed on the upper surface of the fourth oxide layer 207 using a deposition process, and the material of the fifth oxide layer 208 also fills the isolation trench 100. In some embodiments, the thickness of the fifth oxide layer 208 can be greater than the thickness of the fourth oxide layer 207, allowing the subsequently formed bit line contact plug hole 110 to have a greater depth, thereby making the bit line contact plug 120 more stable and improving the stability of the semiconductor structure's performance. The material of the fifth oxide layer 208 may include at least one of silicon oxide and silicon carbide.

[0129] Step S2400: Form a dielectric layer 209 on the fifth oxide layer 208;

[0130] like Figure 17 , Figure 17a and Figure 17b As shown, a dielectric layer 209 is formed on the fifth oxide layer 208 using a deposition process. The material of the dielectric layer 209 may include at least one of silicon nitride and silicon oxynitride.

[0131] Step S2600: A bit line contact plug hole 110 communicating with the active post 30 is formed in the fifth oxide layer 208 and the dielectric layer 209, and a bit line contact plug 120 is formed in the bit line contact plug hole 110.

[0132] Continue to refer to Figures 17 to 18bAt the location corresponding to the active pillar 30 of the dielectric layer 209, the dielectric layer 209 and the fifth oxide layer 208 are etched to form a bit line contact plug hole 110. A bit line contact plug 120 is then formed in the bit line contact plug hole 110 using a deposition process. Subsequently, a chemical mechanical polishing process can be used to grind the surfaces of the dielectric layer 209 and the bit line contact plug 120 flat. The bit line contact plug 120 can be made of at least one of tungsten, tantalum, gold, silver, and ruthenium.

[0133] Step S2800: A second bit line 130 is formed on the dielectric layer 209, and the second bit line 130 is connected to the bit line contact plug 120.

[0134] like Figures 19 to 19c As shown, a deposition process is used to deposit material for the second bit line 130 on the dielectric layer 209, forming a second bit line material layer. Then, an etching process is used to retain the second bit line material layer at the connection portion with the bit line contact plug 120, forming the second bit line 130. Figure 19 As shown, the orthographic projection of the second bit line 130 onto the semiconductor substrate 10 at least partially overlaps with the first bit line 101. In some embodiments, the orthographic projection of the second bit line 130 onto the semiconductor substrate 10 completely overlaps with the first bit line 101, or the first bit line 101 lies within the orthographic projection of the second bit line 130 onto the semiconductor substrate 10. The second bit line 130 extends along a second horizontal direction Y, and a plurality of second bit lines 130 are spaced apart along a first horizontal direction X.

[0135] In the semiconductor structure fabrication method of this disclosure embodiment, a P-type filler 40 is formed in the first annular groove 301 of the active pillar 30, and semiconductor oxide layers 50, 50' are formed between the P-type filler 40 and the word line layer 70, such that the P-type filler 40 located between the semiconductor oxide layer 50 and the active pillar 30 in the vertical direction Z forms a charge storage structure S, in which charge can be stored, and the portion of the active pillar 30 corresponding to the P-type filler 40 forms a bridge.

[0136] When a positive voltage is applied to the word line layer 70 and the drain connection layer 90, electron-hole pairs are generated in the charge storage structure S in the P-type filler 40. Due to the presence of the bridge in the active pillar 30, electrons can leave the charge storage structure S, while holes cannot. Simultaneously, the application of a positive voltage to the word line layer 70 causes an inversion layer to form in the portion of the P-type filler 40 near the semiconductor oxide layer 50. The portion of the P-type filler 40 corresponding to the inversion layer forms a depletion region. Figure 19a As shown, holes can be retained in the charge storage structure S, thus achieving the function of storing charge. When a positive voltage is applied to the word line layer 70 and a negative voltage is applied to the drain connection layer 90, all the charge located in the charge storage structure S can be extracted so that it can be stored again.

[0137] Therefore, the charge storage structure S in this embodiment of the present disclosure functions as a capacitor. The semiconductor structure prepared using the method of this embodiment of the present disclosure no longer requires a capacitor, thus reducing the size of the semiconductor structure. In addition, this method achieves double-layer stacking of this charge storage structure S in the vertical Z direction, increasing the charge storage density and further reducing the critical dimensions of the semiconductor device.

[0138] According to another aspect of this disclosure, a semiconductor structure is provided. The semiconductor structure is prepared by the method of any of the above embodiments. Figures 19a-19c and Figure 20 As shown, the semiconductor structure includes a semiconductor substrate 10, a functional layer, and semiconductor pillars. The semiconductor substrate 10 has a first word line 101. The functional layer is disposed on the semiconductor substrate 10 and includes a first oxide layer 201, a word line layer 70, a second oxide layer 203, a drain connection layer 90, a third oxide layer 205, a word line layer 70, and a fourth oxide layer 207, stacked sequentially. Semiconductor pillars penetrate the functional layer in the vertical Z direction at positions corresponding to the first word line 101. Each semiconductor pillar includes an active pillar 30, a P-type filler 40, and a semiconductor oxide layer 50.

[0139] The materials of the first bit line 101, the first oxide layer 201, the word line layer 70, the second oxide layer 203, the drain connection layer 90, the third oxide layer 205, and the fourth oxide layer 207, as well as the active pillar 30, the P-type filler 40, and the semiconductor oxide layer 50 in this embodiment are the same as those in the method embodiment, and will not be repeated here.

[0140] In some embodiments, the active pillar 30 includes two pillars 302 integrally connected in the vertical direction Z, with the connection point of the two pillars 302 located in the drain connection layer 90. Each pillar 302 has a first annular groove 301 surrounding its two ends. A P-type filler 40 is disposed in the first annular groove 301 of each pillar 302. A semiconductor oxide layer 50 is disposed in each P-type filler 40 and connected to the corresponding word line layer 70. In the vertical direction Z, the size of the semiconductor oxide layer 50 is not smaller than the size of the corresponding word line layer 70 and smaller than the size of the corresponding P-type filler 40.

[0141] In some embodiments, such as Figure 19a and Figure 19bAs shown, each semiconductor oxide layer 50 is disposed within the P-type filler 40, and the orthographic projection of each word line layer 70 onto the semiconductor oxide layer 50 completely overlaps with or is located within the semiconductor oxide layer 50. This results in the P-type filler 40 having a concave cross-section in the vertical direction Z. Therefore, in the vertical direction Z, the P-type filler 40 located between the semiconductor oxide layer 50 and the active pillar 30 forms a charge storage structure S.

[0142] In other embodiments, such as Figure 20 As shown, each semiconductor oxide layer 50 is disposed between the corresponding word line layer 70 and the P-type filler 40, and in the vertical direction Z, the size of the semiconductor oxide layer 50 is equal to the size of the corresponding word line layer 70. In these embodiments, in the vertical direction Z, the P-type filler 40 located between the semiconductor oxide layer 50 and the active pillar 30 also forms a charge storage structure S.

[0143] The semiconductor structure of this disclosure embodiment further includes: a fifth oxide layer 208, a dielectric layer 209, a bit line contact plug 120, and a second bit line 130. For example... Figure 19a and Figure 20 As shown, the fifth oxide layer 208 is disposed on the fourth oxide layer 207, the dielectric layer 209 is disposed on the fifth oxide layer 208, the bit line contact plug 120 passes through the fifth oxide layer 208 and the dielectric layer 209, and is connected to the top end of the active post 30. The second bit line 130 is disposed on the dielectric layer 209 and is connected to the bit line contact plug 120. Figure 19 As shown, the orthogonal projection of the second bit line 130 onto the semiconductor substrate 10 completely overlaps with the first bit line 101, or the first bit line 101 is located within the orthogonal projection of the second bit line 130 onto the semiconductor substrate 10.

[0144] In some embodiments, such as Figure 2 As shown, there are multiple first-line lines 101, and these multiple first-line lines 101 are spaced apart in the first horizontal direction X, with each first-line line 101 extending along the second horizontal direction Y. Figure 19a and Figure 19b As shown, there are multiple semiconductor pillars distributed on the first line 101, and the first horizontal direction X and the second horizontal direction Y are not parallel.

[0145] In some embodiments, such as Figure 19a and Figure 19b As shown, the functional layer also includes an isolation layer 140 extending along the first horizontal direction X. The isolation layer 140 extends from the fourth oxide layer 207 to the top surface of the first oxide layer 201, and the isolation layer 140 is located between two adjacent semiconductor pillars in the second horizontal direction Y, so as to isolate the adjacent semiconductor pillars in the second horizontal direction Y.

[0146] In the semiconductor structure of this embodiment, since a charge storage structure S is present, charge can be stored in the charge storage structure S, which acts as a capacitor. Therefore, the semiconductor structure of this embodiment does not require a separate capacitor, thus reducing the size of the semiconductor structure. Furthermore, the charge storage structure S in the semiconductor structure of this embodiment is double-layered in the vertical Z direction, increasing the charge storage density and further reducing the critical dimensions of the semiconductor device.

[0147] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to utilize this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein a first line is formed therein; A support layer is formed on the semiconductor substrate, the support layer comprising a first oxide layer, a first sacrificial layer, a second oxide layer, a second sacrificial layer, a third oxide layer, a third sacrificial layer and a fourth oxide layer stacked sequentially on the semiconductor substrate; An active column is formed in the support layer at a position corresponding to the first bit line, penetrating the support layer in the vertical direction; Remove the first sacrificial layer and the third sacrificial layer to form the first trench; Etching away a portion of the circumferential wall of the active post from each of the first trenches forms a first annular groove surrounding the active post, and in the vertical direction, the size of the first annular groove is larger than the size of the first trench. A P-type filler is formed in each of the first annular grooves; A semiconductor oxide layer is formed on each of the P-type fillers, wherein in the vertical direction, the size of the semiconductor oxide layer is not less than the size of the first trench and is less than the size of the P-type filler; A word line layer is formed in each of the first trenches; Remove the second sacrificial layer to form a second trench; as well as A drain connection layer is formed in the second trench.

2. The method according to claim 1, characterized in that, Also includes: A fifth oxide layer is formed at the top of the fourth oxide layer and the active pillar; A dielectric layer is formed on the fifth oxide layer; Bit line contact plug holes communicating with the active post are formed in the fifth oxide layer and the dielectric layer, and bit line contact plugs are formed in the bit line contact plug holes; A second bit line is formed on the dielectric layer, and the second bit line is connected to the bit line contact plug.

3. The method according to claim 2, characterized in that, The number of first bit lines is multiple, and the multiple first bit lines are spaced apart in a first horizontal direction. Each first bit line extends along a second horizontal direction. The number of active pillars is multiple, and they are distributed on the first bit lines. The first horizontal direction and the second horizontal direction are not parallel.

4. The method according to claim 3, characterized in that, The process includes the following steps prior to forming the first trench: An isolation groove is formed in the support layer extending along the first horizontal direction, the isolation groove extending from the fourth oxide layer to the top surface of the first oxide layer, and the isolation groove is located between two adjacent active pillars in the second horizontal direction.

5. The method according to claim 4, characterized in that, While forming a word line layer in each of the first trenches, material of the word line layer is also formed in the isolation trench, and then the material of the word line layer located in the isolation trench is removed.

6. The method according to claim 5, characterized in that, While forming the drain connection layer in the second trench, the material of the drain connection layer is also formed in the isolation trench, and then the material of the drain connection layer located in the isolation trench is removed.

7. The method according to claim 6, characterized in that, The fifth oxide layer is also filled in the isolation groove.

8. The method according to claim 2, characterized in that, The materials of the first oxide layer, the second oxide layer, the third oxide layer, the fourth oxide layer and the fifth oxide layer include at least one of silicon oxide and silicon carbide.

9. The method according to claim 1, characterized in that, The formation of a semiconductor oxide layer in each of the P-type fillers includes: Each of the P-type fillers is oxidized to a predetermined thickness to form the semiconductor oxide layer, wherein the orthogonal projection of the first trench onto the semiconductor oxide layer completely overlaps with the semiconductor oxide layer or is located within the semiconductor oxide layer.

10. The method according to claim 9, characterized in that, The preset thickness is less than the thickness of the P-type filler.

11. The method according to claim 1, characterized in that, The formation of a semiconductor oxide layer in each of the P-type fillers includes: The semiconductor oxide layer is formed on the surface of the P-type filler exposed in the first trench, and the size of the semiconductor oxide layer in the vertical direction is equal to the size of the first trench.

12. The method according to claim 1, characterized in that, The active pillar is made of N-type silicon, and the P-type filler is made of P-type doped silicon.

13. The method according to claim 1, characterized in that, The material of the word line layer and the drain connection layer includes at least one of tungsten, tantalum, gold, silver and ruthenium.

14. The method according to claim 1, characterized in that, The formation process of the active column and the P-type filler includes a selective epitaxial growth process.

15. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method according to any one of claims 1 to 14; the semiconductor structure comprises: Semiconductor substrate, having a first line; A functional layer is disposed on the semiconductor substrate, the functional layer comprising a first oxide layer, a word line layer, a second oxide layer, a drain connection layer, a third oxide layer, a word line layer, and a fourth oxide layer stacked sequentially; and A semiconductor pillar, located at a position corresponding to the first bit line, penetrates the functional layer vertically, and the semiconductor pillar includes: An active column includes two columns integrally connected in the vertical direction, and the connection point of the two columns is located in the drain connection layer, and each column has a first annular groove surrounding the column between its two ends; P-type filler is disposed in the first annular groove of each of the columns; A semiconductor oxide layer is disposed on each of the P-type fillers and connected to the corresponding word line layer. In the vertical direction, the size of the semiconductor oxide layer is not less than the size of the corresponding word line layer and is less than the size of the corresponding P-type filler.

16. The semiconductor structure according to claim 15, characterized in that, Each of the semiconductor oxide layers is disposed in the P-type filler, and the orthogonal projection of each word line layer onto the semiconductor oxide layer completely overlaps with or is located within the semiconductor oxide layer.

17. The semiconductor structure according to claim 15, characterized in that, Each of the semiconductor oxide layers is disposed between the corresponding word line layer and the P-type filler, and in the vertical direction, the size of the semiconductor oxide layer is equal to the size of the corresponding word line layer.

18. The semiconductor structure according to claim 15, characterized in that, Also includes: The fifth oxide layer is disposed on the fourth oxide layer; A dielectric layer is disposed on the fifth oxide layer; The bit line contact plug is inserted through the fifth oxide layer and the dielectric layer, and is connected to the top of the active post; as well as The second bit line is disposed on the dielectric layer and is connected to the bit line contact plug.

19. The semiconductor structure according to claim 18, characterized in that, The number of first bit lines is multiple, and the multiple first bit lines are spaced apart in a first horizontal direction. Each first bit line extends along a second horizontal direction. The number of semiconductor pillars is multiple, and they are distributed on the first bit lines. The first horizontal direction and the second horizontal direction are not parallel.

20. The semiconductor structure according to claim 19, characterized in that, The functional layer also includes an isolation layer extending along a first horizontal direction, the isolation layer extending from the fourth oxide layer to the top surface of the first oxide layer, and the isolation layer being located between two adjacent semiconductor pillars in the second horizontal direction.

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