Method for controlling a manufacturing process and associated apparatus

Abstract

A method of determining a process window within a process space is disclosed, the method comprising, for each of a plurality of process conditions (600) associated with providing a feature across a plurality of layers, obtaining (610) profile data (615) relating to the feature to be provided across the plurality of layers to a substrate (625), and failure mode data (650) describing a constraint on the profile data across the plurality of layers. The failure mode data is applied to the profile data to determine (640) a failure count for each process condition; and the process window is determined (655) by associating each process condition with its corresponding failure count. A method of determining an actuation constraint subspace of a process window based on actuation constraints applied by a plurality of actuators is also disclosed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to EP application 20187251.2, filed July 22, 2020; EP application 20188802.1, filed July 31, 2020; and US application 63 / 089,822, filed October 9, 2020, all of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a method and apparatus for applying patterns to a substrate in a photolithography process. Background Technology

[0004] A photolithography apparatus is a machine that applies a desired pattern onto a substrate, typically onto a target portion of the substrate. Photolithography apparatuses can be used, for example, in the fabrication of integrated circuits (ICs). In this case, a patterning device (or alternatively, a mask or photomask) can be used to generate a circuit pattern that will be formed on a single layer of the IC. This pattern can be transferred to a target portion (e.g., a portion comprising one or more dies) on a substrate (e.g., a silicon wafer). The transfer of the pattern is typically achieved by imaging onto a layer of radiation-sensitive material (resist) disposed on the substrate. Typically, a single substrate will contain a network of adjacent target portions patterned sequentially. Known photolithography apparatuses include: a so-called stepper, in which each target portion is irradiated by exposing the entire pattern onto the target portion at once; and a so-called scanner, in which each target portion is irradiated by scanning the pattern in a given direction (“scanning” direction) via a radiation beam while simultaneously scanning the substrate parallel or antiparallel to that direction. A pattern can also be transferred from a patterning device to a substrate by imprinting the pattern onto the substrate.

[0005] To monitor the photolithography process, parameters of the patterned substrate are measured. These parameters may include, for example, overlay errors between successive layers formed in or on the patterned substrate, and the critical linewidth (CD) of the developed photoresist. This measurement can be performed on the product substrate and / or a dedicated measurement target. Various techniques exist for measuring the microstructures formed in the photolithography process, including the use of scanning electron microscopy and various specialized tools. One rapid and non-invasive form of specialized inspection tool is a scatterometer, in which a radiation beam is directed onto a target on the substrate surface, and the characteristics of the scattered or reflected beam are measured. Two main types of scatterometers are known. Spectroscopic scatterometers direct a broadband radiation beam onto the substrate and measure the spectrum of the radiation scattered over a specific narrow angular range (the spectrum being the intensity as a function of wavelength). Angle-resolved scatterometers use a monochromatic radiation beam and measure the intensity of the scattered radiation as a function of angle.

[0006] Examples of known scatterers include angle-resolved scatterers of the type described in US2006033921A1 and US2010201963A1. The targets used by such scatterers are relatively large, such as 40 μm × 40 μm gratings, and the measurement beam generates spots smaller than the grating (i.e., grating underfill). In addition to reconstructing the shape of the measurement feature, such devices can be used to measure diffraction-based overlay, as described in published patent application US2006066855A1. Diffraction-based overlay measurements using dark-field imaging of the diffraction order enable overlay measurements of smaller targets. Examples of dark-field imaging measurements can be found in international patent applications WO2009 / 078708 and WO2009 / 106279, which are incorporated herein by reference in their entirety. Further developments of this technology have been described in the following published patent publications: US20110027704A, US20110043791A, US2011102753A1, US20120044470A, US20120123581A, US20130258310A, US20130271740A, and WO2013178422A1. These targets can be smaller than the illumination point and can be surrounded by the product structure on the wafer. Multiple gratings can be measured in one image using composite grating targets. The contents of all these applications are also incorporated herein by reference.

[0007] In photolithography processes, such as applying patterns to a substrate or measuring such patterns, process control methods are used to monitor and control the process. These process control techniques are typically performed to obtain corrections for controlling the photolithography process. Improvements to these process control methods are desired. Summary of the Invention

[0008] In a first aspect of the invention, a method is provided for determining a process window within a process space for a manufacturing process, the process space being defined by a plurality of process parameters, the process window being a subspace within the process space associated with expected compliance with processing requirements; the method includes: for each of a plurality of process conditions associated with providing features across a plurality of layers, obtaining profile data relating to features to be provided across a substrate; obtaining failure mode data describing constraints on the profile data across the plurality of layers; determining a failure count for each process condition by applying the failure mode data to the profile data; and determining the process window by associating each process condition with its corresponding failure count.

[0009] In a second aspect of the invention, a method is provided for configuring a plurality of actuators for actuating a manufacturing process, the method comprising: obtaining a process window within a process space for the manufacturing process, the process space being defined by a plurality of process parameters, the process window being a subspace within the process space associated with expected compliance with processing requirements; determining an actuation constraint subspace of the process window based on actuation constraints imposed by the plurality of actuators; and determining a control strategy for the plurality of actuators that conforms to the actuation constraint subspace.

[0010] In other aspects of the invention, a computer program comprising program instructions operable, when run on a suitable device, to perform the methods of the first or second aspect is provided, as well as a photolithography apparatus configured to provide a product structure to a substrate in a photolithography process, said photolithography apparatus comprising a processor and the aforementioned computer program.

[0011] Further aspects, features, and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. Note that the invention is not limited to the specific embodiments described herein. These embodiments are for illustrative purposes only. Additional embodiments will be apparent to those skilled in the art based on the teachings contained herein. Attached Figure Description

[0012] Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which:

[0013] Figure 1 It describes photolithography equipment and other apparatus for forming semiconductor device manufacturing facilities;

[0014] Figure 2 A schematic diagram of a scatterer for measuring a target according to an embodiment of the present invention is included;

[0015] Figure 3 An exemplary source of the processing parameters is shown;

[0016] Figure 4 The concept of Overlapping Process Window (OPW) is illustrated schematically;

[0017] Figure 5 The diagram schematically illustrates a method for determining the calibration used to control a photolithography apparatus.

[0018] Figure 6 It is a flowchart describing a method according to one embodiment;

[0019] Figure 7 (a) and Figure 7 (b) Illustrate the problems caused by different failure mechanisms resulting from scanner and external process crosstalk; and Figure 7(c) The corresponding process window and the resulting overlapping process window are illustrated.

[0020] Figure 8 (a)-8(e) each include a two-dimensional representation of the concept of the design-perceived actuation space;

[0021] Figure 9 The diagram illustrates the concept of a holistic, multi-dimensional process window library;

[0022] Figure 10 It is a flowchart of a control method for a photolithography process, including upstream, scanner, and downstream processes; and

[0023] Figure 11 Includes (a) a process space diagram of scanner parameters and downstream parameters, and (b) a flowchart illustrating how the permissible range of the scanner (actuation space or DAAS) varies with downstream parameter settings. Detailed Implementation

[0024] Before describing the embodiments of the present invention in detail, it is illustrative to provide an example environment in which the embodiments of the present invention can be implemented.

[0025] Figure 1 A lithography apparatus LA is shown at 200 as part of an industrial production facility implementing a high-capacity lithography manufacturing process. In this example, the manufacturing process is suitable for manufacturing semiconductor products (integrated circuits) on substrates such as semiconductor wafers. Those skilled in the art will understand that a wide variety of products can be manufactured by processing different types of substrates in variations of this process. The production of semiconductor products is used purely as an example, which has enormous commercial significance today.

[0026] Within the lithography apparatus (or simply "lithography tool" 200), a measurement station MEA is shown at 202, and an exposure station EXP is shown at 204. A control unit LACU is shown at 206. In this example, each substrate accesses both the measurement and exposure stations to be patterned. For example, in an optical lithography apparatus, a projection system is used to transfer a product pattern from a patterning device MA onto a substrate using regulated radiation and a projection system. This is accomplished by forming an image of the pattern within a layer of radiation-sensitive resist material.

[0027] The term "projection system" as used herein should be broadly interpreted to include any type of projection system, including refractive, reflective, antirefractive, magnetic, electromagnetic, and electrostatic optical systems, or any combination thereof, depending on the application of the exposure radiation in use, or other factors such as the use of immersion liquids or vacuum. The patterning MA device can be a mask or stencil that imparts a pattern to a radiation beam transmitted or reflected by the patterning device. Known operating modes include step mode and scan mode. It is well known that projection systems can cooperate in various ways with supports and positioning systems for the substrate and patterning device to apply a desired pattern to many target portions across the substrate. Programmable patterning devices can be used instead of masks with fixed patterns. Radiation can, for example, include electromagnetic radiation in the deep ultraviolet (DUV) or extreme ultraviolet (EUV) bands. This disclosure also applies to other types of lithography processes, such as imprint lithography and direct write lithography, for example, by electron beam.

[0028] The lithography equipment control unit (LACU) controls all movements and measurements of various actuators and sensors to receive the substrate W and the mask MA and perform patterning operations. The LACU also includes signal and data processing capabilities to perform desired calculations related to the operation of the equipment. In practice, the LACU will be implemented as a system of multiple sub-units, each handling real-time data acquisition, processing, and control of subsystems or components within the equipment.

[0029] Before the pattern is applied to the substrate at the exposure station EXP, the substrate is processed in the measurement station MEA, allowing various preparation steps to be performed. Preparation steps may include mapping the surface height of the substrate using a level sensor; and measuring the position of alignment marks on the substrate using an alignment sensor. The alignment marks are nominally arranged in a regular grid pattern. However, due to inaccuracies in mark generation and substrate deformation that occurs throughout the substrate processing, the marks deviate from the ideal grid. Therefore, in addition to measuring the position and orientation of the substrate, the alignment sensor must actually measure the position of many marks across a region of the substrate in detail if the equipment is to print product features in the correct positions with very high precision. The equipment can be a so-called dual-stage type, with two substrate stages, each with a positioning system controlled by a control unit LACU. While one substrate on one stage is exposed at the exposure station EXP, another substrate can be loaded onto the other substrate stage at the measurement station MEA, enabling the performance of various preparation steps. Therefore, the measurement of alignment marks is very time-consuming, and providing two substrate stages allows for a significant increase in the throughput of the equipment. If the position sensor IF cannot measure the position of the substrate stage when it is in the measurement station and the exposure station, a second position sensor can be provided so that the position of the substrate stage can be tracked at both stations. A lithography apparatus LA can, for example, be a so-called dual-stage type, having two substrate stages and two stations (exposure station and measurement station), between which the substrate stages can be exchanged.

[0030] Within the production facility, equipment 200 forms part of a "lithography unit" or "lithography cluster," which also includes a coating unit 208 for applying photoresist and other coatings to a substrate W for patterning via equipment 200. At the output side of equipment 200, a baking unit 210 and a developing unit 212 are provided for developing the exposed pattern into a physical resist pattern. Between all these units, a substrate handling system is responsible for supporting the substrate and transferring it from one unit to the next. These units, generally referred to collectively as tracks, are under the control of a track control unit, which in turn is controlled by a supervisory control system SCS, which also controls the lithography equipment via a lithography equipment control unit (LACU). Therefore, different units can be operated to maximize throughput and processing efficiency. The supervisory control system SCS receives configuration scheme information R, which provides very detailed definitions of the steps to be performed to produce each patterned substrate.

[0031] Once the pattern has been applied and developed in the photolithography unit, the patterned substrate 220 is transferred to other processing apparatuses, such as those illustrated at 222, 224, and 226. In typical manufacturing facilities, a wide range of processing steps are performed by various apparatuses. For example, apparatus 222 in this embodiment is an etching station, and apparatus 224 performs a post-etch annealing step. Additional physical and / or chemical processing steps are applied in other apparatuses such as 226. Fabricating actual devices may require various types of operations, such as material deposition, modification of surface material properties (oxidation, doping, ion implantation, etc.), chemical mechanical polishing (CMP), etc. In practice, apparatus 226 may represent a series of different processing steps performed in one or more apparatuses. As another example, apparatuses and processing steps for implementing self-aligned multiple patterning can be provided to generate multiple smaller features based on a precursor pattern laid by the photolithography equipment.

[0032] As is well known, the fabrication of semiconductor devices involves repeated processing to build device structures with appropriate materials and patterns layer by layer on a substrate. Accordingly, the substrates 230 arriving at the photolithographic cluster can be newly fabricated substrates, or they can be substrates that have been fully processed previously in that cluster or in another device. Similarly, depending on the required processing, the substrates 232 leaving device 226 can be returned for subsequent patterning operations in the same photolithographic cluster, they may be designated for patterning operations in different clusters, or they may be products to be sent for dicing and packaging.

[0033] Each layer of the product structure requires a different set of process steps, and the apparatus 226 used at each layer can be completely different in type. Furthermore, even when the processing steps performed by apparatus 226 are nominally the same, in a large facility, there may be several supposedly identical machines operating in parallel to perform step 226 on different substrates. Minor differences in setup or malfunction between these machines may mean that they affect different substrates in different ways. Even for relatively common steps for each layer, such as etching (apparatus 222), it can be achieved by several nominally identical but parallel-operating etching apparatuses to maximize throughput. Moreover, in practice, different layers require different etching processes (e.g., chemical etching, plasma etching) depending on the details of the material to be etched and specific requirements such as, for example, anisotropic etching.

[0034] As mentioned earlier, previous and / or subsequent processes can be performed in other lithography equipment, and even in different types of lithography equipment. For example, in lithography tools that are more advanced than other, less demanding layers, some layers with high requirements for parameters such as resolution and overlay in device manufacturing processes can be performed. Therefore, some layers can be exposed in immersion lithography tools, while others are exposed in "dry" tools. Some layers can be exposed in tools operating at DUV wavelengths, while other layers are exposed using EUV wavelength radiation.

[0035] To ensure correct and consistent exposure of substrates by photolithography equipment, it is desirable to inspect the exposed substrates to measure characteristics such as overlay error between subsequent layers, line thickness, and critical dimension (CD). Accordingly, the manufacturing facility where the photolithography unit (LC) is located also includes a metrology system that receives some or all of the substrates (W) already processed in the photolithography unit. The measurement results are provided directly or indirectly to the supervisory control system (SCS). If an error is detected, the exposure of subsequent substrates can be adjusted, especially if the metrology can be performed quickly and sufficiently so that other substrates in the same batch will still be exposed. Furthermore, exposed substrates can be stripped and reprocessed to increase yield, or discarded, thus avoiding further processing of substrates known to be defective. In cases where only some target portions of the substrate are defective, further exposure can be performed only on those good target portions.

[0036] Figure 1 The diagram also shows a measurement device 240, which is provided for measuring parameters of the product at a desired stage in the manufacturing process. A common example of a measurement station in modern lithography production facilities is a scatterometer (e.g., a dark-field scatterometer, an angle-resolved scatterometer, or a spectral scatterometer), which can be used to measure the characteristics of the developed substrate at 220 prior to etching in device 222. Using measurement device 240, it is possible to determine whether important performance parameters, such as overlay or critical dimensions (CD), do not meet specified accuracy requirements in the developed resist. Prior to the etching step, there is an opportunity to strip the developed resist and reprocess the substrate 220 through the lithography cluster. By making small adjustments over time through the supervisory control system SCS and / or control unit LACU 206, the measurement results 242 from device 240 can be used to maintain the accurate performance of the patterning operations in the lithography cluster, thereby minimizing the risk of non-conforming products requiring reprocessing.

[0037] Additionally, measuring device 240 and / or other measuring devices (not shown) can be applied to measure the characteristics of the processed substrates 232, 234 and the incoming substrate 230. The measuring devices can be used on the processed substrates to determine important parameters such as overlay or CD.

[0038] Figure 2 (a) illustrates a measuring device suitable for use in embodiments of the present invention. Figure 2 (b) illustrates the target T and the diffracted rays of the measurement radiation used to illuminate the target in more detail. The illustrated measurement device is of the type known as a dark-field measurement device. The measurement device can be a stand-alone device, or incorporated into a lithography apparatus LA (e.g., at a measurement station), or incorporated into a lithography unit LC. The optical axis having several branches throughout the device is indicated by the dashed line O. In this device, light emitted by the light source 11 (e.g., a xenon lamp) is guided onto the substrate W by an optical system including lenses 12, 14 and objective lens 16 via a beam splitter 15. These lenses are arranged in a double sequence of 4F. Different lens arrangements can be used, provided that it still provides an image of the substrate to the detector and simultaneously allows access to the intermediate pupil plane for spatial frequency filtering. Thus, by defining the spatial intensity distribution in the plane presenting the spatial spectrum of the substrate plane (here referred to as the (conjugate) pupil plane), the range of angles at which radiation is incident on the substrate can be selected. Specifically, this can be accomplished by inserting an aperture plate 13 of suitable form between lenses 12 and 14, in the plane of the rear-projected image that serves as the pupil plane of the objective lenses. In the illustrated example, the aperture plate 13 has different forms, labeled 13N and 13S, allowing for the selection of different illumination modes. The illumination system in this example forms an off-axis illumination mode. In the first illumination mode, aperture plate 13N provides off-axis illumination from a specified direction, designated "North" for descriptive purposes only. In the second illumination mode, aperture plate 13S is used to provide similar illumination, but from the opposite direction, labeled "South". Other illumination modes are also possible by using different apertures. The remainder of the pupil plane is ideally dark, as any unwanted light outside the desired illumination mode will interfere with the desired measurement signal.

[0039] like Figure 2As shown in (b), the target T is positioned such that the substrate W is perpendicular to the optical axis O of the objective lens 16. The substrate W may be supported by a support (not shown). The ray of measurement radiation I striking the target T from an angle offset from the optical axis O produces a zero-order ray (solid line 0) and two first-order rays (dot-chain +1 and double dot-chain -1). It should be remembered that, using an overfilled small target, these rays are merely one of many parallel rays covering the area of ​​the substrate that includes the measurement target T and other features. Due to the limited width of the aperture in plate 13 (necessary to allow a useful amount of light to enter), the incident ray I will actually occupy a certain angular range, and the diffracted rays 0 and +1 / -1 will spread out slightly. According to the dot spread function of the small target, each order +1 and -1 will further spread over a certain angular range, rather than a single ideal ray as shown. Note that the grating spacing and illumination angle of the target can be designed or adjusted so that the first-order rays entering the objective lens are closely aligned with the central optical axis. Figure 2 The rays illustrated in (a) and 2(b) are shown slightly off the optical axis, purely to make them easier to distinguish in the illustrations.

[0040] At least the 0th and +1st orders diffracted by the target T on the substrate W are collected by objective lens 16 and guided back by beam splitter 15. (Back) Figure 2 (a) The first and second illumination modes are illustrated by specifying the opposing apertures on the diameter, marked as North (N) and South (S). When the incident ray I for measuring radiation comes from the north side of the optical axis (i.e., when the first illumination mode is applied using aperture plate 13N), the +1 diffraction ray, marked +1 (N), enters the objective lens 16. Conversely, when the second illumination mode is applied using aperture plate 13S, the -1 diffraction ray (marked -1 (S)) is the diffraction ray entering the lens 16.

[0041] The second beam splitter 17 divides the diffracted beam into two measurement branches. In the first measurement branch, the optical system 18 uses the zeroth-order and first-order diffracted beams to form the diffraction spectrum (pupil plane image) of the target on the first sensor 19 (e.g., a CCD or CMOS sensor). Each diffraction order hits a different point on the sensor, allowing image processing to compare and contrast multiple orders. The pupil plane image captured by the sensor 19 can be used for many measurement purposes, such as the reconstruction used in the methods described herein. The pupil plane image can also be used for focusing measurement devices and / or normalizing the intensity measurement of the first-order beam.

[0042] In the second measurement branch, optical systems 20 and 22 form an image of the target T on sensor 23 (e.g., a CCD or CMOS sensor). In this second measurement branch, an aperture stop 21 is positioned in a plane conjugate to the pupil plane. The aperture stop 21 blocks the zero-order diffracted beam, ensuring that the target image formed on sensor 23 is formed only by the -1 or +1 first-order beam. The image captured by sensors 19 and 23 is output to a processor PU that processes the image; the functionality of the processor PU will depend on the specific type of measurement performed. Note that the term "image" used herein is broad. If only one of the -1 or +1 orders exists, such an image with grating lines will not be formed.

[0043] Figure 2 The specific forms of the aperture plate 13 and field stop 21 shown are purely illustrative. In another embodiment of the invention, on-axis illumination of the target is used, and an aperture stop with an off-axis aperture is used to essentially deliver only a first-order diffracted beam to the sensor. In other embodiments, second-order, third-order, and higher-order beams can be used in the measurement. Figure 2 (not shown in the image), replacing the first-order beam or other beams besides the first-order beam.

[0044] The target T may include multiple gratings with different overlay offsets to facilitate the measurement of overlay between multiple layers, where different portions of a composite grating are formed in the multiple layers. The gratings may also differ in their orientation to diffract incident radiation in the X and Y directions. In one example, the target may include two X-direction gratings with offset overlay offsets of +d and -d, and a Y-direction grating with offset overlay offsets of +d and -d. Separate images of these gratings can be identified in an image captured by sensor 23. Once the separate images of these gratings have been identified, the intensity of these individual images can be measured, for example, by averaging or summing the intensity values ​​of selected pixels within the identified regions. The intensity and / or other characteristics of the images can be compared with each other. These results can be combined to measure different parameters of the lithography process.

[0045] Various techniques can be used to improve the accuracy of pattern reproduction on a substrate. Accurate pattern reproduction on a substrate is not the only concern in IC manufacturing. Another concern is yield, which typically measures how many functional devices a device manufacturer or device fabrication process can produce per substrate. Various methods can be employed to increase yield. One such method attempts to make device production (e.g., imaging a portion of a design layout onto a substrate using a lithography apparatus such as a scanner) more tolerant of perturbations in at least one of the processing parameters during substrate processing (e.g., during the process of imaging a portion of the design layout onto a substrate using a lithography apparatus). The concept of overlay process windows (OPW) is a useful tool for this approach. Device (e.g., IC) production may include additional steps such as substrate measurement before, after, or during imaging; substrate loading or unloading; loading or unloading of the patterning apparatus; positioning the die under the projection optics before exposure; stepping from one die to another; etc. Furthermore, various patterns on the patterning apparatus can have different process windows (i.e., a space of process parameter values ​​within which patterns that are within specifications will be produced). Examples of pattern specifications associated with potential system defects include necking, line pullback, line thinning, CD error, edge placement error, overlap, resist top loss, resist undercut, and / or bridging. The process windows of all or some patterns (typically patterns within a specific region) on a patterning apparatus can be obtained by merging (e.g., overlapping) the process windows of each individual pattern. Therefore, these process windows of patterns are referred to as overlapping process windows. The boundary of the OPW may contain the boundaries of the process windows of some individual patterns. In other words, these individual patterns constrain the OPW. These individual patterns may be referred to as “hot spots” or “critical features,” and these terms are used interchangeably herein. Focusing on hot spots is possible and generally economical when controlling the lithography process. When hot spots are defect-free, it is likely that all patterns are defect-free. Imaging becomes more tolerant of perturbations when the processing parameter values ​​are closer to the OPW if the values ​​are outside the OPW, or when the processing parameter values ​​are further away from the OPW boundary if the values ​​are within the OPW.

[0046] Figure 3Exemplary sources of processing parameters 350 are shown. One source may be data 310 from the processing apparatus, such as parameters of the source, projection optics, substrate stage, etc., parameters of the lithography apparatus, parameters of the track, etc. Another source may be data 320 from various substrate measurement tools, such as substrate height maps, focus maps, critical dimension uniformity (CDU) maps, etc. Data 320 may be obtained before the applicable substrate undergoes a step to prevent substrate reprocessing (e.g., development). Another source may be data 330 from one or more patterning apparatus measurement tools, patterning apparatus CDU maps, variations in patterning apparatus (e.g., mask) film stack parameters, etc. Yet another source may be data 340 from the operator of the processing apparatus.

[0047] Figure 4 The concept of OPW is schematically illustrated. For illustration, it is assumed that the region or grid element / pixel 400 on the patterning device has only two individual patterns 410 and 420. The region may include more patterns. The process windows for individual patterns 410 and 420 are 411 and 412, respectively. For illustration, it is assumed that the processing parameters only include focus (horizontal axis) and dosage (vertical axis). However, the processing parameters may include any suitable parameters. The OPW 450 of this region can be obtained by finding the overlap between process windows 411 and 412. OPW 450 in Figure 4 The area is represented as a shaded region. OPW 450 can have an irregular shape. However, to easily represent OPW and easily determine whether a set of processing parameter values ​​are within OPW, a “fitted OPW” (e.g., ellipse 460) can be used instead. The “fitted OPW” can be, for example, a maximal hyperellipse fitted inside OPW (e.g., an ellipse in the two-dimensional processing parameter space in this example, an ellipse in the three-dimensional processing parameter space, etc.). Using a “fitted OPW” tends to reduce computational cost but does not utilize the full size of the OPW.

[0048] The values ​​of the processing parameters can be selected such that they are far from the boundaries of the OPW or the fitted OPW, in order to reduce the chance of the processing parameters moving outside the OPW and thus causing defects and reducing yield. One method of selecting the values ​​of the processing parameters includes: (1) optimizing the lithography equipment (e.g., optimizing the source and projection optics) and optimizing the design layout before actual imaging, (2) determining the OPW or the fitted OPW (e.g., by simulation), and (3) determining a point in the space of the processing parameters that is as far away as possible from the boundaries of the OPW or the fitted OPW (this point may be referred to as the "center" of the OPW or the "center" of the fitted OPW). Figure 4In the example, point 455 is the point in the processing parameter space that is as far away as possible from the boundary of OPW 450, and point 465 is the point in the processing parameter space that is as far away as possible from the boundary of the fitted OPW 460. Points 455 and 465 can be referred to as nominal conditions. If, during or before imaging, the processing parameters are shifted toward or even beyond the boundary of the OPW, deviating from point 455 or point 465, it would be beneficial to ideally have the ability to achieve this shift and to perform appropriate corrections to bring the processing parameters back into the OPW and away from its boundary without interrupting imaging or other processing.

[0049] During or prior to actual imaging, processing parameters may be perturbed by a point that deviates as far as possible from the boundary of the OPW (Optically Surface-Mounted Work) or the boundary of the fitted OPW. For example, focus may change due to the topography of the substrate to be exposed, stage drift, deformation of the projection optics, etc.; dose may change due to drift in source intensity, dwell time, etc. Perturbations may be large enough to cause processing parameters to fall outside the OPW and thus potentially lead to defects. Various techniques can be used to identify and correct perturbed processing parameters. For example, if focus is perturbed, for instance, because a slightly elevated area of ​​the substrate relative to the rest of the substrate is exposed, the stage can be moved or tilted to compensate for the perturbation.

[0050] The control of photolithography processes is typically based on feedback or feedforward measurements, which are then modeled using, for example, inter-field (cross-substrate fingerprint) or intra-field (cross-field fingerprint) models. Within the die, separate functional regions can exist, such as memory regions, logic regions, contact regions, etc. Each different functional region, or different functional region type, can have a different process window, and each process window has a different process window center. For example, different functional region types can have different heights, and therefore different optimal focus settings. Moreover, different functional region types may have different structural complexities, and therefore different focus tolerances (focus process windows) around each optimal focus. However, due to the limitations of control grid resolution, each of these different functional regions can typically be formed using the same focus (or dose or position, etc.) settings.

[0051] Lithography control can typically be performed based on measurements of a previously formed structure, using offline calculations of one or more setpoint corrections for one or more specific degrees of freedom. Setpoint corrections can include corrections to specific process parameters and can include corrections to the settings of specific degrees of freedom to compensate for any drift or error, keeping the measured process parameters within specifications (e.g., within permissible variations from the optimal setpoint or optimal value; e.g., OPW or process window). For example, a critical process parameter is focus, and focus errors themselves can manifest in defective structures formed on the substrate. In a typical focus control loop, a focus feedback method can be used. This method can include a measurement step that measures the focus setup used on a structure formed, for example, using a diffraction-based focusing (DBF) technique, in which a target with focus-dependent asymmetry is formed, such that the focus setup can then be determined by measuring the asymmetry on the target. The measured focus setup can then be used to determine corrections to the lithography process offline; for example, a positional correction of one or both of the mask stage or substrate stage used to correct focus shift (defocus). Such offline position correction can then be communicated to the scanner as a setpoint optimal focus correction or correction configuration scheme for direct actuation by the scanner. Measurements can be obtained on multiple batches, where an average optimal focus correction (across multiple batches) is applied to each substrate in one or more subsequent batches. For example, a control method is described in EP3495888, which is incorporated herein by reference.

[0052] Figure 5This method is illustrated. It shows product information 505 such as product layout, illumination pattern, product micro-morphology, etc., and measurement data 510 (e.g., defocus data or overlay data measured from a previously produced substrate) fed to an offline processing unit 515 executing optimization algorithm 520. The output of optimization algorithm 520 includes one or more setpoint corrections or correction configuration schemes 525, such as actuators for controlling the positioning of the mask stage and / or substrate stage within scanner 535. Setpoint corrections 525 typically include simple correction offsets calculated to compensate for any offset errors (e.g., defocus, dose, or overlay offset errors) included in the measurement data 510. Corrections for controlling the positioning of the mask stage and / or substrate stage can be, for example, control corrections in any direction (i.e., in the x, y, and / or z directions), where x and y define a substrate plane, and z is perpendicular to that plane. More specifically, they can include x / y direction corrections for overlay / alignment errors, and / or z direction corrections for focusing errors. Control algorithm 540 (e.g., a leveling algorithm) uses substrate-specific or online measurement data 550 to calculate control setpoint 545. For example, leveling data (e.g., a wafer height map) can be used to calculate a leveling exposure trajectory (e.g., determining the relative movement or acceleration distribution for the positioning of the substrate stage relative to the mask stage during a photolithography process) and output the position setpoint 545 of the scanner actuator. Scanner 535 equally applies a setpoint correction (offset) 525 directly to the calculated setpoint 545 for each substrate.

[0053] In other embodiments, these process parameters can be optimized in real time to determine corrections (e.g., corrected setpoints) on a per-substrate and / or per-layer basis. Therefore, instead of calculating setpoint corrections offline based on (e.g., offline measurements) and feeding those corrections forward to the scanner, optimized sub-configurations (e.g., suitable optimization functions) can be calculated based on offline measurements, utilizing the actual optimization and calculated setpoints performed within the scanner using the results of measurements on any of each substrate (with additional setpoint corrections optionally calculated offline).

[0054] Conventional optimization strategies may include least-squares minimization or other minimization methods, which apply average optimization across the substrate based on the difference or residual from the actual value and the setpoint value. Another strategy that may have advantages over least-squares strategies may include “gain-specification die” optimization. This aims to maximize the number of dies within specifications, rather than the total or average residual across the substrate. Accordingly, “gain-specification die” optimization uses existing knowledge of the product (die layout) when optimizing process parameters. Least-squares optimization typically treats each location equally, regardless of the die layout. Because of this, least-squares optimization may be preferable to corrections that “only” result in four non-specification locations (but each in a different die) rather than corrections that have seven non-specification locations but only affect two dies (e.g., one die with four defects and the other with three defects). However, since only a single defect will tend to make a die defective, maximizing the number of defect-free dies (i.e., gain-specification dies) is ultimately more important than simply minimizing the number of defects or the average residual per substrate.

[0055] One type of specification-compliant die optimization may include optimizing the maximum absolute value (max abs) of each die. This maximum absolute value optimization minimizes the maximum deviation of performance parameters from the control objective. This produces a solution, but does not prevent dies from going out of specification (it only attempts to minimize the number of specification-compliant dies). Accordingly, other strategies may be preferred, such as constraint-based strategies, where the objective is defined by including adding constraints to the optimization problem; for example, such that one or more parameters or metrics are constrained within limits; that is, they are not allowed to go out of specification.

[0056] However, other constraints exist, such as physical constraints of the system, including constraints on field size and the variability of each field, constraints on slit width and the variability of each slit, and actuation constraints on how the stage can physically move. As a result, for some constrained optimization problems, there is no simple solution: that is, the optimization problem is infeasible, making it impossible to find a solution that satisfies all constraints. In these cases, the optimization solver cannot simply produce results and send configuration schemes to, for example, a scanner.

[0057] To understand how patterning processes work, computational lithography can be used to simulate how one or more aspects of the patterning process "work." Therefore, appropriate computational lithography software can predict one or more characteristics of pattern formation on a substrate, such as the predicted CD of the pattern, the predicted profile, etc., and may do so at different stages of pattern formation. This can include various models that model one or more aspects of the patterning process. For example, an illumination model can represent the optical characteristics of illumination (including the radiation intensity distribution and / or phase distribution). A projection optics model can represent the optical characteristics of projection optics (including variations in the radiation intensity distribution and / or phase distribution caused by projection optics). A design layout model can represent the optical characteristics of a design layout (including variations in the radiation intensity distribution and / or phase distribution caused by a given design layout, which is a representation of the arrangement of features on a patterning apparatus or a representation of the arrangement of features formed by the patterning apparatus).

[0058] Illumination models, projection optics models, and design layout models can be used to simulate space images. Resist models can be used to simulate resist images from space images. Photolithography simulations can, for example, predict contours and / or CDs in resist images.

[0059] More specifically, note that the illumination model can represent the optical characteristics of the illumination, including but not limited to NA-sigma(σ) settings and any particular illumination shape (e.g., off-axis illumination such as ring, quadrupole, dipole, etc.). The projection optics model can represent the optical characteristics of the projection optics, including, for example, aberrations, distortion, refractive index, physical size or dimension, etc. The design layout model can also represent one or more physical characteristics of the physical patterning apparatus, as described, for example, in U.S. Patent No. 7,587,704, which is incorporated herein by reference in its entirety. The optical characteristics associated with the lithographic projection apparatus (e.g., characteristics of the illumination, patterning apparatus, and projection optics) indicate a spatial image. Since the patterning apparatus used in the lithographic projection apparatus can be varied, it is desirable to separate the optical characteristics of the patterning apparatus from the optical characteristics of the rest of the lithographic projection apparatus, which includes at least the illumination and projection optics, and thus design layout models.

[0060] Resin models can be used to calculate resist images from spatial images, examples of which can be found in U.S. Patent No. 8,200,468, which is incorporated herein by reference in its entirety. Resin models are generally only related to the properties of the resist layer (e.g., the effects of chemical processes that occur during exposure, post-exposure baking, and / or development).

[0061] The purpose of simulation can be to accurately predict, for example, edge locations, spatial image intensity slope, CD and / or contours, which can then be compared with the intended design. The intended design is typically defined as the pre-OPC design layout.

[0062] Based on the design layout, one or more parts can be identified, referred to as "segments". In one embodiment, a set of segments is extracted that represent complex patterns in the design layout (typically around 50 to 1000 segments, although any number of segments can be used). As those skilled in the art will understand, these patterns or segments represent small parts of the design (e.g., circuits, cells, etc.), and in particular, segments represent small parts that require special attention and / or verification. In other words, a segment can be a part of the design layout, or a similar behavior to a part of the design layout, where key features or hotspots are identified through experience, through trial and error, or by running full-chip simulations. Segments typically contain one or more test patterns or measurement patterns.

[0063] In some examples, simulation and modeling can be used to configure one or more features of a patterned device pattern (e.g., performing optical proximity correction), one or more features of illumination (e.g., changing one or more properties of the spatial / angular intensity distribution of illumination, such as changing shape), and / or one or more features of the projection optics (e.g., numerical aperture, etc.). This configuration can generally be referred to as mask optimization, source optimization, and projection optimization, respectively. Such optimizations can be performed individually or combined in different ways. One such example is source mask optimization (SMO), which involves configuring one or more features of the patterned device pattern and one or more features of the illumination. The optimization technique can focus on one or more segments. Optimization can be achieved using simulations described herein to generate various parameter values.

[0064] Identifying features or combinations of integrated circuit (IC) designs that are more likely to fail or generate defects (e.g., hot spots) is important. EPE defects have multilayered characteristics and are often caused by one or more CD and / or OVL variations. Methods for accurately identifying and sequencing these hot spots prior to wafer fabrication, such as using computational lithography, are highly needed. The interactions of EPE-specific failure mechanisms between layers (which originate from factors such as interlayer geometry, crosstalk of contributors, etc.) impose additional constraints on EPE process windows and hot spot detection and sequencing that are currently uncaptured or unconsidered.

[0065] The aforementioned hotspot detection based on computational lithography is currently based on calculations involving a single layer. However, such single-layer hotspot detection may often be insufficient to represent multi-layer products because: a) single-layer hotspots may not necessarily be a problem for multi-layer hotspots (i.e., the functionality of multi-layer products); b) single-layer performance may be constrained by the variability of other layer profiles (e.g., interlayer crosstalk occurs). For hotspot detection, it is possible to directly measure the edge placement error (EPE) from the actual product (e.g., using multilayer electron beam inspection); however, electron beam inspection is too slow for high-volume manufacturing.

[0066] Therefore, hotspot detection and / or sequencing are proposed based on constraints of multidimensional, multi-layer process windows (e.g., focusing, exposure, and overlay or FEO PW), which take into account process crosstalk and multi-layer interactions. More specifically, the method may include performing hotspot detection using a multidimensional, multi-layer process window that takes into account constraints on the contour position / size of all layers of interest, such as interactions between layers and / or interactions between process condition parameters (e.g., overlay, dosage, and focusing or FEO space).

[0067] For example, the method may include obtaining multilayer profile data (which may include measured and / or simulated profiles) for a number of process conditions, many of which may vary in more than two aspects, such as focus, dosage, overlay, or any other process parameter. Other process parameters may include, for example, any controllable scanner parameters (such as aberrations), or other non-scanner parameters of the IC manufacturing process (e.g., the duration and temperature of the etching / patterning process). It is understood that any crosstalk between layers and / or process parameters will naturally be taken into account in the experimental profile, which is extracted from images obtained via measurements (e.g., via SEM measurements and profile extraction algorithms). Additionally, computational lithography models and thus simulated profiles may also be designed to account for such crosstalk. Current methods that do not account for such crosstalk may lead to an overestimation of OPW and thus miss critical hotspots, as well as a mismatch between hotspot prediction and verification.

[0068] A specific example of crosstalk that is currently unconsidered but can be considered using the methods disclosed herein is overlaying of imaging crosstalk. Overlay settings for multiple layers in a specific EPE use case can be used to estimate the MSD (Moving Standard Deviation), which is derived from the overlay-driven (or moving average MA-driven) stage, lens, etc. The resulting MSD can be used as input to an imaging model to predict critical size uniformity (CDU), local critical size uniformity (LCDU), etc., and the resulting MSD is therefore also overlay-driven. Accordingly, strong overlay correction (e.g., a third-level correction through the slit) will increase the MSD (and thus the fading error) and increase the LCDU; therefore, expanding the multidimensional, multilayer process window in the overlay dimension, depending on the chosen process settings and overlay correction strategy, will result in a reduction of the multidimensional, multilayer process window in the CD dimension. This crosstalk is naturally considered in the experimental profile extracted from measurements.

[0069] Measured and / or simulated profiles can be stacked under each process condition. Profile stacking is described in PCT Publication WO2020094286A1 (incorporated herein by reference) and can be used to derive profile variability. Methods may include obtaining one or more images of portions of a substrate on each of multiple layers of the substrate. Variation measures such as overlay allowances can be calculated based on characteristics of the features, such as the profiles of the features. Images can be stacked (e.g., aligned and overlaid) as follows: images relating to one or more corresponding images of the same feature in different layers of the substrate; and / or images relating to multiple features on the same layer of the substrate. Based on one or more reference locations in each image or overlaid onto one or more reference locations on each image, an alignment process can align the images such that there is no overlay error between the images. For example, an alignment process may include aligning the target designs of features in the images such that there is no overlay error between target designs. The alignment process may be based on aligning the images according to expected design data (e.g., GDS data). The effect of performing an alignment process is to remove the effects of any overlay error between different images. Overlay allowance is a measure of the random variation of features in a stack of aligned images. Overlay allowance can be calculated based on the differences between the contours of corresponding features in aligned versions of an image. It can also be calculated based on the target contour of a feature. For example, for each image, overlay allowance can be calculated by comparing a feature in the image to its target. The differences between the contours of a feature in one image and those in other images, as well as the target contour of the feature, can be determined by several well-known image-specific metrics such as critical size uniformity (CDU), linewidth roughness (LWR), critical size amplitude, and placement error.

[0070] Based on performance data (e.g., overlay data or other performance parameter data) and failure mode data for each process condition, a failure count (e.g., a count of instances that do not meet constraints) is determined for each process condition. The failure mode data can be EPE failure mode data that includes multi-layer profile constraints describing the profiles and combinations of indicative (non-generative) defects across multiple layers. In this way, a multi-layer process window (PW) based on multidimensional EPE failure counts can be determined, taking into account the interaction between layers and individual process conditions. Such a PW window can be defined as a region of process conditions where no failures are predicted or the failure probability is below a threshold.

[0071] Based on this multi-layered process window, hotspots can be identified; for example, regions comprising small process window volumes or spaces, or regions associated with small process window volumes or spaces. Furthermore, the multi-layered OPW provides a method for guiding correction strategies (e.g., co-optimization in the FEO space), such as by ranking EPE correction strategies. This offers the additional advantage of hotspot identification and verification based on the same EPE.

[0072] Accordingly, a first embodiment can describe a method for determining a process window, comprising: obtaining contour data of features provided to a substrate across multiple layers; obtaining fault mode data, the fault mode data including constraints on the contour data across the multiple layers; obtaining a plurality of process conditions associated with providing features across the multiple layers; determining a fault count for each process condition by associating the contour data with its corresponding process conditions and subsequently applying constraints to the contour data; and associating each process condition with its corresponding fault count to obtain a process window.

[0073] Hotspots can be identified as features that do not include multi-layer process windows or include small multi-layer process windows. For example, a hotspot can be identified as any feature that includes multi-layer process windows smaller than a threshold. Alternatively or additionally, all features can be sorted according to the predicted multi-layer process window size, where those n features with the smallest process window are identified as hotspots (where n is an arbitrary number). Based on the identified hotspots, the entire EPE process window can be found as an overlapping multidimensional (e.g., FEO), multi-layer volume of all identified hotspots.

[0074] Multidimensional, multi-layered PWs can help troubleshoot by pointing to the most critical contributors limiting the PW (e.g., layer 1 or layer 2 CD, OVLx or OVLy), thus enabling immediate corrective action.

[0075] The same approach can be used for both simulated and measured profile data. In the previous example, the profile data could include simulated profile data generated by computational lithography. In this way, computational lithography hotspot prediction is possible. In this approach, simulated profiles and overlay fingerprints obtained under different process conditions (both measured and simulated) can be used as inputs for lithography simulation prior to wafer fabrication. Profile-based analysis for pixel sizes of 1 nm and below is possible for accurate lithography simulation. For measured profile data and wafer-based hotspot detection, measured EPE profiles and overlays measured under process conditions (e.g., in-device measurement) can be inputs for hotspot verification. This approach can be used for high-volume manufacturing with simulated profiles and / or sufficiently fast EPE profile measurements.

[0076] The proposed hotspot detection and ranking method can be used to rank EPE solutions and process options (settings), wherein the overlapping multilayer process window volume is predicted in each solution, and the solutions may include, for example, different imaging, overlap correction strategies, resists, etc.

[0077] Figure 6 This is a flowchart describing a method according to one embodiment. In a computational lithography (CL) process, process condition data 600 (i.e., describing different process conditions) and multilayer layout data 605 (e.g., EPE layout data after OPC (Optical Proximity Correction) for multiple layers) are fed into a lithography model 610, which includes modeling of crosstalk effects, localization effects, etc., to generate simulated contour data 615 (e.g., including contours for each layer and for each process condition, categorized by process condition). Alternatively or additionally, a wafer metrology (WM) process may include exposing multiple layers of interest on a wafer 625 for each process condition 600. Metrology 630 (e.g., imaging and contour extraction) is then performed on these wafers (each layer) to obtain measured contour data 635 including contours for each layer and for each process condition. The measured contour data 635 may then be stacked 620 for each process condition. Stacked measured profile data 635 and / or simulated profile data 615, together with measured and / or simulated performance data 645 (e.g., overlay data / fingerprints possibly obtained from Monte Carlo simulations or worst-case specification values) and EPE failure mode data 650 (e.g., multilayer constraints driven by EPE failure modes), are used in step 640 to identify and count failures for each process condition. Such a step can be performed using a lithographic manufacturability inspection (LMC) method with EPE failure mode detection. The final step 655 may include one or more of the following operations: • Hotspot detection, detected as features (e.g., causing a small process window) at some PW(multiple) locations that violate EPE constraints;

[0078] • Determine the PW of EPE in multidimensional space (e.g., F, E, OVL for the layer of interest); • Sort EPE hotspots according to their PW;

[0079] • Overlapping PW calculations, which serve as inputs for process capability;

[0080] • The verification of the predicted hotspot results uses wafer data as feedback on the simulation accuracy.

[0081] The above description references non-scanner parameters. This will now be expanded upon. Failure mechanisms: Specific interactions between EPE layers (such as interlayer geometry, contributor crosstalk, etc.) are influenced by non-scanner components (such as masks and non-lithographic process steps). These impose additional constraints on EPE multidimensional, multilayer process windows, as well as hotspot detection and sequencing. Hotspots in multilayer EPE use cases can include crosstalk between layers and scanner and non-scanner parameters (the latter including, for example, mask pattern density and etch micro-load effects). By considering both scanner and non-scanner parameters used for hotspot prediction and detection, the aforementioned multi-parameter optimization in EPE control can be improved, thereby providing a safe correction or actuation space for the scanner knob (control) used to control the EPE.

[0082] For example, static masking within the field and potential low-frequency masking dynamics (e.g., due to surface degradation), as well as dynamic spatial and temporal non-scanner process variations, are significant contributors to EPE. Therefore, it is advantageous to include these in EPE hotspot detection methods, allowing them to be considered when defining safety calibrations for EPE control applications.

[0083] Therefore, a global EPE failure mechanism and geometry-specific hotspot detection are proposed, which can be based on a global simulation of the wafer shape, which responds to mask and / or non-scanner patterning process variations in addition to scanner patterning process variations. Crosstalk-aware simulation models (physical and / or empirical, e.g., based on machine learning methods) incorporating lithography parameters and external or non-lithography parameters can be used to predict the EPE's response to variations in scanner and non-scanner parameters. External / non-lithography parameters can include, for example, mask pattern density, surface transparency, and etch micro-load effects. The resulting process window can be referred to as the global multilayer, multidimensional process window (HMPW).

[0084] Figure 7 The illustration shows an example of a single-exposure cut based on a single-exposure line. In general, many lithographic and non-lithographic parameters can contribute to the EPE and are therefore part of the HMPW. The example shows a simplified HMPW scenario where dose and overlay contribute to the HMPW, but also considers the crosstalk between lithography-CD and etching.

[0085] Figure 7 (a) illustrates the first hotspot and potential failure mode, which can be termed the "mouse bite defect" of the next AA block. Dosage errors in layer A cause a reduction in the lateral space between blocks, which is amplified by the etch micro-load effect X-tk (crosstalk). Together with overlay errors, this results in the mouse bite defect MBF. The figure shows the blocks on mask M, and the exposed blocks stacked under each dose condition L-ST (only two conditions are shown for simplicity) (after photolithography / pre-etching). The next stage shows the stacked blocks AEI-ST after etching under each dose condition and etch condition (e.g., etch time). The upper figure is an example without crosstalk, and the lower figure illustrates the effect of crosstalk (e.g., due to micro-load). The stacked hole cutting step C-Si is shown for both the crosstalk-free and crosstalk-containing examples, followed by the same step with the effect of C-Si+OVL with overlay offset addition. The mouse bite defect MBF is evident in the example of crosstalk and overlay effects.

[0086] Figure 7 (b) The second hotspot and potential failure mode are illustrated, which can be referred to as the incomplete cut fault (ICF) of the AA line. (Flow and labeling are related to...) Figure 7 (a) Basically the same.

[0087] Figure 7 (c) is a simplified 2D process space diagram showing the overall multidimensional process window MBF-HMPW for mouse bites and the overall multidimensional process window ICF-HMPW for incomplete cut failure. The overlapping area is the overlapping HMPW used for the process. Actual process windows can be multidimensional and will therefore have more dimensions than the two-dimensional example shown in this simplified example.

[0088] Using this HMPW, hotspot detection and sequencing can be performed based on lithographic and non-lithographic parameters such as focus and dose, overlay, mask CD variations, and patterning process variations (e.g., lithographic bias, spacer deposition variations, etc.). HMPW assists in troubleshooting by pointing to the most critical contributors to insufficient overlap between individual hotspot volumes (e.g., mask, scanner, or patterning variations that limit PW). The results help initiate immediate corrective actions: such as volume centering and / or volume enhancement.

[0089] The proposed HMPW-based hotspot detection and ranking method can be used to rank EPE solutions and process options (settings) by determining the relationship between the predicted overlapping HMPW process window volume for each solution and cost and / or workload. This can take into account one or more of the following: different imaging options, mask options, overlay correction strategies, patterning process control, etc.

[0090] Intelligent sampling and / or training using Design of Experiments (DoE) techniques can be performed to characterize HMPW within a reasonable timeframe.

[0091] An HMPW library can be compiled that performs interpolation and dynamic expansion / learning based on data collected during wafer fabrication and inspection. This allows previously learned knowledge to be reused and accelerates the development of new HMPWs. Further embodiments using such a library will be described later.

[0092] The process for determining HMPW can be similar to Figure 6 The process is illustrated in the figure. Stacking step 620 is performed under HMPW conditions (but not overlay), while overlay offset / error (measured and / or simulated) is injected in step 640, thereby generating a new set of profiles before the fault count for each HMPW condition.

[0093] The methods described above provide multi-dimensional (e.g., FEO), multi-layer PW for sensing crosstalk. The methods can be specific to use cases and failure modes specific to the correct EPE detector. Furthermore, the same methods can be used for computational lithography-based hotspot prediction and wafer-based hotspot verification, making their results directly comparable. The methods can provide direct input to hotspot ranking and can assist in ranking process option scenarios for EPE improvement and control. The concept can be extended to include non-lithography parameters to determine HMPW.

[0094] In another embodiment, the concept of a design-aware actuation space (DAAS) will be described. DAAS encompasses all actuator configurations conforming to the OPW (e.g., the possible complete trajectory of multiple actuator setpoints during wafer exposure). In other words, DAAS describes an actuation constraint subspace or process space defined by the OPW, which is constrained by possible actuator configurations (i.e., those that can actually be actuated).

[0095] For example, an EUV scanner can use exposure dose and one or more tunable mirror elements to compensate for external disturbances in the manufacturing process for actuation in mask stage / wafer stage positioning. Currently, the scanner performs actuator range-aware optimization for all actuators during operation, including all in-situ measurement inputs (alignment / leveling). Actuator range awareness is provided by the scanner to the optimizer. The optimizer generates a "correction configuration scheme" without knowing the in-situ measurement inputs. The optimizer uses a fingerprint based on the relevant process environment and actuator range provided by the scanner for the desired correction for each field. The actuator range can be determined based on the software version / patch on the scanner and commercial interface options.

[0096] As already described, process correction can be designed to control edge placement error (EPE). This error can be controlled by a combination of conventional overlay, focusing, dosing, and aberration actuators. For example, a high-NA EUV system can use a scanning mirror actuation in conjunction with the scanning stage. Such actuation offers many correction possibilities, but may lead to other effects such as MSD error (e.g., fading) and higher-order aberrations, which, if not avoided, can degrade image performance.

[0097] It is possible that the actuator may be moved outside the range where all product features (especially hotspots) are printed (e.g., PW); there is no suitable intrinsic mechanism to enhance hotspot printability. Process windows (e.g., overlapping PW, OPW) for all hotspots can be calculated using known methods or methods disclosed in the first embodiment (e.g., multilayer OPW). OPW can be a multidimensional parameter space for all hotspots to be printed (e.g., dose, focus, MSD, aberration, etc.).

[0098] The actuator configuration of the scanner (e.g., in operation) should conform to OPW. Fingerprint information may optionally be added to anticipate the effects of actuator variations on dynamics (e.g., MSD) and inter-field / intra-field variations, thereby imposing additional constraints on the actuation solution. Accordingly, DAAS includes OPW constrained by possible actuator configurations conforming to OPW.

[0099] The complete actuator configuration conforming to OPW (the complete trajectory of multiple actuator setpoints during wafer exposure) is called the Design-Aware Actuation Space (DAAS). DAAS can be used as part of a constrained optimization problem for determining the control inputs of the actuators.

[0100] Accordingly, a method for configuring a plurality of actuators may include the following steps: obtaining a volume within a control parameter space associated with expected compliance with processing requirements; determining a subset of the volume based on actuation constraints imposed by the plurality of actuators; obtaining a configuration of the plurality of actuators, the configuration including actuator setpoints defined in the control parameter space; and using the subset to evaluate the configuration.

[0101] Such an approach could include performing design-aware optimization of all actuators in operation within the scanner, including all in-situ measurement inputs (e.g., alignment data, leveling data, wavefront measurement data, or more). Design awareness is provided to the scanner as an "optimization model," and can be provided via an application. The optimization model could include actuator constraints based on (e.g., simulated) lithography process windows. The optimization model could include a per-wafer / exposure-related fingerprint (based on the process environment). Design awareness could be based on full-mask simulation using computational lithography based on a hotspot list (e.g., pre-mask fabrication). The optimization model could optimize the cost function per die based on DAAS.

[0102] Data science techniques can be used to parameterize and classify the Design Actuation Space (DAAS). The DAAS can be unified with the physical actuator space defined by the latest available actuator range, allowing it to be updated. This approach allows for the compensation of drift in uncorrectable parameters with correctable parameters.

[0103] Design awareness can be achieved through actuation space simulation using computational lithography. Actuation space simulation can be performed on any number of the following control parameters: Zn (n = 2, 3, 4, 5, 6, 7, 8, 10, 11... and higher), MSD Zn (attenuation due to slit integration), dose, pupil (shape parameter), wavelength (multifocal imaging), and bandwidth (contrast control).

[0104] Using computational metrology, a hotspot list is tested for all actuable combinations of the aforementioned control parameters, where actuation can be limited to movements permitted only by the scanner hardware. The hotspot list can be identical to the hotspot list currently used for OPC (Surface Mount Technology) for Mask and Source Optimization (SMO) and for LMC (Low Motion Crush) of the OPC mask before wafer fabrication. Alternatively, the hotspot list can be a multi-layered hotspot list determined using any method from the first aspect. DAAS can be limited to all actuable parameter combinations through which all hotspots pass.

[0105] DAAS can be described, for example, in a parametric manner (e.g., a multidimensional elliptical surface or spline) or as a trained neural network.

[0106] Device feature sensitivity is not part of the design-aware optimization model: any combination of Zn movements is acceptable because the scanner does not coordinate itself. The scanner only knows the sensitivity of the alignment and reference markers to convert / interpret instantaneous in-situ measurements into Zn space.

[0107] Figure 8 Figures (a) and (b) illustrate the concept of DAAS. Each of these figures shows a two-dimensional process space (Zp-Zq space). Figure 8(a) shows the OPW (shaded area) of the Zp-Zq parameter space determined using known techniques or methods, such as those of the first embodiment. Reference Figure 8 (b) The actuable parameter space (actuable combinations) is described by the box APS (i.e., those combinations within the box are actuable). The overlapping area between the actuable parameter space APS and OPW is DAAS (dark shading).

[0108] Design-aware optimization may include searching to find the nearest point in the DAAS. For example, a correction request (in DAAS parameters) may be represented by a point CR. Optimization may find the nearest point within the DAAS or the design-aware correction DAC. This approach may include performing the following steps within the scanner:

[0109] First, the calibration request is converted into DAAS parameters. The scanner checks the latest available actuator range and combines it with the DAAS range to update the DAAS. The scanner determines whether a uniform space or DAAS exists; if not, the system will not actuate the request and will issue a warning. Assuming a DAAS exists, it determines whether the requested calibration is within the DAAS; if so, the calibration is actuated as requested. If the requested calibration is not within the DAAS, the nearest accessible point within the DAAS is identified and actuated. Finally, the deviation from the requested actuation can be calculated. The report is a warning.

[0110] Figure 8 (c) illustrates that when an uncorrectable parameter drift pushes the process out of the DAAS or OPW, an actuation correction t1 along another dimension (e.g., via correction of another parameter) can bring the process back into the DAAS.

[0111] DAAS can include "uncorrectable" parameters that can drift and can be measured by in-situ measurements (e.g., wavefront sensors on a wafer stage). Figure 8 In (c), the uncorrectable parameter Zp limits the 1D DAASt0 at the first time, with correction capability only in the Zq direction (of course, a practical example could have more dimensions). The correction c0 at time t0 is within the DAAS and therefore within the OPW. Between time t0 and time t1, due to the drift of the uncorrectable parameter, the correction c0' drifts outside the DAAS. However, correction using the parameter Zq (or, in a multidimensional example, a combination of more than one other parameter) can bring the correction c1 back into the DAAS t1. If the drift of the uncorrectable parameter makes it impossible to return the correction c1' to the DAAS t1', a warning can be issued and the process stopped (system shutdown).

[0112] Figure 8Figures (d) and (e) illustrate additional (optional) optimization model refinements. For example, refer to... Figure 8 (d) The optimization model within the scanner can attempt to keep the system state close to the “center” or initial state S in the DAAS to prevent the need for sudden adjustments (such as X to E) when an uncorrectable parameter X moves out of the region.

[0113] Figure 8 The shaded area in (d) can represent regions where external processes fail for Zq; that is, it represents actuation spaces that are not preferred due to constraints from other process steps (crosstalk with Zq). Drift compensation for Zp using Zq should be far from these boundaries to leave sufficient control margin for external processes. For example, the system can learn how to adjust DAAS to conform to such new or additional constraints.

[0114] There is a risk that when the failure of the external process is not part of the known design awareness space, the external process (which only cares about Zq) will pick up the drift correction M and (with delay) request to move it back to the initial state C when the system has already corrected itself A.

[0115] Figure 8 (e) This diagram illustrates several options for mitigating crosstalk with external processes. In one embodiment, the system may not use correctable parameters affecting the external process to compensate for uncorrectable parameters, but instead issue a warning only when the design-aware space is exceeded, as shown at points S, M, and E. In another option, the system may learn of any new constraints from the external process and modify the design-aware actuator range during operation (e.g., based on known rules or self-learning) to avoid crosstalk with the external process. This approach can generate a new boundary NB to at least a portion of the DAAS. In yet another option, the system may consider internal adjustments (e.g., points M and A) since a previous exposure (the exposure on which external corrections are based). The optimization model will then learn of the state changes since the last exposure M, which addresses the problem raised in the previous paragraph.

[0116] It is understood that the DAAS can change if external processes or parameters change (e.g., different etcher settings or different OPC settings). In one embodiment, it is recommended to select an appropriate process window for a specific external configuration or setting. This approach may include selecting a process window from a library of process windows, each corresponding to a specific configuration or combination of external / non-lithographic parameter settings (e.g., and lithographic or scanner parameter settings). Accordingly, based on changes in external settings (e.g., new etcher settings or OPC settings / mask design), an appropriate process window can be selected from the library, for example, by a controller external to the scanner. The controller or scanner can then use this process window to determine the DAAS (e.g., using the methods already described during operation).

[0117] This invention assumes that a suitable process windowing method is available, which describes the multidimensional volume of all parameters (lithographic and non-lithographic) that affect edge placement errors. Such a method can be the already described Holistic Multidimensional Process Window (HMPW) method, and accordingly, the library can be a library of HMPW. To perform interpolation, the library can be parameterized or trained on a neural network or any other machine learning technique capable of classifying multidimensional process window volumes.

[0118] Figure 9 This arrangement is illustrated. The first process window PW is shown. 1,1 (The sum of the shaded areas) and DAAS 1,1 (Darker shaded area) This involves the initial settings of external process parameter P1 and source mask optimization parameter SMO1. For different settings of external process parameter P1, the process window PW for the same process and layer... 2,1 and DAAS DAAS 2,1 They are shown as different. Similarly, for different settings of the SMO parameter SMO2, the process window PW for the same process and layer is different. 1,2 and DAAS DAAS 1,2 This is shown again as distinct. A library LIB can be constructed and used, comprising process windows (e.g., HMPW) for all relevant combinations of scanner / lithography parameters and external / non-lithography parameters, including upstream parameters (e.g., those that have an impact before exposure, such as those related to mask design and / or optimization) and / or downstream parameters (e.g., those that have an impact after exposure, such as those related to further substrate processing steps, such as etching steps). Each of these combinations of scanner parameters and external parameters can be described as an operating point.

[0119] Based on the acceptable EPE and desired correction capability of the relevant external processes, appropriate (lithographic and non-lithographic) operating points and corresponding HMPWs can be selected from the HMPW library. Accordingly, given HMPWs that may be related to upstream (e.g., including mask OPC / SMO parameters) and / or downstream actuators, an economically optimal operating point can be defined for design-aware actuator control of the scanner actuator for each wafer. DAAS for scanner actuators can be implemented in operation at the latest known process operating points.

[0120] A concrete example of using OPC optimization, which is currently typically performed to minimize EPE. However, using the concepts disclosed in this embodiment, OPC optimization can include balancing OPC workload (mask optimization) with EPE gain. For the globally optimal EPE, OPC optimization is not necessarily pursued, but rather aimed at keeping the EPE within specifications; for example, OPC is a tool to ensure printability / yield, but the OPC may not necessarily optimize for an EPE exceeding that specification. This less complex / less demanding OPC strategy simplifies the OPC design process, resulting in faster mask design cycles and cheaper masks at the cost of acceptable performance loss (EPE), which remains within DAAS and is therefore expected. Process and design awareness during OPC can also provide greater actuation space. Alternatively or additionally, OPC optimization can be aimed at ensuring DAAS is maximized without necessarily further optimizing performance metrics; for example, to ensure sufficient margin to compensate for anticipated variations in the process or lithography equipment. In this way, OPC optimization can enhance the correction potential of scanners or other non-lithography equipment. For example, by reducing the contrast / PW of one or more features that typically vary in downstream etching processes, the scanner's sensitivity to dose shifts can be increased, providing more compensation capability for downstream etching processes through the scanner. Alternatively, the contrast / PW can be increased to allow for more dose-related errors in the scanner.

[0121] Given the latest mask (OPC) and upstream process (UP) and downstream process (DP) operating points in the HMPW library, a subspace containing the design-aware actuator space (DAAS) for the scanner can be determined. The scanner can perform design-aware optimizations for all actuators during operation, including all other last-minute in-situ measurement inputs (e.g., alignment / leveling) corrected for known and upstream correctable upstream disturbances (computational measurements).

[0122] Figure 10This is a flowchart describing the control aspects proposed in this embodiment. The external controller CTL provides the HPMW subspace HPMW SS as a DAAS to the internal scanner SC for controlling the lithography process. Upstream control of one or more upstream processes UP is performed by the upstream controller US CTL, and downstream control of one or more downstream processes DP is performed by the downstream controller DS CTL. Each of these controllers may include the same controller or other controllers. Data from upstream measurements UM or in-situ measurements can be fed to the external controller CTL and / or the upstream controller US CTL. Calculation measurements CM can be performed to determine the correction for upstream interference estimated using upstream measurements UM. Downstream measurements (e.g., AEI / ACI EPE measurements) can also be performed on the substrate after downstream processes(DP); data from downstream measurements can be fed to the external controller CTL and / or the downstream controller DS CTL.

[0123] It can be assumed that the upstream measurement UM describes upstream process effects that can potentially be corrected for by upstream and / or downstream process parameters. Therefore, these contributions can be removed before the data is used to control the scanner SC so that double correction is not performed.

[0124] Upstream process UP can be compensated within the scanner SC as feedforward FF correction, and / or can also be compensated by upstream process UP through feedback FB to subsequent batches. Upstream process can be, for example, mask writing.

[0125] Regarding downstream interference: The upstream measurement UM does not contain any downstream-related interference. The downstream (EPE) measurement DM contains downstream-related interference. Based on the downstream EPE measurement DM, the external controller CTL can issue a compensation request to the scanner. This compensation request includes compensation for downstream induced interference that cannot be corrected by (or will not be corrected by) the downstream calibration mechanism, but does not include compensation for downstream induced interference that will be corrected by the downstream calibration mechanism. This request may include a design-aware actuation subspace for general scanner parameters.

[0126] For upstream interference: Upstream and downstream measurements include upstream-related interference. Based on the downstream measurement DM, the external controller can issue a compensation request to the scanner. This request includes compensation for upstream induced interference that cannot be corrected by (or will not be corrected by) upstream or downstream calibration mechanisms, but does not include compensation for upstream induced interference that will be corrected by upstream and / or downstream calibration mechanisms. Similarly, the request can be a design-aware actuation subspace of general scanner parameters.

[0127] Based on upstream measurements, the computational measurement CM can issue a (in operation) calibration request to the scanner SC. This calibration request includes compensation for upstream induced interference that cannot be calibrated by (or will not be calibrated by) upstream or downstream calibration mechanisms, but does not include compensation for upstream interference that is included in a request already requested by an external controller.

[0128] Figure 11 Specific control aspects of the disclosed embodiments are illustrated. Figure 11 (a) is a process space diagram of the scanner parameter Zq relative to the downstream parameter DP. This diagram shows the variation in the value of the downstream parameter (or more generally, any external parameter); for example, values ​​DP1 to DP2 generate different permissible actuation ranges ZqR1 and ZqR2 for the scanner parameter (as shown by the white lines corresponding to each value). Therefore, the external control sets the operating point for the downstream parameter. This sets the actuation ranges ZqR1 and ZqR2 for the scanner parameter.

[0129] refer to Figure 11 (b) is a flowchart, and based on the assumption that feedback from the downstream process DP will be slow, the downstream process operating point is used by the external controller CTL to determine the scanner SC range ZqR based on a subspace of the overall design-aware actuation space (HMPW). This can be done, for example, when determining the correction +DP for the downstream process DP based on the downstream measurement DM.

[0130] Further embodiments are disclosed in the following list of numbered clauses:

[0131] 1. A method for determining a process window within a process space for a manufacturing process, said process space being defined by a plurality of process parameters, said process window being a subspace within said process space associated with expected compliance with processing requirements; the method comprising:

[0132] For each of a plurality of process conditions associated with providing features across multiple layers, profile data relating to the features to be provided to a substrate across the plurality of layers is obtained; failure mode data describing constraints on the profile data of the plurality of layers is obtained; a failure count for each process condition is determined by applying the failure mode data to the profile data; and the process window is determined by associating each process condition with its corresponding failure count.

[0133] 2. The method according to Clause 1, wherein the process window is determined to include the process conditions for which the fault count meets the counting criteria.

[0134] 3. The method according to Clause 2, wherein the counting criterion is an expected zero-fault count.

[0135] 4. The method according to any of the preceding clauses, wherein the contour data includes measured contour data from an exposed structure on a substrate across the plurality of layers.

[0136] 5. The method according to any of the preceding clauses, wherein the contour data comprises simulated contour data derived from computational simulations of exposures of a structure across the plurality of layers.

[0137] 6. The method according to any of the preceding clauses, wherein each of the process conditions is associated with a corresponding combination of the process parameters.

[0138] 7. The method according to any of the preceding clauses, wherein the plurality of process parameters includes two or more of the following: focusing, dose, overlay, MA, MSD, any projection aberration parameter, irradiation wavelength and / or bandwidth, any etching parameter, any patterning device optimization parameter.

[0139] 8. The method according to Clause 7, wherein the patterning device optimization parameters include one or more parameters related to optical proximity correction or source mask optimization.

[0140] 9. The method according to any of the preceding clauses further includes using the process window to identify one or more key features from a key region of the process window, the key region including or associated with a small process window volume or area.

[0141] 10. The method according to Clause 9, comprising: sorting the key features according to the volume or area of ​​the key region.

[0142] 11. The method according to Clause 9 or 10 further comprises: determining the overlapping process window for the process as a common area or volume defined by the critical region.

[0143] 12. The method according to Clause 11 further comprises: using the overlapping process window to determine one or more process parameters among the process parameters as the major contributors to limiting the process window.

[0144] 13. The method according to clause 11 or 12 further includes: selecting a control strategy for the manufacturing process as a control strategy that conforms to the overlapping process window.

[0145] 14. The method according to Clause 13 further includes determining an overlapping process window for each of a plurality of control strategies; evaluating each control strategy based on the overlapping process window; and making a control decision based on the evaluation.

[0146] 15. The method according to Clause 14 further comprises: sorting the control strategies according to the volume or area of ​​the overlapping process windows of the control strategies.

[0147] 16. The method according to any one of clauses 11 to 15, further comprising: determining an actuation constraint subspace of the overlapping process window based on actuation constraints applied by a plurality of actuators used in the manufacturing process; and determining a control strategy associated with process conditions that conform to the actuation constraint subspace of the overlapping process window.

[0148] 17. The method according to Clause 16, wherein determining the control strategy comprises: obtaining a configuration of the plurality of actuators defined by actuator setpoints described in the process space; and evaluating whether the configuration conforms to the actuation constraint subspace.

[0149] 18. The method according to clause 16 or 17 further includes configuring the plurality of actuators according to the determined control strategy.

[0150] 19. The method according to any one of Clauses 16 to 18, wherein determining the control strategy includes using an optimization model describing the limitations of the plurality of actuators.

[0151] 20. The method according to Clause 19, wherein the optimization model includes fingerprints relating to the exposure of each of the layers.

[0152] 21. The method according to Clause 19 or 20, wherein the optimization model optimizes the cost function per die.

[0153] 22. The method according to any one of Clauses 19 to 20, wherein the optimization model is operable to minimize the drift of the process combination corresponding to the selected control strategy from the center or initial state in the actuation constraint subspace.

[0154] 23. The method according to any one of clauses 19 to 22, wherein the optimization model is operable to adapt the actuation constraint subspace to conform to new or additional constraints.

[0155] 24. The method according to any one of Clauses 19 to 23, wherein the optimization model is operable to mitigate crosstalk with an external process when selecting a control strategy by one or more of the following methods: not using correctable parameters that affect the external process to compensate for drift of uncorrectable parameters; learning any new constraints imposed by the external process and modifying the actuation constraint subspace accordingly; and taking into account any state changes since the last exposure.

[0156] 25. The method according to any one of clauses 16 to 24 further comprises: updating the actuation constraint subspace with a physical actuator space defined by the latest available actuator range.

[0157] 26. The method according to any one of clauses 16 to 25 further comprises: compensating for the drift of uncorrectable process parameters with correctable process parameters based on an evaluation of the actuation constraint subspace.

[0158] 27. The method according to any one of clauses 16 to 26, wherein determining the actuation constraint subspace of the overlapping process window comprises: evaluating a list of key features for all actuable combinations of the control parameters; and defining the actuation constraint subspace as the actuation constraint subspace including all actuable combinations of the control parameters, wherein the key features are determined to be generated for all actuable combinations.

[0159] 28. The method according to any one of Clauses 16 to 27, wherein the determination of overlapping process windows is performed in advance for a plurality of different configurations to construct a library of overlapping process windows; and the determination of the actuation constraint subspace of the overlapping process windows comprises: determining the actuation constraint subspace for overlapping process windows corresponding to a specific configuration obtained from the library.

[0160] 29. The method according to Clause 28, wherein the configuration describes the configuration of both at least one lithography device parameter and at least one non-lithography parameter.

[0161] 30. The method according to Clause 29, wherein determining the actuation constraint subspace includes determining the actuation constraint subspace in response to a change in the at least one non-lithographic parameter.

[0162] 31. The method according to clause 29 or 30, wherein determining the actuation constraint subspace includes determining the actuation constraint subspace for a lithography apparatus capable of operating to pattern on an exposed substrate, and the determining step takes into account corrections performed outside the lithography apparatus.

[0163] 32. The method according to any one of clauses 29 to 31, wherein the at least one non-lithographic parameter includes at least one optical proximity correction parameter related to the optical proximity correction process, and the method includes balancing optical proximity correction workload and gain in performance metrics.

[0164] 33. The method according to Clause 32, wherein the optical proximity correction process includes performing optical proximity effect correction process optimization, the optical proximity effect correction process optimization being designed to ensure that the optimization metric is within specifications without having to further optimize the performance metric.

[0165] 34. A method for configuring a plurality of actuators for actuating a manufacturing process, comprising: obtaining a process window within a process space for the manufacturing process, the process space being defined by a plurality of process parameters, the process window being a subspace within the process space associated with expected compliance with processing requirements;

[0166] Based on the actuation constraints applied by the plurality of actuators, an actuation constraint subspace of the process window is determined; and a control strategy for the plurality of actuators that conforms to the actuation constraint subspace is determined.

[0167] 35. The method according to Clause 34, wherein determining the control strategy comprises: obtaining a configuration of the plurality of actuators defined by actuator setpoints described in the process space; and evaluating whether the configuration conforms to the actuation constraint subspace.

[0168] 36. The method according to clause 34 or 35 further includes configuring the plurality of actuators according to the determined control strategy.

[0169] 37. The method according to any one of clauses 34 to 36, wherein determining the control strategy includes using an optimization model describing the limitations of the plurality of actuators.

[0170] 38. The method according to Clause 37, wherein the optimization model includes fingerprints relating to the exposure of each layer of the layer.

[0171] 39. The method according to clause 37 or 38, wherein the optimization model optimizes the cost function per die.

[0172] 40. The method according to any one of clauses 37 to 39, wherein the optimization model is operable to minimize the drift of the process combination corresponding to the selected control strategy from the center or initial state in the actuation constraint subspace.

[0173] 41. The method according to any one of clauses 37 to 40, wherein the optimization model is operable to adapt the actuation constraint subspace to conform to new or additional constraints.

[0174] 42. The method according to any one of Clauses 37 to 41, wherein the optimization model is operable to mitigate crosstalk with an external process when selecting a control strategy by one or more of the following methods: not using correctable parameters that affect the external process to compensate for drift of uncorrectable parameters; learning any new constraints imposed by the external process and modifying the actuation constraint subspace accordingly; and taking into account any state changes since the last exposure.

[0175] 43. The method according to any one of clauses 34 to 42 further includes: updating the actuation constraint subspace with a physical actuator space defined by the latest available actuator range.

[0176] 44. The method according to any one of clauses 34 to 43 further comprises: compensating for the drift of uncorrectable process parameters with correctable process parameters based on an evaluation of the actuation constraint subspace.

[0177] 45. The method according to any one of clauses 34 to 44, wherein determining the actuation constraint subspace of the process window comprises: evaluating a list of key features of all actuable combinations of the control parameters; and defining the actuation constraint subspace as the actuation constraint subspace including all actuable combinations of the control parameters, wherein the key features are determined to be generated for all actuable combinations.

[0178] 46. ​​The method according to any one of clauses 34 to 45, wherein the plurality of process parameters includes both photolithography process parameters and non-photolithography process parameters.

[0179] 47. The method according to Clause 46, wherein the plurality of process parameters includes two or more of the following: focusing, dose, overlay, MA, MSD, any projection aberration parameter, irradiation wavelength and / or bandwidth, any etching parameter, any patterning device optimization parameter.

[0180] 48. The method according to Clause 47, wherein the patterning device optimization parameters include one or more parameters related to optical proximity correction or source mask optimization.

[0181] 49. The method according to any one of clauses 46 to 48, wherein the process windows are obtained from a process window library, and each process window corresponds to a different configuration of the plurality of process parameters.

[0182] 50. The method according to Clause 49, wherein determining the actuation constraint subspace includes determining the actuation constraint subspace in response to a change in the at least one non-lithographic parameter.

[0183] 51. The method according to any one of clauses 46 to 50, wherein determining the actuation constraint subspace comprises determining the actuation constraint subspace for a lithography apparatus capable of operating to expose patterns on a substrate, and the determining step takes into account corrections performed outside the lithography apparatus.

[0184] 52. The method according to any one of clauses 46 to 51, wherein the at least one non-lithographic parameter includes at least one optical proximity effect correction parameter related to the optical proximity correction process, and the method includes balancing the optical proximity effect correction workload and gain in performance metrics.

[0185] 53. The method according to Clause 52, wherein the optical proximity correction process includes performing optical proximity correction process optimization, the optical proximity correction process optimization being designed to ensure that the optimization metric is within specifications without having to further optimize the performance metric.

[0186] 54. The method according to clause 52 or 53, wherein the optical proximity correction process includes performing optical proximity correction process optimization, the optical proximity correction process optimization being designed to ensure that the actuation constraint subspace is maximized without having to further optimize the performance metric.

[0187] 55. A computer program comprising program instructions that, when run on a suitable device, are operable to perform the method described in any one of clauses 1 to 54.

[0188] 56. A non-transitory computer program carrier comprising the computer program described in Clause 55.

[0189] 57. A processing system comprising: a non-transitory computer program carrier as described in clause 56; and a processor operable to execute the program instructions.

[0190] 58. A lithography apparatus configured to provide a product structure to a substrate in a lithography process, the lithography apparatus comprising the processing system described in clause 57.

[0191] 59. The lithography apparatus according to Clause 58 further includes: a substrate stage for holding the substrate; a mask stage for holding the patterning apparatus; and a projection system operable to project a radiation beam patterned by the patterning apparatus onto the substrate.

[0192] In all the above embodiments, data science methods can be used to appropriately describe / train OPW and / or DAAS. Such data science methods can include neural networks, and more specifically can include, for example, deep learning neural networks, transfer learning networks (which can, for example, transfer (similar) learning and knowledge between different processes or layers), or residual neural networks.

[0193] Within this disclosure, any reference to permitted process space or process window may include overlapping process windows and / or N-dimensional process windows as described (e.g., axes may include one or more of focus, dosage, overlap, contrast, etc.). In one embodiment, process window tracking may be employed. This includes locally restricting one (or more) process window axes to offset the setpoint of another axis or axes. Process window tracking is described in WO 2016202559, which is incorporated herein by reference. In all cases, process window information may be determined based on product information or mask design information (related to the structure being exposed) and / or simulated design information.

[0194] The terms “radiation” and “beam” used in relation to lithography equipment cover all types of electromagnetic radiation, including ultraviolet (UV) radiation (e.g., with wavelengths around 365 nm, 355 nm, 248 nm, 193 nm, 157 nm, or 126 nm) and extreme ultraviolet (EUV) radiation (e.g., with wavelengths in the range of 5 nm to 20 nm), as well as particle beams (such as ion beams or electron beams).

[0195] Where the context permits, the term “lens” can refer to any one or a combination of various types of optical components, including refractive, reflective, magnetic, electromagnetic, and electrostatic optical components.

[0196] The above description of specific embodiments will fully reveal the general nature of the invention. Various applications of these specific embodiments can be easily modified and / or adapted without departing from the general concept of the invention, using knowledge in the art, without excessive experimentation. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology in this specification is for the purpose of description by way of example and not for limitation, and that the terminology or terminology in this specification should be interpreted by those skilled in the art based on the teachings and guidance.

[0197] The breadth and scope of this invention should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for determining a process window within a process space for a substrate manufacturing process, the process space being defined by a plurality of process parameters, the process window being a subspace within the process space associated with expected compliance with processing requirements; the method comprising: For each of a plurality of process conditions associated with providing features across a plurality of layers of the substrate, contour data relating to the features provided across the plurality of layers of the substrate to the substrate is obtained, wherein the contour data is extracted from an image of the substrate; Obtain edge placement error (EPE) failure mode data, which describes the constraints on the contour data across the plurality of layers of the substrate; The EPE failure mode data is applied to the profile data to determine the EPE failure count for each process condition. as well as The process window is determined by associating each process condition with its corresponding EPE failure count.

2. The method according to claim 1, wherein the process window is determined to include the process conditions in which the EPE fault count meets the counting criteria for the process conditions.

3. The method of claim 2, wherein the counting criterion is an expected zero EPE fault count.

4. The method of claim 1, wherein the contour data comprises measured contour data of an exposed structure on the substrate across the plurality of layers.

5. The method of claim 1, wherein the contour data comprises simulated contour data derived from computational simulations of exposure of structures on the substrate across the plurality of layers.

6. The method of claim 1, wherein the plurality of process parameters includes two or more of the following: focusing, dose, overlay, MA, MSD, any projection aberration parameter, irradiation wavelength and / or bandwidth, any etching parameter, and any patterning device optimization parameter.

7. The method according to claim 6, wherein the optimized parameters of the patterning device include: One or more of the parameters related to optical proximity correction or source mask optimization.

8. The method of claim 1, further comprising using the process window to identify one or more key features from a key region of the process window, the key region comprising or associated with a small process window volume or area.

9. The method according to claim 8, further comprising: The key features are sorted according to the volume or area of ​​the key region.

10. The method of claim 8, further comprising: The overlapping process window used for the process is defined as a common area or volume defined by the critical region.

11. The method of claim 10, further comprising: The control strategy for the manufacturing process used for the substrate is selected as the control strategy that conforms to the overlapping process window.

12. The method of claim 10, further comprising: The actuation constraint subspace of the overlapping process window is determined based on the actuation constraints applied by the plurality of actuators used in the manufacturing process of the substrate. And determine a control strategy associated with process conditions that conform to the actuation constraint subspace of the overlapping process window.

13. The method of claim 12, wherein determining the control strategy comprises: Obtaining a configuration of the plurality of actuators defined by actuator setpoints described in the process space, and further including evaluating whether the configuration conforms to the actuation constraint subspace.

14. A computer program comprising program instructions that, when run on a suitable device, are operable to perform the method according to any one of claims 1 to 13.

15. A non-transitory computer program carrier, comprising the computer program according to claim 14.

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