Transition time processing apparatus and method for static timing analysis

Abstract

The application discloses a conversion time processing device and method for static timing analysis, relates to the technical field of timing analysis, and mainly aims to reduce the calculation power consumption of static timing analysis and improve the accuracy of the static timing analysis result. The conversion time processing device for static timing analysis comprises a selection module, a first processing module and a second processing module. The selection module is used for selecting a target circuit unit and a non-target circuit unit from a circuit to be subjected to timing analysis. The first processing module is used for performing combined processing on the conversion times of all output signals of the target circuit unit, and replacing the conversion times of all the output signals with the conversion time obtained through the combined processing. The second processing module is used for maintaining the conversion times of all output signals of the non-target circuit unit unchanged.

Description

Technical Field

[0001] This application relates to the field of time series analysis technology, and in particular to a conversion time processing device and method for static time series analysis. Background Technology

[0002] In the design process of integrated circuits, timing analysis is required to identify any timing errors. Currently, static timing analysis is widely used in integrated circuit design because it can perform comprehensive timing and functional testing of integrated circuits.

[0003] Static timing analysis primarily calculates the overall delay of an integrated circuit by measuring the transition times of the output signals from its individual circuit units. Therefore, the processing of the transition times of each circuit unit's output signals directly impacts the computational cost of static timing analysis and the accuracy of the results. Summary of the Invention

[0004] In view of this, this application proposes a conversion time processing device and method for static time series analysis, aiming to improve the accuracy of static time series analysis results while reducing the computational power consumption of static time series analysis.

[0005] To achieve the above objectives, this application mainly provides the following technical solutions:

[0006] In a first aspect, this application provides a transition time processing apparatus for static timing analysis, the transition time processing apparatus for static timing analysis comprising:

[0007] The selection module is used to select target circuit units and non-target circuit units from the circuit to be analyzed in timing analysis.

[0008] The first processing module is used to merge the conversion times of all output signals of the target circuit unit and replace the conversion times of all output signals with the merged conversion times.

[0009] The second processing module is used to keep the conversion time of all output signals of the non-target circuit unit unchanged.

[0010] In some embodiments, the selection module includes: a first selection submodule, configured to select a first circuit unit from the circuit once every first number of logic levels; and to determine all selected first circuit units as target circuit units; wherein the first number is a positive integer not less than 2.

[0011] In some embodiments, the selection module includes: a second selection submodule, configured to select a second circuit unit from the circuit; and to determine all selected second circuit units as target circuit units if the total number of second circuit units does not reach a first threshold; wherein the total number of output signals of the second circuit units reaches a second threshold, and the second threshold is a positive integer not less than 2.

[0012] In some embodiments, the selection module includes: a third selection submodule, configured to select a second circuit unit from the circuit; and, if the total number of the second circuit units reaches a first threshold, to determine a portion of the second circuit units as target circuit units; wherein the total number of output signals of the second circuit units reaches a second threshold, and the second threshold is a positive integer not less than 2.

[0013] In some embodiments, the target circuit units determined by the third selection submodule have the following characteristics: at least a second number of logic levels are spaced between any two target circuit units, wherein the second number is a positive integer not less than 2.

[0014] In some embodiments, the selection module includes a fourth selection submodule, used to select all circuit units in the circuit that were not selected as target circuit units as non-target circuit units.

[0015] In some embodiments, the first processing module includes: a first processing submodule, configured to, when the number of output signals of the target circuit unit is not less than two, determine one of the conversion times of the output signals that meets the timing analysis requirements as the conversion time obtained by merging processing.

[0016] In some embodiments, the first processing module includes: a second processing submodule, configured to, when the number of output signals of the target circuit unit is not less than two, assign a corresponding weight to the conversion time of each output signal of the target circuit unit; determine a weighted sum of conversion times based on the assigned weights; and determine the resulting weighted sum as the conversion time obtained by merging processing.

[0017] In a second aspect, this application provides a static timing analysis apparatus, which includes: an analysis device and a transition time processing device for static timing analysis according to the first aspect;

[0018] The analysis device is used to perform static timing analysis on the circuit based on the transition time determined by the transition time processing device for each circuit unit in the circuit to be analyzed.

[0019] Thirdly, this application provides a transition time processing method for static timing analysis, which includes:

[0020] Select target circuit units and non-target circuit units from the circuit to be analyzed in timing sequence;

[0021] For the target circuit unit, the conversion times of all output signals of the target circuit unit are merged, and the conversion times of all output signals are replaced with the conversion times obtained by merging.

[0022] For the non-target circuit unit, the conversion time for all output signals of the non-target circuit unit remains unchanged.

[0023] Fourthly, this application provides a computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device where the storage medium is located to perform the conversion time processing method for static timing analysis as described in the third aspect.

[0024] The conversion time processing apparatus and method for static timing analysis provided in this application first selects target circuit units and non-target circuit units from the circuit to be analyzed during conversion time processing. Then, for the target circuit unit, the conversion times of all output signals of the target circuit unit are merged, and the conversion times of all output signals are replaced with the merged conversion times. For non-target circuit units, the conversion times of all output signals of the non-target circuit units remain unchanged. The scheme provided in this application divides the circuit units in the circuit to be analyzed into two parts. The conversion times of the output signals of one part of the circuit units need to be merged, while the conversion times of the output signals of the other part of the circuit units remain unchanged. This reduces the number of conversion times used in static timing analysis, and because some conversion times are not merged and remain unchanged, it improves the accuracy of the static timing analysis results. Therefore, the scheme provided in this application can improve the accuracy of static timing analysis results while reducing the computational power consumption of static timing analysis.

[0025] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of the structure of a conversion time processing device for static timing analysis provided in one embodiment of this application is shown;

[0028] Figure 2 This illustration shows a schematic diagram of a conversion time processing apparatus for static timing analysis according to another embodiment of this application;

[0029] Figure 3 This illustration shows a schematic diagram of a circuit provided in one embodiment of the present application;

[0030] Figure 4 A schematic diagram of a circuit provided in another embodiment of this application is shown;

[0031] Figure 5 This illustration shows a structural schematic diagram of a static timing analysis device according to an embodiment of this application;

[0032] Figure 6 A flowchart of a conversion time processing method for static timing analysis provided in one embodiment of this application is shown. Detailed Implementation

[0033] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0034] Currently, static timing analysis is widely used in integrated circuit design to identify timing errors. Static timing analysis primarily calculates the overall delay of the integrated circuit by analyzing the transition times of the output signals from its circuit units. Therefore, the processing of the transition times of each circuit unit's output signals directly affects the computational cost and accuracy of the static timing analysis results.

[0035] The inventors considered the following two points: First, if for each circuit unit in an integrated circuit, the most pessimistic transition time is selected from the transition times of all output signals of that circuit unit, then during static timing analysis, each circuit unit has only one transition time involved in calculating the delay of the entire integrated circuit. Although this reduces the computational power consumption of static timing analysis, the selection of the most pessimistic transition time leads to a pessimistic static timing analysis result, making the analysis relatively inaccurate. Second, if the transition times of all output signals of each circuit unit are reserved, then during static timing analysis, the number of transition times involved corresponds to the number of output signals in the circuit unit for delay calculation. While this ensures more accurate static timing analysis results, the large number of transition times involved in the calculation severely consumes the memory of the analysis equipment, resulting in high computational power consumption and slow analysis speed. Therefore, considering the above two points, the inventor discovered through research that, in order to reduce the computational power consumption of static timing analysis while improving the accuracy of static timing analysis results, the circuit units in the circuit to be analyzed can be divided into two parts. The conversion time of the output signal of one part of the circuit units needs to be merged, while the conversion time of the output signal of the other part of the circuit units can remain unchanged.

[0036] Based on the above considerations, embodiments of this application provide a conversion time processing apparatus and method for static timing analysis. Specifically, the conversion time processing apparatus and method for static timing analysis provided in this application divides the circuit units in the circuit to be analyzed into two parts. The conversion times of the output signals of one part of the circuit units need to be merged, while the conversion times of the output signals of the other part of the circuit units remain unchanged. This reduces the amount of conversion time used in static timing analysis, and since some conversion times are not merged and remain unchanged, this conversion time processing technique can reduce the computational power consumption of static timing analysis while improving the accuracy of the static timing analysis results.

[0037] The following is a detailed description of the conversion time processing apparatus and apparatus for static timing analysis provided in the embodiments of this application.

[0038] like Figure 1 As shown in the figure, this application provides a conversion time processing device for static timing analysis. The conversion time processing device for static timing analysis mainly includes a selection module 11, a first processing module 12, and a second processing module 13.

[0039] The selection module 11 is used to select target circuit units and non-target circuit units from the circuit to be analyzed in timing analysis.

[0040] The first processing module 12 is used to merge the conversion times of all output signals of the target circuit unit and replace the conversion times of all output signals with the conversion times obtained by merging the conversion times.

[0041] The second processing module 13 is used to keep the conversion time of all output signals of non-target circuit units constant for non-target circuit units.

[0042] The following describes the specific structure and interaction relationships of the components involved in the conversion time processing device used for static timing analysis:

[0043] Select module 11:

[0044] The selection module 11 is mainly used to select target circuit units and non-target circuit units from the circuit to be analyzed for timing. Target circuit units are those whose output signal transition times need to be combined. Non-target circuit units are those whose output signal transition times do not need to be combined and whose output signal transition times remain unchanged. In practical applications, any integrated circuit with timing analysis requirements can be used as the circuit to be analyzed for timing.

[0045] The technical solutions for selecting target circuit units from the circuit to be time-series analyzed by module 11 include the following three:

[0046] The first type, such as Figure 2 As shown, the selection module 11 includes: a first selection submodule 111, used to select a first circuit unit from the circuit once every first number of logic levels; and to determine all selected first circuit units as target circuit units; wherein the first number is a positive integer not less than 2.

[0047] The circuit to be analyzed in timing analysis typically consists of multiple circuit units. The connections between these units create multiple logic levels, with each circuit unit occupying its own logic level. For example, such as... Figure 3 As shown, Figure 3 This is a schematic diagram of a circuit. Figure 3 It can be seen that the circuit consists of circuit units U1-U4. Based on the connection relationship between the circuit units, the circuit has four logic levels. Specifically, circuit unit U1 is located at the first logic level, circuit unit U3 at the second logic level, circuit unit U2 at the third logic level, and circuit unit U4 at the fourth logic level.

[0048] The first selection submodule 111 mainly uses the logic hierarchy involved in the circuit to select the target circuit unit. Since the selection of the target circuit unit does not need to consider other factors, it only needs to select the target single-path unit from the circuit at the set hierarchical interval, thus simplifying the selection process of the target circuit unit.

[0049] The hierarchical interval used by the first selection submodule 111 is determined based on a first quantity. That is, every first quantity of logic levels, a first circuit unit is selected from the circuit once, and all selected first circuit units are determined as target circuit units. There are two cases for selecting a first circuit unit: First, if the logic level contains only one circuit unit, then this circuit unit is directly selected as the first circuit unit. Second, if the logic level contains two or more circuit units, then according to the preset selection rules, a number of first circuit units that meet the selection rules can be selected from these circuit units.

[0050] The first quantity is a key data point for determining the hierarchical interval, used to limit the logical hierarchy interval. The first quantity can be set based on the following two principles: First, the first quantity should ensure that the ratio of selected target circuit units to non-target circuit units is within a certain range. This not only combines the transition times of the target circuit unit's output signal into a single transition time, reducing the number of transition times used in static timing analysis, but also maintains the original state of the transition times of non-target circuits, thus improving the accuracy of the static timing analysis results. Second, the number of hierarchical intervals between circuit units that output at least two output signals is counted, and the number of hierarchical intervals that appears most frequently in the count is set as the first quantity. This ensures that most of the selected target circuit units are those that output at least two output signals. Since circuit units that output at least two signals each have their own corresponding transition time, the transition times are numerous. This numerous transition times increase the computational cost of subsequent static timing analysis. Therefore, selecting most circuit units with at least two output signals as target circuit units allows for the merging of the transition times of all output signals from these units. The transition times of all output signals are then replaced with the merged transition times, ensuring that all output signals of the target circuit unit have the same transition time. In this way, only one transition time of the target circuit unit is involved in the delay calculation during subsequent static timing analysis, thus reducing the number of transition times required to calculate the delay of the entire integrated circuit and consequently reducing the computational cost of static timing analysis.

[0051] For example, such as Figure 3 As shown, from Figure 3As can be seen, circuit unit U1 has two pins, A1 and A2. Circuit unit U1 receives two input signals through these two pins and processes them accordingly.

[0052] The two input signals are processed to form two output signals. Circuit unit U1 outputs these two output signals through pin Z1, and these two output signals are then transmitted as input signals to circuit unit U3. Circuit unit U3 receives the two input signals transmitted by circuit unit U1 through pin B1, processes them respectively, and forms two output signals. Circuit unit U3 outputs these two output signals through pin Z3, and these two output signals are then transmitted as input signals to circuit unit U2. Circuit unit U2 receives the two input signals transmitted by circuit unit U3 through pin C1, and simultaneously receives another input signal through pin C2. Circuit unit U2 processes these three output signals respectively, forming three output signals. Circuit unit U2 outputs these three output signals through pin Z2, and these three output signals are then transmitted as input signals to circuit unit U4. Circuit unit U4 receives these three output signals transmitted by circuit unit U2 through pin D1, processes them respectively, forms three output signals, and finally outputs the three formed output signals through pin Z4. Therefore, Figure 3 In the circuit shown, each circuit unit outputs at least two signals. Considering the need to reduce the computational cost of static timing analysis while improving the accuracy of the results, the first quantity can be set to 2, meaning one circuit unit is selected as the target circuit unit every two logic levels. After selection, circuit units U3 and U4 are chosen as the target circuit units.

[0053] The first selection submodule 111 selects a first circuit unit from the circuit every first number of logic levels, and determines each selected first circuit unit as a target circuit unit. Thus, each target circuit unit has a gap between itself and its adjacent previous target circuit unit, and also a gap between itself and its adjacent next target circuit unit. This achieves the following effects: First, the target circuit units are selected from the circuit at certain level intervals, and the transition times of all output signals of any target circuit unit are unified into a single transition time. Therefore, for static timing analysis performed according to the logic level order of the circuit units, the existence of target circuit units can avoid continuous delay calculations for circuit units with two or more transition times during static timing analysis, thus alleviating computational burden to some extent. Second, the unified transition times of all output signals of the target circuit unit reduce the number of transition times used in static timing analysis. Simultaneously, since the transition times of some circuit units' output signals are not merged and remain unchanged, these circuit units can reflect the true state.

[0054] The second type, such as Figure 2 As shown, the selection module 11 includes: a second selection submodule 112, used to select a second circuit unit from the circuit; when the total number of the second circuit units is determined not to reach a first threshold, all the selected second circuit units are determined as target circuit units; wherein, the total number of output signals of the second circuit units reaches the second threshold, and the second threshold is a positive integer not less than 2.

[0055] Since each output signal of a circuit unit has its own corresponding conversion time, the conversion time is relatively long. This long conversion time will increase the computational power consumption of subsequent static timing analysis. Therefore, the circuit unit that outputs at least two output signals is selected as the second circuit unit so that the target circuit unit can be selected in a targeted manner within the second circuit unit.

[0056] After the second circuit unit is selected, its total number needs to be compared with a first threshold to select a target circuit unit from the second circuit unit based on the comparison result. This first threshold is set based on the total number of circuit units in the circuit; that is, the first threshold is used to ensure that the proportion of the selected target circuit unit in all circuit units does not exceed a proportion threshold.

[0057] When the second selection submodule 112 determines that the total number of second circuit units has not reached the first threshold, it indicates that the proportion of second circuit units in all circuit units meets the requirements. Therefore, all second circuit units are selected as target circuit units. In this way, the conversion time of the output signal of the target circuit unit is combined into a single conversion time. This not only reduces the number of conversion times used in static timing analysis, but also improves the accuracy of static timing analysis results because the conversion times of non-target circuits remain unchanged.

[0058] The third type, such as Figure 2 As shown, the selection module 11 includes: a third selection submodule 113, used to select a second circuit unit from the circuit; when the total number of the second circuit units reaches a first threshold, a portion of the second circuit units are determined as target circuit units; wherein, the total number of output signals of the second circuit units reaches a second threshold, and the second threshold is a positive integer not less than 2.

[0059] As can be seen from the second technical solution above, the first threshold is used to ensure that the proportion of the selected target circuit unit in all circuit units does not exceed the proportion threshold. When the third selection submodule 113 determines that the total number of second circuit units reaches the first threshold, it indicates that if all second circuit units are selected as target circuit units, it will lead to too much conversion time of the output signals of the circuit units and merged processing, which will affect the accuracy of the static timing analysis results. Therefore, it is sufficient to determine only a portion of the second circuit units as target circuit units.

[0060] The target circuit units determined by the third selection submodule 113 have the following characteristics: any two target circuit units are separated by at least a second number of logic levels, where the second number is a positive integer not less than 2. The purpose of having a logic level interval between target circuit units is that the target circuit units are selected from the circuit at a certain level interval, and the conversion time of all output signals of any target circuit unit is unified to a single conversion time. Therefore, for static timing analysis performed according to the logic level order of circuit units in the circuit, the existence of target circuit units can avoid continuous delay calculations for circuit units with two or more conversion times during static timing analysis. Thus, the existence of target circuit units can alleviate computational burden to a certain extent.

[0061] The technical solution for selecting non-target circuit units from the circuit to be time-series analyzed by module 11 is as follows: Figure 2 As shown, the selection module 11 includes a fourth selection submodule 114, which is used to select all circuit units in the circuit that have not been selected as target circuit units as non-target circuit units.

[0062] Non-target circuit units are those whose output signal transition times do not require merging and whose transition times remain unchanged. To ensure the completeness of static timing analysis, all circuit units not selected as target circuit units must be identified as non-target circuit units.

[0063] First processing module 12:

[0064] The first processing module 12 is mainly used to merge the conversion times of all output signals of the target circuit unit and replace the conversion times of all output signals of the target circuit unit with the merged conversion times. In this way, the conversion times of all output signals of the target circuit unit are unified into the same conversion time. When performing static timing analysis, the number of conversion times involved in static timing analysis can be reduced, thereby reducing the computational power consumption of static timing analysis.

[0065] The technical solutions for the first processing module 12 to merge the conversion times of all output signals of the target circuit unit include the following two:

[0066] One is, such as Figure 2 As shown, the first processing module 12 includes: a first processing submodule 121, which is used to determine one of the conversion times of the output signals that meets the timing analysis requirements as the conversion time obtained by merging processing when the number of output signals of the target circuit unit is not less than two.

[0067] When processing the conversion times of all output signals of the target circuit unit, the first processing submodule 121 needs to consider timing analysis requirements. Therefore, the first processing submodule 121 uses two methods to merge the conversion times of all output signals of the target circuit unit: First, if the timing analysis requirement is the slowest path, the first processing submodule 121 determines the maximum conversion time among all output signals of the target circuit unit as the merged conversion time and replaces all other conversion times of the target circuit unit with this maximum conversion time. Second, if the timing analysis requirement is the fastest path, the first processing submodule 121 determines the minimum conversion time among all output signals of the target circuit unit as the merged conversion time and replaces all other conversion times of the target circuit unit with this minimum conversion time.

[0068] Another one is, such as Figure 2As shown, the first processing module 12 includes: a second processing submodule 122, which is used to assign a corresponding weight to the conversion time of each output signal of the target circuit unit when the number of output signals of the target circuit unit is not less than two; determine the weighted sum of the conversion times based on the assigned weights; and determine the resulting weighted sum as the conversion time obtained by merging processing.

[0069] To ensure that the conversion time obtained after merging processing can incorporate the conversion times of all output signals of the target processing unit, a corresponding weight is assigned to the conversion time of each output signal of the target circuit unit. This weight can be assigned based on the magnitude of the conversion time.

[0070] After assigning corresponding weights to the conversion times of all output signals of the target circuit unit, for each conversion time, the product of the conversion time and the weight is calculated. The sum of all the resulting products is determined as the weighted sum, and this weighted sum is used as the conversion time obtained through merging. The conversion times of all output signals of the target circuit unit are then replaced with the conversion times obtained through merging.

[0071] Second processing module 13:

[0072] The first processing module 13 primarily maintains the transition times of all output signals from non-target circuit units unchanged; that is, it does not process the transition times of the output signals from non-target circuit units, simply keeping the transition times constant. The purpose of this is that, during static timing analysis, the transition times of all output signals from non-target circuit units can be included in the delay calculation, thus improving the accuracy of the static timing analysis results to a certain extent.

[0073] The conversion time processing apparatus for static timing analysis provided in this application first selects target circuit units and non-target circuit units from the circuit to be analyzed during conversion time processing. Then, for the target circuit unit, the conversion times of all output signals of the target circuit unit are merged, and the conversion times of all output signals are replaced with the merged conversion times. For non-target circuit units, the conversion times of all output signals of the non-target circuit units remain unchanged. In the scheme provided in this application, the circuit units in the circuit to be analyzed are divided into two parts. The conversion times of the output signals of one part of the circuit units need to be merged, while the conversion times of the output signals of the other part of the circuit units remain unchanged. This reduces the amount of conversion time used in static timing analysis, and because some conversion times are not merged and remain unchanged, the accuracy of the static timing analysis results can be improved. Therefore, the scheme provided in this application can improve the accuracy of static timing analysis results while reducing the computational power consumption of static timing analysis.

[0074] Furthermore, the following are examples: Figure 4 The circuit diagram shown is used as an example to illustrate the specific application of the conversion time processing device for static timing analysis provided in the embodiments of this application. Figure 4 The circuit consists of circuit units U1 to U4. The transition time processing device selects one circuit unit as the target circuit unit every two logic levels. After selection, circuit units U3 and U4 are selected as target circuit units. Circuit units U1 and U2 are selected as non-target circuit units.

[0075] For circuit unit U1: Input signal Ei1 is received through pin A1, with a transition time of T1. Input signal Ei2 is received through pin A2, with a transition time of T2. Circuit unit U1 processes input signal Ei1 to obtain output signal Eo1. The transition time of output signal Eo1 is T3, which is obtained by processing the transition time T1 of input signal Ei1. Circuit unit U1 processes input signal Ei2 to obtain output signal Eo2. The transition time of output signal Eo2 is T4, which is obtained by processing the transition time T1 of input signal Ei2. Since circuit unit U1 is a non-target circuit unit, the transition times T3 and T4 of output signal Eo1 remain unchanged. Therefore, the transition times T3 and T4 are marked at the output pin Z1 of circuit unit U1, respectively.

[0076] For circuit unit U3: The output signals Eo1 and Eo2 of circuit unit U1 are used as input signals and input to pin B1 of circuit unit U3. Circuit unit U3 processes the input signal Eo1 to obtain the output signal Eo3. The conversion time of the output signal Eo3 is T5, which is obtained by processing the conversion time T3 of the input signal Eo1. Circuit unit U3 processes the input signal Eo2 to obtain the output signal Eo4. The conversion time of the output signal Eo4 is T6, which is obtained by processing the conversion time T4 of the input signal Eo2. Since circuit unit U3 is the target circuit unit, the conversion times T5 of the output signal Eo3 and T6 of the output signal Eo4 need to be combined. During the merging process, the conversion time T5 is relatively large, so the conversion time T5 is determined as the conversion time obtained after the merging process. Therefore, the conversion times of the output signals Eo3 and Eo4 are both replaced with T5. Therefore, only the switching time T5 is marked at the output pin Z3 of circuit unit U3.

[0077] For circuit unit U2: The output signals Eo3 and Eo4 of circuit unit U3 are used as input signals and input to pin C1 of circuit unit U2. Circuit unit U3 processes the input signals Eo3 and Eo4 respectively to obtain the corresponding output signals Eo5 and Eo6. It should be noted that since the transition time of input signals Eo3 and Eo4 is T5, the output signals Eo5 and Eo6 obtained by circuit unit U2 after processing input signals Eo3 and Eo4 have the same transition time T7. Input signal Ei3 is received through pin C2, and the transition time of input signal Ei3 is T10. Circuit unit U2 processes input signal Ei3 to obtain output signal Eo7. The transition time of output signal Eo7 is T8, which is obtained by circuit unit U2 processing the input signal Ei3 at the transition time T10. Since circuit unit U2 is a non-target circuit unit, the transition times T7 of output signals Eo5 and Eo6 and the transition time T8 of output signal Eo7 remain unchanged. Therefore, the switching time T7 and switching time T8 are marked at the output pin Z2 of circuit unit U2.

[0078] For circuit unit U4: The output signals Eo5, Eo6, and Eo7 of circuit unit U2 are used as input signals and input to pin D1 of circuit unit U4. Circuit unit U4 processes the input signals Eo5 and Eo6 respectively to obtain the corresponding output signals Eo8 and Eo9. It should be noted that since the transition time of input signals Eo5 and Eo6 is T7, the output signals Eo8 and Eo9 obtained by circuit unit U4 after processing input signals Eo5 and Eo6 have the same transition time T9. Circuit unit U4 processes the input signal Eo7 to obtain the output signal Eo10. The transition time of output signal Eo10 is T11, which is obtained by circuit unit U4 processing the transition time T8 of input signal Eo7. Since circuit unit U4 is the target circuit unit, the transition time T9 of output signals Eo8 and Eo9 and the transition time T11 of output signal Eo10 need to be combined. During the merging process, the conversion time T9 is relatively large; therefore, T9 is determined as the conversion time obtained after the merging process. Thus, the conversion times of output signals Eo8, Eo9, and Eo10 are all replaced with T9. Therefore, the conversion time T9 is marked at the output pin Z4 of circuit unit U4.

[0079] In the Figure 4When performing static timing analysis on the circuit shown, the delay can be calculated using the transition times of the output signals indicated in the figure. Since the circuit units are divided into target and non-target circuit units, the transition times of the output signals of one part need to be combined, while the transition times of the output signals of the other part remain unchanged. This reduces the number of transition times used in static timing analysis, and because some transition times remain unchanged, the accuracy of the static timing analysis results is improved. Therefore, the solution provided in this application can improve the accuracy of static timing analysis results while reducing the computational cost.

[0080] Furthermore, one embodiment of this application also provides a device for static timing analysis, such as... Figure 5 As shown, the device for static time series analysis includes: analysis device 21 and the aforementioned conversion time processing device 22 for static time series analysis.

[0081] Analysis device 21 is used to perform static timing analysis on the circuit based on the switching time determined by switching time processing device 22 for each circuit unit in the circuit to be analyzed.

[0082] The static timing analysis apparatus provided in this application can divide the circuit units in the circuit to be analyzed into two parts. The transition times of the output signals of one part of the circuit units need to be merged, while the transition times of the output signals of the other part of the circuit units remain unchanged. This reduces the amount of transition time used in static timing analysis, and since some transition times are not merged and remain unchanged, the accuracy of the static timing analysis results can be improved. In addition, reducing the amount of transition time used in static timing analysis saves more timing resources during timing analysis, facilitating timing convergence in integrated circuit design.

[0083] Furthermore, one embodiment of this application also provides a transition time processing method for static timing analysis, such as... Figure 6 As shown, the transformation time processing method for static time series analysis includes the following steps:

[0084] 301. Select target circuit units and non-target circuit units from the circuit to be analyzed in timing sequence.

[0085] 302. For the target circuit unit, the conversion times of all output signals of the target circuit unit are merged, and the conversion times of all output signals are replaced with the conversion times obtained by merging.

[0086] 303. For the non-target circuit unit, the conversion time of all output signals of the non-target circuit unit remains unchanged.

[0087] The conversion time processing method for static timing analysis provided in this application first selects target circuit units and non-target circuit units from the circuit to be analyzed. Then, for the target circuit unit, the conversion times of all output signals of the target circuit unit are merged, and the conversion times of all output signals are replaced with the merged conversion times. For non-target circuit units, the conversion times of all output signals of the non-target circuit units remain unchanged. The solution provided in this application divides the circuit units in the circuit to be analyzed into two parts. The conversion times of the output signals of one part of the circuit units need to be merged, while the conversion times of the output signals of the other part of the circuit units remain unchanged. This reduces the number of conversion times used in static timing analysis, and because some conversion times are not merged and remain unchanged, it improves the accuracy of the static timing analysis results. Therefore, the solution provided in this application can improve the accuracy of static timing analysis results while reducing the computational power consumption of static timing analysis.

[0088] In some embodiments, the specific process of selecting target circuit units from the circuit to be time-series analyzed in step 301 includes the following steps: selecting a first circuit unit from the circuit every first number of logic levels; determining all selected first circuit units as target circuit units; wherein, the first number is a positive integer not less than 2.

[0089] In some embodiments, the specific process of selecting target circuit units from the circuit to be time-series analyzed in step 301 includes the following steps: selecting a second circuit unit from the circuit; determining that the total number of the second circuit units does not reach a first threshold, and determining all selected second circuit units as target circuit units; wherein the total number of output signals of the second circuit units reaches a second threshold, and the second threshold is a positive integer not less than 2.

[0090] In some embodiments, the specific process of selecting target circuit units from the circuit to be time-series analyzed in step 301 includes the following steps: selecting a second circuit unit from the circuit; determining a portion of the second circuit units as target circuit units when the total number of the second circuit units reaches a first threshold; wherein the total number of output signals of the second circuit units reaches a second threshold, and the second threshold is a positive integer not less than 2.

[0091] In some embodiments, the determined target circuit units have the following characteristics: at least a second number of logic levels are spaced between any two target circuit units, wherein the second number is a positive integer not less than 2.

[0092] In some embodiments, the specific process of selecting non-target circuit units from the circuit to be time-series analyzed in step 301 includes the following steps: selecting all circuit units in the circuit that were not selected as target circuit units as non-target circuit units.

[0093] In some embodiments, the specific execution process of step 302 above, which merges the conversion times of all output signals of the target circuit unit and replaces the conversion times of all output signals with the conversion times obtained by merging the conversion times, includes: when the number of output signals of the target circuit unit is not less than two, determining one of the conversion times of the output signals that meets the timing analysis requirements as the conversion time obtained by merging the conversion times.

[0094] In some embodiments, the specific execution process of step 302 above, which merges the conversion times of all output signals of the target circuit unit and replaces the conversion times of all output signals with the conversion times obtained by merging the conversion times, includes: when the number of output signals of the target circuit unit is not less than two, assigning a corresponding weight to the conversion time of each output signal of the target circuit unit; determining a weighted sum of conversion times based on the assigned weights, and determining the obtained weighted sum as the conversion time obtained by merging the conversion times.

[0095] For detailed explanations of each step in the conversion time processing method for static timing analysis provided in this application embodiment, please refer to the corresponding detailed explanations of the above-described conversion time processing device embodiment for static timing analysis, which will not be repeated here.

[0096] Furthermore, based on the above embodiments, another embodiment of this application provides a computer-readable storage medium, the storage medium including a stored program, wherein, when the program is executed, it controls the device where the storage medium is located to perform the above-described conversion time processing method for static timing analysis.

[0097] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0098] It is understood that the relevant features in the above methods and apparatus can be referenced interchangeably. Furthermore, the terms "first," "second," etc., in the above embodiments are used to distinguish between embodiments and do not represent the superiority or inferiority of any particular embodiment.

[0099] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0100] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this application is not directed to any particular programming language. It should be understood that the content of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing preferred embodiments of this application.

[0101] In addition, the memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0102] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0103] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data cutover device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data cutover device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0104] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data cutover device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0105] These computer program instructions can also be loaded onto a computer or other programmable data cutover device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0106] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0107] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0108] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0109] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0110] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0111] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A conversion time processing device for static time series analysis, characterized in that, The device includes: The selection module is used to select target circuit units and non-target circuit units from the circuit to be analyzed in timing analysis. The first processing module is used to merge the conversion times of all output signals of the target circuit unit and replace the conversion times of all output signals with the merged conversion times. The second processing module is used to keep the conversion time of all output signals of the non-target circuit unit unchanged for the non-target circuit unit. The selection module includes: a second selection submodule, used to select a second circuit unit from the circuit; if the total number of the second circuit units does not reach a first threshold, all selected second circuit units are determined as target circuit units; wherein, the total number of output signals of the second circuit units reaches a second threshold, the second threshold being a positive integer not less than 2; the second circuit unit is a circuit unit that outputs at least two output signals.

2. The apparatus according to claim 1, characterized in that, The selection module includes: The first selection submodule is used to select a first circuit unit from the circuit once every first number of logic levels; and to determine all selected first circuit units as target circuit units; wherein the first number is a positive integer not less than 2.

3. The apparatus according to claim 1, characterized in that, The selection module includes: The third selection submodule is used to select a second circuit unit from the circuit; when the total number of the second circuit units reaches a first threshold, a portion of the second circuit units are determined as target circuit units; wherein, the total number of output signals of the second circuit units reaches a second threshold, and the second threshold is a positive integer not less than 2.

4. The apparatus according to claim 3, characterized in that, The target circuit units determined by the third selection submodule have the following characteristics: there is at least a second number of logic levels between any two target circuit units, wherein the second number is a positive integer not less than 2.

5. The apparatus according to any one of claims 1-2 and 4, characterized in that, The selection module includes: The fourth selection submodule is used to select all circuit units in the circuit that were not selected as target circuit units as non-target circuit units.

6. The apparatus according to any one of claims 1-2 and 4, characterized in that, The first processing module includes: a first processing submodule, used to determine, when the number of output signals of the target circuit unit is not less than two, one of the conversion times of the output signals that meets the timing analysis requirements as the conversion time obtained by merging processing; or, The first processing module includes: a second processing submodule, configured to assign a corresponding weight to the conversion time of each output signal of the target circuit unit when the number of output signals of the target circuit unit is not less than two; determine a weighted sum of conversion times based on the assigned weights; and determine the resulting weighted sum as the conversion time obtained by merging processing.

7. A device for static time series analysis, characterized in that, The device includes: an analysis device and a conversion time processing apparatus for static time series analysis as described in any one of claims 1-6; The analysis device is used to perform static timing analysis on the circuit based on the transition time determined by the transition time processing device for each circuit unit in the circuit to be analyzed.

8. A method for processing conversion time in static time series analysis, characterized in that, The method includes: Select target circuit units and non-target circuit units from the circuit to be analyzed in timing sequence; For the target circuit unit, the conversion times of all output signals of the target circuit unit are merged, and the conversion times of all output signals are replaced with the conversion times obtained by merging. For the non-target circuit unit, the conversion time for all output signals of the non-target circuit unit remains unchanged; Selecting target circuit units from the circuit to be time-series analyzed includes: selecting a second circuit unit from the circuit; if the total number of the second circuit units does not reach a first threshold, all selected second circuit units are determined as target circuit units; wherein the total number of output signals of the second circuit units reaches a second threshold, the second threshold being a positive integer not less than 2; and the second circuit unit is a circuit unit that outputs at least two output signals.

9. A computer-readable storage medium, characterized in that, The storage medium includes a stored program, wherein, when the program is executed, it controls the device where the storage medium is located to execute the conversion time processing method for static timing analysis as described in claim 8.

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