A method for processing time series data, a computer storage medium and a terminal

Abstract

The application discloses a method, a computer storage medium and a terminal for realizing timing data processing, and comprises the following steps: configuring a simulation environment according to test parameters of a test case; traversing all predetermined paths of the test case; extracting a netlist file for performing simulation processing from a hardware circuit of a field programmable gate array (FPGA) chip; performing simulation processing in the configured simulation environment after the predetermined paths are configured through the netlist file; and obtaining timing data from data obtained from the simulation processing. The simulation processing of the chip is performed through the hardware circuit, and the timing data in the real circuit is obtained, so that the quality of the timing data provided for the matched software tool is improved.

Description

Technical Field

[0001] This article relates to, but is not limited to, field-programmable gate array (FPGA) technology, and particularly to a method for implementing time-series data processing, computer storage media, and terminals. Background Technology

[0002] With the rapid development of semiconductor technology, the application fields of Field Programmable Gate Arrays (FPGAs) are becoming more and more extensive. At the same time, they integrate more configurable logic units and become faster and faster, making the extraction of timing data more important. Timing data can be used to help software perform timing optimization and plays an important role in the process of hardware upgrades.

[0003] Methods for extracting timing data in related technologies include: 1. Abstracting and establishing a software timing model based on the FPGA's hardware architecture, then performing timing simulation on this model and extracting the corresponding simulation parameters. This method does not require simulating the actual circuit and can obtain simulation parameters relatively quickly. However, the timing data obtained through the software timing model differs from the timing of the actual circuit and can only be used in situations where timing data requirements are not very strict, although it can shorten the time to some extent. 2. Simulating the hardware circuit sequentially according to different loads can obtain actual timing data. In situations where the number of loads is small, the actual simulation data of the circuit can be obtained relatively quickly. However, running a simulation for each load in the hardware circuit requires a lot of manpower and time.

[0004] In summary, how to improve the efficiency and quality of time series data extraction has become an issue that needs to be addressed. Summary of the Invention

[0005] The following is an overview of the topics described in detail in this article.

[0006] This invention provides a method, computer storage medium, and terminal for processing time-series data, which can improve the extraction efficiency and quality of time-series data.

[0007] This invention provides a method for implementing time-series data processing, comprising: Configure the simulation environment according to the test parameters of the test cases; Iterate through all the predefined paths of the test cases; Extract the netlist file used for performing simulation processing from the hardware circuitry of the Field Programmable Gate Array (FPGA) chip; After configuring the predetermined path through the netlist file, the simulation process is executed in the configured simulation environment; Time series data is obtained from the data obtained through simulation processing.

[0008] In one exemplary instance, traversing all predetermined paths of the test case includes: For each pre-selected input line in the test case, the input line, and all loads between the module containing the input line and other modules are added to a preset table to obtain the predetermined path.

[0009] In one exemplary instance, the step of configuring a predetermined path via a netlist file and then performing simulation processing in the configured simulation environment includes: After loading a predetermined path configured through a netlist file in the simulation environment, simulation processing is performed by loading a preset excitation signal onto the input line of the loaded predetermined path configured through the netlist file.

[0010] In one exemplary instance, the excitation signal includes: The predetermined reference voltage value is output sequentially according to a preset strategy, multiplying the reference voltage value by a preset percentage.

[0011] In one exemplary instance, the simulation processing by loading a preset excitation signal onto the input line configured with a predetermined path through a netlist file includes: For each input line, starting from zero load, the loads in the predetermined path are sequentially superimposed to obtain all load combinations; For all load combinations obtained through traversal, simulation processing is performed by loading the excitation signal onto the input lines.

[0012] In one exemplary instance, after obtaining time-series data from the data obtained from the simulation processing, the method further includes: The acquired timing data is added to a preset table for timing analysis of the FPGA chip.

[0013] In one exemplary instance, extracting the netlist file for performing simulation processing from the hardware circuitry of the FPGA chip includes: When it is determined that the number of modules contained in the predetermined path is greater than a preset value, the netlist of all modules contained in the FPGA chip is extracted, and the extracted netlist of the modules is used as the netlist file for performing simulation processing.

[0014] In one exemplary instance, extracting the netlist file for performing simulation processing from the hardware circuitry of the FPGA chip includes: When it is determined that the number of modules contained in the predetermined path is less than or equal to a preset value, the netlist of the modules contained in the predetermined path is extracted, and the extracted netlist of the modules contained in the predetermined path is used as the netlist file for performing simulation processing.

[0015] On the other hand, embodiments of the present invention also provide a computer storage medium storing a computer program, which, when executed by a processor, implements the above-described method for implementing timing data processing.

[0016] Furthermore, embodiments of the present invention also provide a terminal, comprising: a memory and a processor, wherein the memory stores a computer program; wherein, The processor is configured to execute computer programs in memory; When the computer program is executed by the processor, it implements the method for timing data processing as described above.

[0017] The technical solution of this application includes: configuring a simulation environment according to the test parameters of the test case; traversing all predetermined paths of the test case; extracting a netlist file for performing simulation processing from the hardware circuit of the field-programmable gate array (FPGA) chip; configuring predetermined paths through the netlist file and then performing simulation processing in the configured simulation environment; and obtaining timing data from the data obtained from the simulation processing. This embodiment of the invention obtains timing data from the real circuit by performing chip simulation processing through hardware circuitry, thus improving the quality of timing data provided for supporting software tools.

[0018] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0019] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions of the present invention.

[0020] Figure 1 This is a flowchart illustrating a method for time-series data processing according to an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0022] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0023] Figure 1 This is a flowchart illustrating the method for time-series data processing according to an embodiment of the present invention, as shown below. Figure 1 As shown, it includes: Step 101: Configure the simulation environment according to the test parameters of the test case; Step 102: Traverse all predetermined paths of the test case; Step 103: Extract the netlist file used for performing simulation processing from the hardware circuitry of the Field Programmable Gate Array (FPGA) chip; Step 104: After configuring the predetermined path through the netlist file, perform simulation processing in the configured simulation environment; Step 105: Obtain time series data from the data obtained from the simulation processing.

[0024] The embodiments of the present invention perform chip simulation processing through hardware circuits to obtain timing data in real circuits, thereby improving the quality of timing data provided for supporting software tools.

[0025] In one exemplary embodiment, the present invention performs simulation processing through a circuit simulator, for example, through ALPS. In another exemplary embodiment, the present invention determines test parameters with reference to ALPS simulation requirements. In one exemplary embodiment, the test parameters consist of temperature and voltage. In yet another exemplary embodiment, the test parameters include three common temperature values ​​and three common voltage values ​​known to those skilled in the art. Based on a specific test case, the combination of temperature and voltage values ​​corresponding to the test case is pre-set with reference to relevant technologies to form the test parameters corresponding to the test case. In one exemplary embodiment, the predetermined path can be directly determined according to test requirements with reference to relevant principles, and is a path from an input line to an output line in the FPGA chip.

[0026] In one exemplary instance, embodiments of the present invention traverse all predetermined paths of a test case, including: For each pre-selected input line in the test case, the input line, and all loads between the module containing the input line and other modules are added to a preset table to obtain the predetermined path.

[0027] The modules in this embodiment of the invention include programmable logic blocks (PLCs) and clock modules, etc. A line used as an input in a test case is selected as an input line. This input line can be connected to another line on another PLC. This line is then selected as an output line, and the two lines connected together form a predetermined path. The input line is also on a PLC, i.e., the module where the input line resides. This module may contain more than just the input line; it may also contain other lines, which can be internally connected to other lines. The method for obtaining the preset path in this embodiment can be implemented with reference to related technologies. Input lines are selected according to software and upgrade needs; generally, one line of each length is randomly selected.

[0028] In one exemplary instance, after configuring a predetermined path through a netlist file, this embodiment of the invention performs simulation processing in the configured simulation environment, including: After loading a predetermined path configured through a netlist file in the simulation environment, simulation processing is performed by loading a preset excitation signal onto the input line of the loaded predetermined path configured through the netlist file.

[0029] In one exemplary instance, the excitation signal in this embodiment of the invention includes: The predetermined reference voltage value is output sequentially according to a preset strategy, multiplying the reference voltage value by a preset percentage.

[0030] In one exemplary instance, the embodiment of the present invention outputs a voltage value obtained by multiplying a reference voltage value by a preset percentage, which includes: the reference voltage value being multiplied by 0 and then directly changing to the reference voltage value being multiplied by 100%, to obtain the voltage value.

[0031] In one exemplary instance, embodiments of the present invention perform simulation processing by loading a preset excitation signal onto an input line configured with a predetermined path via a netlist file, including: For each input line, starting from zero load, the loads in the predetermined path are sequentially superimposed to obtain all load combinations; For all load combinations obtained through traversal, simulation processing is performed by applying excitation signals to the input lines.

[0032] Once all the expected loads are listed in the embodiments of the present invention, the simulation of different quantities of loads and the data collection can be automated, thereby reducing the manpower and time required.

[0033] In one exemplary instance, after obtaining time-series data from the data obtained through simulation processing, the method of this embodiment of the invention further includes: The acquired timing data is added to a preset table for timing analysis of the FPGA chip.

[0034] This invention provides timing data of the actual circuit through hardware simulation; it is automated, requiring only the given simulation conditions to iterate through all conditions. This embodiment performs simulation in hardware circuits, obtaining timing data from the actual circuit, providing more accurate data for timing optimization in the corresponding software, and offering effective technical support for FPGA application development. Furthermore, this embodiment is automated; only the initial simulation conditions need to be given, and it can automatically iterate through all conditions and automatically collect data, saving significant manpower and time.

[0035] In one exemplary instance, embodiments of the present invention extract a netlist file for performing simulation processing from the hardware circuitry of an FPGA chip, including: When it is determined that the number of modules contained in the predetermined path is greater than a preset value, the netlist of all modules contained in the FPGA chip is extracted, and the extracted netlist of modules is used as the netlist file for performing simulation processing.

[0036] In one exemplary instance, embodiments of the present invention extract a netlist file for performing simulation processing from the hardware circuitry of an FPGA chip, including: When it is determined that the number of modules contained in the predetermined path is less than or equal to a preset value, the netlist of the modules contained in the predetermined path is extracted, and the extracted netlist of the modules contained in the predetermined path is used as the netlist file for performing simulation processing.

[0037] It should be noted that a netlist is used to describe the interconnections between circuit components (modules), and is generally a text file following a relatively simple tagging syntax. In one exemplary instance, the netlist in this embodiment of the invention contains the connections between modules and the circuit connection information within each module. In another exemplary instance, the preset value in this embodiment of the invention can be set by those skilled in the art based on experience; for example, it can be set to 3. When the number of modules in a predetermined path is less than or equal to the preset value, this embodiment of the invention uses a netlist containing only the necessary modules for simulation, reducing the simulation time. In one exemplary instance, the modules included in the predetermined path in this embodiment of the invention may include: the module containing the input lines and the module containing the output lines.

[0038] This invention also provides a computer storage medium storing a computer program, which, when executed by a processor, implements the aforementioned method for implementing timing data processing.

[0039] This invention also provides a terminal, comprising: a memory and a processor, wherein the memory stores a computer program; wherein, The processor is configured to execute computer programs in memory; When a computer program is executed by a processor, it implements the method for processing time-series data as described above.

[0040] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A method for implementing time-series data processing, comprising: Configure the simulation environment according to the test parameters of the test cases; Traverse all predetermined paths of the test case, where the predetermined paths include: each pre-selected input line in the test case, and the path obtained by adding the input line, the module containing the input line, and all loads between other modules to a pre-defined table; Extract the netlist file used for performing simulation processing from the hardware circuitry of the Field Programmable Gate Array (FPGA) chip; After configuring the predetermined path through the netlist file, the simulation process is executed in the configured simulation environment; Time series data is obtained from the data obtained through simulation processing.

2. The method according to claim 1, characterized in that, The step of configuring a predetermined path via a netlist file and then performing simulation processing in the configured simulation environment includes: After loading a predetermined path configured through a netlist file in the simulation environment, simulation processing is performed by loading a preset excitation signal onto the input line of the loaded predetermined path configured through the netlist file.

3. The method according to claim 2, characterized in that, The excitation signal includes: The predetermined reference voltage value is output sequentially according to a preset strategy, multiplying the reference voltage value by a preset percentage.

4. The method according to claim 2 or 3, characterized in that, The simulation processing, which involves loading a preset excitation signal onto the input line of a predefined path configured in the netlist file, includes: For each input line, starting from zero load, the loads in the predetermined path are sequentially superimposed to obtain all load combinations; For all load combinations obtained through traversal, simulation processing is performed by loading the excitation signal onto the input lines.

5. The method according to any one of claims 1-3, characterized in that, After obtaining time-series data from the data obtained from simulation processing, the method further includes: The acquired timing data is added to a preset table for timing analysis of the FPGA chip.

6. The method according to any one of claims 1-3, characterized in that, The extraction of the netlist file for performing simulation processing from the hardware circuitry of the FPGA chip includes: When it is determined that the number of modules contained in the predetermined path is greater than a preset value, the netlist of all modules contained in the FPGA chip is extracted, and the extracted netlist of the modules is used as the netlist file for performing simulation processing.

7. The method according to any one of claims 1-3, characterized in that, The extraction of the netlist file for performing simulation processing from the hardware circuitry of the FPGA chip includes: When it is determined that the number of modules contained in the predetermined path is less than or equal to a preset value, the netlist of the modules contained in the predetermined path is extracted, and the extracted netlist of the modules contained in the predetermined path is used as the netlist file for performing simulation processing.

8. A computer storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the method for timing data processing as described in any one of claims 1 to 7.

9. A terminal, comprising: A memory and a processor, wherein the memory stores a computer program; wherein, The processor is configured to execute computer programs in memory; When the computer program is executed by the processor, it implements the method for processing time-series data as described in any one of claims 1 to 7.

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