一种构建芯片中时钟树的方法、装置及电子设备
By dividing the chip layout into multiple regions and constructing a three-level clock tree, the problems of high clock resource consumption and high latency in existing technologies are solved, achieving higher process tolerance and lower power consumption, and improving the performance of the clock tree.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LOONGSON TECH CORP
- Filing Date
- 2022-11-28
- Publication Date
- 2026-07-17
AI Technical Summary
Existing clock network construction methods require building clock trees separately for multiple clock sources, which leads to increased chip resource consumption, clock latency and power consumption, and insufficient tolerance for on-chip fluctuations and process corners.
The chip layout is divided into multiple regions, and a three-level clock tree is constructed. The first-level clock tree is constructed using anchor points and sink points, the second-level clock tree is formed by cloning clock regeneration units, and the third-level clock tree is constructed according to constraint information, so as to realize the clock sharing of timing units in the same clock domain.
It reduces clock latency and power consumption of the clock network, enhances tolerance to on-chip fluctuations and process variations, reduces chip trace resource usage, and improves clock tree performance and quality.
Smart Images
Figure CN116167329B_ABST