Pixel driving circuit, display panel and display device

Abstract

This disclosure relates to the field of display technology, and proposes a pixel driving circuit, a display panel, and a display device. The pixel driving circuit includes: a driving circuit, a data writing circuit, and a compensation circuit. The driving circuit provides driving current from a second node to a third node based on the voltage of a first node. The data writing circuit responds to a signal from a first gate driving signal terminal to transmit a data signal to the second node. The compensation circuit responds to a signal from a second gate driving signal terminal to connect the first node and a fourth node, with the fourth node connected to the first node. The first gate driving signal terminal outputs an effective level during a hysteresis cancellation phase to transmit the data signal to the second node. The first and second gate driving signal terminals output effective levels during the data writing phase, where the hysteresis cancellation phase precedes the data writing phase. This pixel driving circuit can solve the problem of low brightness in the first frame of a display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, and a display device. Background Technology

[0002] In related technologies, the driving transistors in pixel driving circuits are prone to hysteresis, which affects the display effect of the display panel. For example, when the display panel changes from a black screen to a white screen, the hysteresis of the driving transistors will cause the brightness of the first frame of the display panel to be low, resulting in flickering and ghosting problems.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a pixel driving circuit is provided, the pixel driving circuit comprising: a driving circuit, a data writing circuit, and a compensation circuit; the driving circuit is connected to a first node, a second node, and a third node, and is used to provide a driving current from the second node to the third node based on the voltage of the first node; the data writing circuit is connected to the second node, a data signal terminal, and a first gate driving signal terminal, and is used to transmit the signal of the data signal terminal to the second node in response to a signal from the first gate driving signal terminal; the compensation circuit is connected to the third node, a fourth node, and a second gate driving signal terminal, and is used to connect the third node and the fourth node in response to a signal from the second gate driving signal terminal, the fourth node being connected to the first node; wherein, the first gate driving signal terminal is used to output an effective level during a hysteresis cancellation phase to turn on the data writing circuit and transmit the signal of the data signal terminal to the second node; the first gate driving signal terminal is used to output an effective level during the data writing phase to turn on the data writing circuit and transmit the signal of the data signal terminal to the second node; the second gate driving signal terminal is used to output an effective level during the data writing phase to turn on the first node and the fourth node; and in the same frame period, the hysteresis cancellation phase precedes the data writing phase.

[0005] In an exemplary embodiment of this disclosure, the pixel driving circuit further includes: a light-emitting control circuit, a first reset circuit, a second reset circuit, and a storage circuit. The light-emitting control circuit is connected to a first power supply terminal, a second node, a third node, a fifth node, and an enable signal terminal, and is used to respond to a signal from the enable signal terminal to turn on the first power supply terminal and the second node, and to respond to a signal from the enable signal terminal to turn on the third node and the fifth node. The first reset circuit is connected to the fourth node, a first initial signal terminal, and a first reset signal terminal, and is used to respond to a signal from the first reset signal terminal to transmit a signal from the first initial signal terminal to the fourth node. The second reset circuit is connected to the fifth node, a second initial signal terminal, and a second reset signal terminal, and is used to respond to a signal from the second reset signal terminal to transmit a signal from the second initial signal terminal to the fifth node. The storage circuit is connected between the first node and the first power supply terminal.

[0006] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes an isolation circuit, which is connected to the first node, the fourth node, and the third gate driving signal terminal, and is used to conduct the first node and the fourth node in response to a signal from the third gate driving signal terminal.

[0007] In one exemplary embodiment of this disclosure, the driving circuit includes: a driving transistor, the first terminal of which is connected to the second node, the second terminal of which is connected to the third node, and the gate of which is connected to the first node; the data writing circuit includes: a fourth transistor, the first terminal of which is connected to the data signal terminal, the second terminal of which is connected to the second node, and the gate of which is connected to the first gate driving signal terminal; the compensation circuit includes: a second transistor, the first terminal of which is connected to the fourth node, the second terminal of which is connected to the third node, and the gate of which is connected to the second gate driving signal terminal.

[0008] In one exemplary embodiment of this disclosure, the light-emitting control circuit includes: a fifth transistor and a sixth transistor, wherein the first electrode of the fifth transistor is connected to the first power supply terminal, the second electrode is connected to the second node, and the gate is connected to the enable signal terminal; the first electrode of the sixth transistor is connected to the third node, the second electrode is connected to the fifth node, and the gate is connected to the enable signal terminal; the first reset circuit includes: a first transistor, wherein the first electrode of the first transistor is connected to the first initial signal terminal, the second electrode is connected to the fourth node, and the gate is connected to the first reset signal terminal; the second reset circuit includes: a seventh transistor, wherein the first electrode of the seventh transistor is connected to the second initial signal terminal, the second electrode is connected to the fifth node, and the gate is connected to the second reset signal terminal; the storage circuit includes: a capacitor, wherein the first electrode is connected to the first node, and the second electrode is connected to the first power supply terminal.

[0009] In one exemplary embodiment of this disclosure, the isolation circuit includes: an eighth transistor, wherein the first terminal of the eighth transistor is connected to the first node, the second terminal is connected to the fourth node, and the gate is connected to the third gate drive signal terminal.

[0010] In one exemplary embodiment of this disclosure, the driving circuit includes: a driving transistor, wherein a first terminal of the driving transistor is connected to the second node, a second terminal is connected to the third node, and a gate is connected to the first node; the eighth transistor is an N-type transistor, and the driving transistor is a P-type transistor.

[0011] In one exemplary embodiment of this disclosure, the first gate drive signal terminal and the second gate drive signal terminal are used to receive the same gate drive signal.

[0012] In one exemplary embodiment of this disclosure, the pixel driving circuit is applied to a display panel, the display panel including a gate driving circuit, and the first gate driving signal terminal and the first reset signal terminal are connected to the same gate driving circuit.

[0013] In one exemplary embodiment of this disclosure, the pixel driving circuit is applied to a display panel, the display panel including a gate driving circuit, and the first reset signal terminal and the second reset signal terminal are connected to the same gate driving circuit.

[0014] In an exemplary embodiment of this disclosure, the third gate drive signal terminal is used to output an invalid level during the hysteresis elimination phase to disconnect the first node and the fourth node;

[0015] The third gate drive signal terminal is used to output an effective level during the data writing phase to turn on the first node and the fourth node.

[0016] In one exemplary embodiment of this disclosure, during a frame driving cycle, the third gate driving signal terminal is used to output at least two valid level pulses;

[0017] The hysteresis elimination phase is located between two adjacent effective level pulse periods output by the third gate drive signal terminal.

[0018] In an exemplary embodiment of this disclosure, the third gate drive signal terminal is used to output an effective level during the hysteresis elimination phase to turn on the first node and the fourth node;

[0019] The third gate drive signal terminal is used to output an effective level during the data writing phase to turn on the first node and the fourth node.

[0020] In one exemplary embodiment of this disclosure, during a frame driving cycle, the first gate driving signal terminal is used to output at least two valid pulse signals; wherein, the first gate driving signal terminal is used to output a valid level pulse during the hysteresis cancellation phase to transmit the signal of the data signal terminal to the second node; the first gate driving signal terminal is used to output another valid level pulse during the data writing phase to transmit the signal of the data signal terminal to the second node.

[0021] In an exemplary embodiment of this disclosure, during a frame driving cycle, the first gate driving signal terminal is used to output two valid pulse signals, and the first reset signal terminal is used to output two valid pulse signals.

[0022] The two valid pulses output from the first gate drive signal terminal are later than the two valid pulses output from the first reset signal terminal;

[0023] Alternatively, a valid pulse output from the first gate drive signal terminal may be located between two valid pulses output from the first reset signal terminal, and a valid pulse output from the first reset signal terminal may be located between two valid pulses output from the first gate drive signal terminal.

[0024] In an exemplary embodiment of this disclosure, the data signal terminal is used to output the same data signal during the data writing phase and the hysteresis elimination phase;

[0025] Alternatively, the data signal terminal is used to output a reset signal with a preset voltage during the hysteresis elimination phase.

[0026] According to one aspect of this disclosure, a display panel is provided, the display panel including the pixel driving circuit described above.

[0027] According to one aspect of this disclosure, a display device is provided, the display device including the display panel described above.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0030] Figure 1 A schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0031] Figure 2 for Figure 1 The timing diagram of each control signal in a driving method of the pixel driving circuit shown is shown.

[0032] Figure 3 A schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0033] Figure 4 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0034] Figure 5 for Figure 4 The timing diagram of each control signal in a driving method of the pixel driving circuit shown is shown.

[0035] Figure 6 for Figure 4 The timing diagram of each control signal of the pixel driving circuit in the holding frame is shown.

[0036] Figure 7 for Figure 4 The timing diagram of each control signal in another driving method of the pixel driving circuit shown;

[0037] Figure 8 for Figure 4 The timing diagram of each control signal in another driving method of the pixel driving circuit shown;

[0038] Figure 9 for Figure 2 The diagram shows the brightness change state of the display panel when switching frames in the driving method shown.

[0039] Figure 10 for Figure 5 The diagram shows the brightness change state of the display panel when switching frames in the driving method shown.

[0040] Figure 11 for Figure 7 The diagram shows the brightness change state of the display panel when switching frames in the driving method shown.

[0041] Figure 12 for Figure 8 The diagram shows the brightness change state when the display panel switches frames in the driving method shown. Detailed Implementation

[0042] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0043] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0044] like Figure 1 The diagram shown is a schematic representation of an exemplary embodiment of the pixel driving circuit of this disclosure. The pixel driving circuit includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. Specifically, the first terminal of the driving transistor T3 is connected to the second node N2, the second terminal is connected to the third node N3, and the gate is connected to the first node N1; the first terminal of the eighth transistor T8 is connected to the first node N1, the second terminal is connected to the fourth node N4, and the gate is connected to the third gate driving signal terminal Gate3; the first terminal of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second terminal is connected to the fourth node N4, and the gate is connected to the first reset signal terminal Re1; the first terminal of the second transistor T2 is connected to the fourth node N4, the second terminal is connected to the third node N3, and the gate is connected to the first gate driving signal terminal Gate1; the fourth transistor T4's first terminal is connected to the second node N2, the second terminal is connected to the third node N3, and the gate is connected to the first gate driving signal terminal Gate1; the fourth transistor T4's first terminal is connected to the third node N3, the second terminal is connected to the fourth node N4 ... One transistor T5 is connected to the data signal terminal Da, the second transistor is connected to the second node N2, and the gate is connected to the first gate drive signal terminal Gate1; the first transistor T5 is connected to the first power supply terminal VDD, the second transistor is connected to the second node N2, and the gate is connected to the enable signal terminal EM; the first transistor T6 is connected to the third node N3, the second transistor is connected to the fifth node N5, and the gate is connected to the enable signal terminal EM; the first transistor T7 is connected to the second initial signal terminal Vinit2, the second transistor is connected to the fifth node N5, and the gate is connected to the second reset signal terminal Re2; capacitor C is connected between the first node N1 and the first power supply terminal VDD.

[0045] The pixel driving circuit can be connected to the first electrode of the OLED light-emitting unit, and the second electrode of the OLED light-emitting unit can be connected to the second power supply terminal VSS. Among them, the eighth transistor T8 can be an N-type transistor, and the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors.

[0046] like Figure 2 As shown, Figure 1 The diagram shows the timing diagrams of various control signals in a driving method of the pixel driving circuit. Specifically, EM is the timing diagram for the enable signal terminal, Gate3 is the timing diagram for the third gate driving signal terminal, Re1 is the timing diagram for the first reset signal terminal, and Re2 is the timing diagram for the second reset signal terminal. The driving method of this pixel driving circuit includes: a first reset stage t1, a data writing stage t2, a second reset stage t3, and a light emission stage t4. During the reset phase t1, the first reset signal terminal Re1 outputs a low-level signal, the third gate drive signal terminal G3 outputs a high-level signal, the first transistor T1 and the eighth transistor T8 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1. During the data writing phase t2, the first gate drive signal terminal Gate1 outputs a low-level signal, the third gate drive signal terminal Gate3 outputs a high-level signal, the second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on, and the data signal terminal Da outputs a data signal to input a compensation voltage Vth+Vdata to the first node N1, where Vth is the threshold voltage of the driving transistor T3 and Vdata is the data signal voltage of the data signal terminal. During the second reset phase t3, the second reset signal terminal Re2 outputs a low-level signal, and the second initial signal terminal Vinit2 inputs the second initial signal to the fifth node N5. During the light emission phase t4, the enable signal terminal EM outputs a low-level signal, and the driving transistor T3 outputs a driving current to the third node according to the voltage difference between the first node N1 and the first power supply terminal VDD to drive the OLED light emission unit to emit light.

[0047] However, the driving transistor T3 is prone to hysteresis, which can affect the display effect of the display panel. For example, when the display panel changes from a black screen to a white screen, the hysteresis of the driving transistor T3 can cause the brightness of the first frame of the display panel to be low, resulting in flickering and ghosting.

[0048] Based on this, this exemplary embodiment provides a pixel driving circuit, such as... Figure 3The diagram shown is a schematic representation of an exemplary embodiment of the pixel driving circuit of this disclosure. The pixel driving circuit may include: a driving circuit 1, a data writing circuit 2, and a compensation circuit 3. The driving circuit 1 is connected to a first node N1, a second node N2, and a third node N3, and is used to provide a driving current to the third node N3 via the second node N2 based on the voltage of the first node N1. The data writing circuit 2 is connected to the second node N2, a data signal terminal Da, and a first gate driving signal terminal Gate1, and is used to transmit the signal of the data signal terminal Da to the second node N2 in response to the signal of the first gate driving signal terminal Gate1. The compensation circuit 3 is connected to the third node N3, a fourth node N4, and a second gate driving signal terminal Gate2, and is used to respond to the signal of the second gate driving signal terminal Gate1. The signal of Gate2 connects the third node N3 and the fourth node N4, and the fourth node N4 is connected to the first node N1; wherein, the first gate drive signal terminal Gate1 is used to output an effective level during the hysteresis cancellation phase to transmit the signal of the data signal terminal Da to the second node N2; the first gate drive signal terminal Gate1 is used to output an effective level during the data writing phase to transmit the signal of the data signal terminal Da to the second node N2, and the second gate drive signal terminal Gate2 is used to output an effective level during the data writing phase to turn on the third node N3 and the fourth node N4. In the same frame period, the hysteresis cancellation phase is earlier than the data writing phase.

[0049] In this exemplary embodiment, the effective level is the level that enables the target circuit to be turned on. For example, the effective level of an N-type transistor is a high level, and the effective level of a P-type transistor is a low level.

[0050] The pixel driving circuit provided in this exemplary embodiment can improve the hysteresis phenomenon of the driving circuit by inputting a signal to the second node N2 through the data signal terminal Da during the hysteresis elimination stage before the data writing stage. Specifically, during the hysteresis elimination stage, the signal input from the data signal terminal Da to the second node N2 can be either the data signal output during the data writing stage or a reset signal with a preset voltage magnitude.

[0051] like Figure 4The diagram shown is a schematic representation of another exemplary embodiment of the pixel driving circuit of this disclosure. The pixel driving circuit further includes: a light-emitting control circuit 7, a first reset circuit 4, a second reset circuit 5, and a storage circuit 6. The light-emitting control circuit 7 is connected to a first power supply terminal VDD, a second node N2, a third node N3, a fifth node N5, and an enable signal terminal EM. It is used to respond to the signal of the enable signal terminal EM to turn on the first power supply terminal VDD and the second node N2, and to respond to the signal of the enable signal terminal EM to turn on the third node N3 and the fifth node N5. The first reset circuit 4 is connected to the fourth node N4, a first initial signal terminal Vinit1, and a first reset signal terminal Re1. It is used to respond to the signal of the first reset signal terminal Re1 to transmit the signal of the first initial signal terminal Vinit1 to the fourth node N4. The second reset circuit 5 is connected to the fifth node N5, a second initial signal terminal Vinit2, and a second reset signal terminal Re2. It is used to respond to the signal of the second reset signal terminal Re2 to transmit the signal of the second initial signal terminal Vinit2 to the fifth node N5. The storage circuit 6 is connected between the first node N1 and the first power supply terminal VDD.

[0052] In this exemplary embodiment, as Figure 4 As shown, the pixel driving circuit further includes an isolation circuit 8, which is connected to the first node N1, the fourth node N4, and the third gate driving signal terminal Gate3, and is used to respond to the signal of the third gate driving signal terminal Gate3 to turn on the first node N1 and the fourth node N4.

[0053] In this exemplary embodiment, as Figure 4 As shown, the driving circuit includes: a driving transistor T3, the first terminal of the driving transistor T3 is connected to the second node N2, the second terminal is connected to the third node N3, and the gate is connected to the first node N1; the data writing circuit 2 includes: a fourth transistor T4, the first terminal of the fourth transistor T4 is connected to the data signal terminal Da, the second terminal is connected to the second node N2, and the gate is connected to the first gate driving signal terminal Gate1; the compensation circuit 3 includes: a second transistor T2, the first terminal of the second transistor T2 is connected to the fourth node N4, the second terminal is connected to the third node N3, and the gate is connected to the second gate driving signal terminal Gate2.

[0054] In this exemplary embodiment, as Figure 4As shown, the light-emitting control circuit 7 includes: a fifth transistor T5 and a sixth transistor T6. The first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the second node N2, and the gate is connected to the enable signal terminal EM. The first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the fifth node N5, and the gate is connected to the enable signal terminal EM. The first reset circuit 4 includes: a first transistor T1. The first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode is connected to the fourth node N4, and the gate is connected to the first reset signal terminal Re1. The second reset circuit 5 includes: a seventh transistor T7. The first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the second electrode is connected to the fifth node N5, and the gate is connected to the second reset signal terminal Re2. The storage circuit 6 includes: a capacitor C. The first electrode of the capacitor C is connected to the first node N1, and the second electrode is connected to the first power supply terminal VDD.

[0055] In this exemplary embodiment, as Figure 4 As shown, the isolation circuit 8 includes an eighth transistor T8, the first terminal of the eighth transistor T8 is connected to the first node N1, the second terminal is connected to the fourth node N4, and the gate is connected to the third gate drive signal terminal Gate3.

[0056] In this exemplary embodiment, as Figure 4 As shown, the pixel driving circuit can be connected to the first electrode of the OLED light-emitting unit, and the second electrode of the OLED light-emitting unit can be connected to the second power supply terminal VSS. The eighth transistor T8 can be an N-type transistor, while the first transistor T1, second transistor T2, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 can be P-type transistors. The eighth transistor T8 can be an N-type oxide transistor, and it has a smaller leakage current, thereby reducing the leakage current of the first node N1 in the light-emitting stage.

[0057] In this exemplary embodiment, the first gate driving signal terminal Gate1 can be multiplexed as the second gate driving signal terminal Gate2. The pixel driving circuit is applied to a display panel, which includes a first gate driving circuit. The first gate driving circuit may include multiple cascaded first shift register units, and the output terminals of the multiple first shift register units sequentially output shift signals. The first reset signal terminal Re1 and the second reset signal terminal can be connected to the same first gate driving circuit. For example, the first reset signal terminal Re1 in the nth row pixel driving circuit can be connected to the output terminal of the nth stage first shift register unit, and the second reset signal terminal Re2 in the nth row pixel driving circuit can be connected to the output terminal of the (n+1)th stage first shift register unit, where n is a positive integer greater than or equal to 1. The first gate driving signal terminal Gate1 and the first reset signal terminal Re1 can also be connected to the first gate driving circuit. For example, the first reset signal terminal Re1 in the nth row pixel driving circuit can be connected to the output terminal of the nth stage first shift register unit, and the first gate driving signal terminal Gate1 in the nth row pixel driving circuit can be connected to the output terminal of the (n+m)th stage first shift register unit, where m is a positive integer greater than or equal to 2.

[0058] like Figure 5 As shown, Figure 4 The diagram shows the timing diagrams of various control signals in a driving method of the pixel driving circuit. Specifically, EM is the timing diagram for the enable signal terminal, Gate1 is the timing diagram for the first gate driving signal terminal, Gate2 is the timing diagram for the second gate driving signal terminal, Gate3 is the timing diagram for the third gate driving signal terminal, Re1 is the timing diagram for the first reset signal terminal, and Re2 is the timing diagram for the second reset signal terminal. The driving method of this pixel driving circuit includes: a first reset stage t1, a second reset stage t2, a third reset stage t3, a fourth reset stage t4, a hysteresis cancellation stage t5, a data writing stage t6, and a light emission stage t7.

[0059] In the first reset phase t1, the third gate drive signal terminal Gate3 outputs a high-level signal, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 and the eighth transistor T8 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1; in the second reset phase t2, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal vinit2 inputs the second initial signal to the fifth node N5; in the third reset phase t3, the first reset signal terminal Re1 and the third gate drive signal terminal Gate3 output low-level signals, the eighth transistor T8 is turned off, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the fourth node N4; in the fourth reset phase t4, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal vinit2 inputs the first initial signal to the fifth node N5. The fifth node N5 receives the second initial signal. During the hysteresis cancellation phase t5, the first gate drive signal terminal Gate1, the second gate drive signal terminal Gate2, and the third gate drive signal terminal Gate3 output low-level signals. The eighth transistor T8 is turned off, and the second transistor T2 and the fourth transistor T4 are turned on. The data signal terminal Da inputs data signals or reset signals to the second node N2 and the third node N3 to improve the hysteresis of the driving transistor T3. During the data writing phase t6, the third gate drive signal terminal Gate3 outputs a high-level signal, the first gate drive signal terminal Gate1 and the second gate drive signal terminal Gate2 output low-level signals, and the second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on. The data signal terminal Da outputs a data signal to write a voltage Vdata+Vth to node N, where Vdata is the data signal voltage and Vth is the threshold voltage of the driving transistor T3. During the light emission phase t7, the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in capacitor C.

[0060] The formula for the output current of the driving transistor is as follows:

[0061] I = (μWCox / 2L)(Vgs-Vth) 2

[0062] Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor.

[0063] Based on the above formula for the output current of the driving transistor, substituting the gate voltage Vdata+Vth and the source voltage Vdd of the driving transistor in the pixel driving circuit of this disclosure into the above formula, we can obtain: the output current of the driving transistor in the pixel driving circuit of this disclosure is I=(μWCox / 2L)(Vdata+Vth-Vdd-Vth). 2 Where Vdd is the voltage at the first power supply terminal VDD.

[0064] In this exemplary embodiment, as Figure 5 As shown, the third gate drive signal terminal Gate3 can be used to output two valid level pulses, and the hysteresis cancellation phase can be located between two adjacent valid level pulse periods output by the third gate drive signal terminal Gate3. Figure 5 As shown, in one frame drive cycle, the first gate drive signal terminal Gate1 can be used to output two valid pulse signals; wherein, the first gate drive signal terminal Gate1 is used to output a valid level pulse during the hysteresis cancellation phase to transmit the signal of the data signal terminal Da to the second node N2; the first gate drive signal terminal Gate1 can be used to output another valid level pulse during the data writing phase to transmit the signal of the data signal terminal Da to the second node N2. Figure 5 As shown, in one frame driving cycle, the first gate driving signal terminal Gate1 can be used to output two valid pulse signals, and the first reset signal terminal Re1 can also be used to output two valid pulse signals.

[0065] In this exemplary embodiment, the display panel applying the pixel driving circuit may include a second gate driving circuit. The second gate driving circuit can provide an enable signal to an enable signal terminal. The second gate driving circuit may include multiple cascaded second shift register units, and these multiple stages of second shift register units can sequentially output shift signals. The enable signal terminals in the Nth row pixel driving circuit and the N+1th row pixel driving circuit can be connected to the output terminal of the same stage of the second shift register unit, where N is an odd number greater than or equal to 1. The display panel applying the pixel driving circuit may also include a third gate driving circuit. The third gate driving circuit can provide a signal to a third gate driving signal terminal. The third gate driving circuit may include multiple cascaded third shift register units, and these multiple stages of third shift register units can sequentially output shift signals. The third gate driving signal terminals in the Nth row pixel driving circuit and the N+1th row pixel driving circuit can be connected to the output terminal of the same stage of the third shift register unit, where N is an odd number greater than or equal to 1.

[0066] In other exemplary embodiments, the first gate drive signal terminal and the second gate drive signal terminal may also output different gate drive signals. Thus, the first initial signal terminal Vinit1 can input a first initial signal to the third node N3 through the first transistor and the second transistor T2 to reset the third node N3.

[0067] In this exemplary embodiment, the display panel including the pixel driving circuit described above may include scan frames and hold frames that are displayed alternately in sequence, and the driving method for the scan frames may be as follows: Figure 5 As shown. Figure 6 As shown, Figure 4 The diagram shows the timing of the control signals of the pixel driving circuit in the hold frame. EM is the timing diagram of the enable signal terminal, Gate1 is the timing diagram of the first gate drive signal terminal, Gate2 is the timing diagram of the second gate drive signal terminal, Gate3 is the timing diagram of the third gate drive signal terminal, Re1 is the timing diagram of the first reset signal terminal, and Re2 is the timing diagram of the second reset signal terminal. Unlike the scan frame, in the hold frame, the third gate drive signal terminal Gate3 continuously outputs a low-level signal to turn off the eighth transistor T8. In the hold frame, the data signal terminal Da does not rewrite data signals to the first node N1.

[0068] like Figure 7 As shown, Figure 4 The diagram shows the timing of each control signal in another driving method of the pixel driving circuit. EM is the timing diagram of the enable signal terminal, Gate1 is the timing diagram of the first gate driving signal terminal, Gate2 is the timing diagram of the second gate driving signal terminal, Gate3 is the timing diagram of the third gate driving signal terminal, Re1 is the timing diagram of the first reset signal terminal, and Re2 is the timing diagram of the second reset signal terminal. The driving method of this pixel driving circuit includes: a first reset stage t1, a second reset stage t2, a hysteresis cancellation stage t3, a third reset stage t4, a fourth reset stage t5, a data writing stage t6, and a light emission stage t7.

[0069] In the first reset phase t1, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the fourth node N4. In the second reset phase t2, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs the second initial signal to the fifth node N5. In the hysteresis elimination phase t3, the first gate drive signal terminal Gate1 and the second gate drive signal terminal Gate2 output low-level signals, the third gate drive signal terminal Gate3 outputs a high-level signal, the eighth transistor T8, the second transistor T2, and the fourth transistor T4 are turned on, and the data signal terminal Da inputs a data signal to the second node N2 to improve the hysteresis of the driving transistor T3. In the third reset phase t4, the third gate drive signal terminal Gate3 outputs a high-level signal. In the first reset phase t5, the second reset signal terminal Re1 outputs a low-level signal, turning on the first transistor T1 and the eighth transistor T8. The first initial signal terminal Vinit1 inputs the first initial signal to the first node N1. In the fourth reset phase t5, the second reset signal terminal Re2 outputs a low-level signal, turning on the seventh transistor T7. The second initial signal terminal Vinit2 inputs the second initial signal to the fifth node N5. In the data writing phase t6, the third gate drive signal terminal Gate3 outputs a high-level signal, while the first gate drive signal terminal Gate1 and the second gate drive signal terminal Gate2 output low-level signals. The second transistor T2, the fourth transistor T4, and the eighth transistor T8 turn on. The data signal terminal Da outputs a data signal to write a voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. In the light-emitting phase t7, the enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6 and the fifth transistor T5. The driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in capacitor C.

[0070] and Figure 5 Compared to the driving method of the pixel driving circuit shown, Figure 7 The driving methods shown differ in that: Figure 5 In the driving method shown, the third gate drive signal terminal Gate3 is used to output an invalid level during the hysteresis elimination phase to disconnect the first node N1 and the fourth node N4; Figure 7 In the driving method shown, the third gate drive signal terminal Gate3 is used to output an effective level during the hysteresis cancellation phase to turn on the first node N1 and the fourth node N4. Furthermore, in Figure 5 In the driving method shown, the two valid pulses output by the first gate drive signal terminal Gate1 are later than the two valid pulses output by the first reset signal terminal Re1; Figure 7In the driving method shown, a valid pulse output by the first gate drive signal terminal Gate1 is located between two valid pulses output by the first reset signal terminal Re1, and a valid pulse output by the first reset signal terminal Re1 is located between two valid pulses output by the first gate drive signal terminal Gate1.

[0071] like Figure 8 As shown, Figure 4 The diagram shows the timing of each control signal in another driving method of the pixel driving circuit. EM is the timing diagram of the enable signal terminal, Gate1 is the timing diagram of the first gate driving signal terminal, Gate2 is the timing diagram of the second gate driving signal terminal, Gate3 is the timing diagram of the third gate driving signal terminal, Re1 is the timing diagram of the first reset signal terminal, and Re2 is the timing diagram of the second reset signal terminal. The driving method of this pixel driving circuit includes: a first reset stage t1, a second reset stage t2, a hysteresis cancellation stage t3, a third reset stage t4, a fourth reset stage t5, a data writing stage t6, and a light emission stage t7.

[0072] and Figure 7 The pixel driving circuit shown differs in its driving method. Figure 8 In the first reset phase of the driving method shown, the third gate drive signal terminal G3 outputs a high-level signal, the eighth transistor T8 and the first transistor T1 are both turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1.

[0073] In this exemplary embodiment, as Figure 5-8 As shown, the effective pulse widths of the first reset signal terminal Re1, the second reset signal terminal Re2, the first gate drive signal terminal Gate1, and the second gate drive signal terminal Gate2 can be equal. The effective pulse width of the third gate drive signal terminal Gate3 can be 5-15 times the effective pulse width of the first reset signal terminal Re1. For example, the effective pulse width of the third gate drive signal terminal Gate3 can be 5, 8, 10, 12, or 15 times the effective pulse width of the first reset signal terminal Re1. In this exemplary embodiment, the effective pulse widths of the first reset signal terminal Re1, the second reset signal terminal Re2, the first gate drive signal terminal Gate1, and the second gate drive signal terminal Gate2 can be less than 1H, and the effective pulse width of the third gate drive signal terminal Gate3 can be 8H, 12H, etc. Here, 1H represents one cycle duration.

[0074] It should be understood that, in other exemplary embodiments, the above-described driving method can also be applied to pixel driving circuits with other structures. For example, the above-described driving method can be applied to the pixel driving circuit of the 7T1C, i.e. Figure 4There is no eighth transistor T8 between the first node N1 and the fourth node N4.

[0075] like Figure 9-12 As shown, Figure 9 for Figure 2 The diagram shows the brightness change state of the display panel when switching frames in the driving method shown. Figure 10 for Figure 5 The diagram shows the brightness change state of the display panel when switching frames in the driving method shown. Figure 11 for Figure 7 The diagram shows the brightness change state of the display panel when switching frames in the driving method shown. Figure 12 for Figure 8 The diagram shows the brightness changes of the display panel during frame switching in the driving method shown. The horizontal axis represents time, and the vertical axis represents brightness. Figure 9-12 This shows the brightness state of the first frame during the transition from a black screen to a white screen. According to... Figure 9-12 It can be seen that, Figure 2 The driving method shown can only achieve 34% of the target brightness in the first frame. Figure 5 The driving method shown can achieve 75% of the target brightness in the first frame. Figure 7 The driving method shown can achieve 50% of the target brightness in the first frame. Figure 8 The driving method shown can achieve 65% of the target brightness in the first frame.

[0076] This exemplary embodiment also provides a display panel and a display device. The display panel includes the pixel driving circuit described above. The display device includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0077] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0078] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments and features described in these embodiments can be combined to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

[0079] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A pixel driving circuit, characterized by comprising: The pixel driving circuit includes: A driving circuit, connected to a first node, a second node, and a third node, is used to provide a driving current from the second node to the third node based on the voltage of the first node. A data writing circuit is connected to the second node, the data signal terminal, and the first gate drive signal terminal, and is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the second node; A compensation circuit is connected to the third node, the fourth node, and the second gate drive signal terminal, and is used to respond to the signal of the second gate drive signal terminal to connect the third node and the fourth node, wherein the fourth node is connected to the first node; Wherein, the first gate drive signal terminal is used to output an effective level during the hysteresis elimination stage to turn on the data writing circuit and transmit the signal of the data signal terminal to the second node; The first gate drive signal terminal is used to output an effective level during the data writing phase to turn on the data writing circuit and transmit the signal of the data signal terminal to the second node. The second gate drive signal terminal is used to output an effective level during the data writing phase to turn on the first node and the fourth node. In the same frame period, the hysteresis cancellation phase is earlier than the data writing phase. The pixel driving circuit also includes: An isolation circuit is provided, which connects the first node, the fourth node, and the third gate drive signal terminal, and is used to respond to the signal of the third gate drive signal terminal to turn on the first node and the fourth node. The third gate drive signal terminal is used to output an invalid level during the hysteresis elimination phase to disconnect the first node and the fourth node; The third gate drive signal terminal is used to output an effective level during the data writing phase to turn on the first node and the fourth node; Alternatively, the third gate drive signal terminal is used to output an effective level during the hysteresis elimination phase to turn on the first node and the fourth node; The third gate drive signal terminal is used to output an effective level during the data writing phase to turn on the first node and the fourth node.

2. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes: A light-emitting control circuit is connected to a first power supply terminal, a second node, a third node, a fifth node, and an enable signal terminal. It is used to respond to a signal from the enable signal terminal to turn on the first power supply terminal and the second node, and to respond to a signal from the enable signal terminal to turn on the third node and the fifth node. A first reset circuit is connected to the fourth node and a first initial signal terminal. The first reset signal terminal is used to respond to the signal of the first reset signal terminal to transmit the signal of the first initial signal terminal to the fourth node. The second reset circuit is connected to the fifth node, the second initial signal terminal, and the second reset signal terminal, and is used to respond to the signal of the second reset signal terminal to transmit the signal of the second initial signal terminal to the fifth node. The storage circuit is connected between the first node and the first power supply terminal.

3. The pixel driving circuit according to claim 1, characterized in that, The driving circuit includes: A driving transistor, wherein the first terminal of the driving transistor is connected to the second node, the second terminal is connected to the third node, and the gate is connected to the first node; The data writing circuit includes: The fourth transistor has its first terminal connected to the data signal terminal, its second terminal connected to the second node, and its gate connected to the first gate drive signal terminal. The compensation circuit includes: The second transistor has its first terminal connected to the fourth node, its second terminal connected to the third node, and its gate connected to the second gate drive signal terminal.

4. The pixel driving circuit according to claim 2, characterized in that, The light-emitting control circuit includes: The fifth transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the second node, and its gate connected to the enable signal terminal. The sixth transistor has its first terminal connected to the third node, its second terminal connected to the fifth node, and its gate connected to the enable signal terminal. The first reset circuit includes: A first transistor, wherein the first terminal of the first transistor is connected to the first initial signal terminal, the second terminal is connected to the fourth node, and the gate is connected to the first reset signal terminal; The second reset circuit includes: The seventh transistor has its first terminal connected to the second initial signal terminal, its second terminal connected to the fifth node, and its gate connected to the second reset signal terminal. The storage circuit includes: The capacitor has its first electrode connected to the first node and its second electrode connected to the first power supply terminal.

5. The pixel driving circuit according to claim 1, characterized in that, The isolation circuit includes: The eighth transistor has its first terminal connected to the first node, its second terminal connected to the fourth node, and its gate connected to the third gate drive signal terminal.

6. The pixel driving circuit of claim 5, wherein, The driving circuit includes: A driving transistor, wherein the first terminal of the driving transistor is connected to the second node, the second terminal is connected to the third node, and the gate is connected to the first node; The eighth transistor is an N-type transistor, and the driving transistor is a P-type transistor.

7. The pixel driving circuit according to any one of claims 1-2, wherein, The first gate drive signal terminal and the second gate drive signal terminal are used to receive the same gate drive signal.

8. The pixel driving circuit of claim 2, wherein, The pixel driving circuit is applied to the display panel, which includes a gate driving circuit. The first gate driving signal terminal and the first reset signal terminal are connected to the same gate driving circuit.

9. The pixel driving circuit of claim 2, wherein, The pixel driving circuit is applied to the display panel, which includes a gate driving circuit. The first reset signal terminal and the second reset signal terminal are connected to the same gate driving circuit.

10. The pixel driving circuit of claim 9, wherein, During one frame driving cycle, the third gate driving signal terminal is used to output at least two valid level pulses; The hysteresis elimination phase is located between two adjacent effective level pulse periods output by the third gate drive signal terminal.

11. The pixel driving circuit according to claim 1, characterized in that, During one frame driving cycle, the first gate driving signal terminal is used to output at least two valid pulse signals; Wherein, the first gate drive signal terminal is used to output an effective level pulse during the hysteresis elimination phase to transmit the signal of the data signal terminal to the second node; The first gate drive signal terminal is used to output another valid level pulse during the data writing phase to transmit the signal from the data signal terminal to the second node.

12. The pixel driving circuit according to claim 2, characterized in that, During one frame drive cycle, the first gate drive signal terminal is used to output two valid pulse signals, and the first reset signal terminal is used to output two valid pulse signals. The two valid pulses output from the first gate drive signal terminal are later than the two valid pulses output from the first reset signal terminal; Alternatively, a valid pulse output from the first gate drive signal terminal may be located between two valid pulses output from the first reset signal terminal, and a valid pulse output from the first reset signal terminal may be located between two valid pulses output from the first gate drive signal terminal.

13. The pixel driving circuit according to claim 1, characterized in that, The data signal terminal is used to output the same data signal during the data writing phase and the hysteresis elimination phase; Alternatively, the data signal terminal is used to output a reset signal with a preset voltage during the hysteresis elimination phase.

14. A display panel, characterized in that, Includes the pixel driving circuit according to any one of claims 1-13.

15. A display device, characterized in that, Includes the display panel as described in claim 14.

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