Three-dimensional chip, preparation method and electronic device

Abstract

The application discloses a three-dimensional chip, a preparation method and an electronic device, relates to the technical field of chips, and can improve the performance and reliability of the three-dimensional chip. The three-dimensional chip comprises a first chip unit, a second chip unit, and a basic bonding unit. The first chip unit is provided with a first circuit. The second chip unit is provided with a second circuit. The first circuit and the second circuit are electrically connected through the basic bonding unit. The basic bonding unit is associated with at least one redundant bonding unit. The redundant bonding unit is connected in parallel with the corresponding basic bonding unit between the same first circuit and the same second circuit.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a three-dimensional chip, a fabrication method, and an electronic device. Background Technology

[0002] In 3D ICs (three-dimensional ICs), HB cells (Hybrid bonding cells) are used to connect two chips. The only data exchange path between the two chips is the HB cell, and the number of HB cells directly affects the performance and reliability of the 3D chip.

[0003] However, in existing 3D chips, the number and location of HB cells depend on the chip's port locations and the requirements of chip circuit connections, without considering the performance and reliability of the 3D chip. Summary of the Invention

[0004] This application provides a three-dimensional chip, a fabrication method, and an electronic device, which can improve the performance and reliability of the three-dimensional chip.

[0005] A first aspect of this application provides a three-dimensional chip, comprising:

[0006] A first chip unit, wherein a first circuit is provided on the first chip unit;

[0007] The second chip unit has a second circuit on it;

[0008] A basic bonding unit is provided, through which the first circuit and the second circuit are electrically connected. The basic bonding unit is associated with at least one redundant bonding unit, and the redundant bonding unit and the corresponding basic bonding unit are connected in parallel between the same first circuit and the same second circuit.

[0009] In some embodiments, the first circuit includes a first conductive portion, the second circuit includes a second conductive portion, and the first conductive portion and the second conductive portion are electrically connected through the basic bonding unit;

[0010] The orthographic projection of the second conductive portion onto the first chip unit is the first projection. The overlapping area between the region where the first conductive portion, which is electrically connected to the second conductive portion, is located and the first projection is the bonding region. The basic bonding unit and the redundant bonding unit that are electrically connected to the same first conductive portion and the same second conductive portion are both disposed within the bonding region.

[0011] In some embodiments, the area of ​​the first projection is larger than the area of ​​the region where the first conductive part is electrically connected to the second conductive part.

[0012] In some embodiments, the first chip unit includes a first top metal layer, and the first conductive portion is disposed within the first top metal layer;

[0013] The second chip unit includes a second top metal layer, and the second conductive portion is disposed within the second top metal layer;

[0014] The basic bonding unit and the redundant bonding unit are disposed between the first top metal layer and the second top metal layer.

[0015] In some embodiments, the first chip unit includes a first active layer, which is disposed on the side of the first top metal layer away from the second chip unit, and a first device is disposed within the first active layer;

[0016] The second chip unit includes a second active layer, which is disposed on the side of the second top metal layer away from the first chip unit, and a second device is disposed within the second active layer;

[0017] The first circuit includes the first device, and the first device and the first conductive part in the first circuit are electrically connected;

[0018] The second circuit includes the second device, and the second device and the second conductive part in the second circuit are electrically connected.

[0019] In some implementations, the number of redundant bonding units connected in parallel with the basic bonding unit between the same first circuit and the same second circuit is at least two.

[0020] In some implementations, the redundant bonding units connected in parallel with the basic bonding unit between the same first circuit and the same second circuit are arranged in an array.

[0021] A second aspect of this application provides a method for fabricating a three-dimensional chip, used to fabricate the three-dimensional chip as described in the first aspect, the method comprising:

[0022] A first circuit, a basic bonding unit, and a redundant bonding unit are disposed on the first chip unit, wherein the basic bonding unit and the redundant bonding unit are both electrically connected to the first circuit;

[0023] A second circuit is set on the second chip unit;

[0024] The first chip unit and the second chip unit are bonded together through the basic bonding unit and the redundant bonding unit to electrically connect the first circuit and the second circuit through the basic bonding unit. The basic bonding unit is associated with at least one redundant bonding unit, and the redundant bonding unit is connected in parallel with the corresponding basic bonding unit between the same first circuit and the same second circuit.

[0025] In some embodiments, when the first circuit includes a first conductive portion and the second circuit includes a second conductive portion, the step of setting the first circuit, the basic bonding unit, and the redundant bonding unit on the first chip unit includes:

[0026] A first conductive portion is disposed on the first chip unit;

[0027] The basic bonding unit and the redundant bonding unit are disposed in the area where the first conductive part is located, so that both the basic bonding unit and the redundant bonding unit are electrically connected to the first conductive part;

[0028] The provision of a second circuit on the second chip unit includes:

[0029] A second conductive portion is disposed on the second chip unit, wherein the orthographic projection of the second conductive portion on the first chip unit is a first projection, and the first projection covers the area where the basic bonding unit and the redundant bonding unit are located;

[0030] The step of bonding the first chip unit and the second chip unit together through the basic bonding unit and the redundant bonding unit to electrically connect the first circuit and the second circuit through the basic bonding unit includes:

[0031] The first chip unit and the second chip unit are bonded together through the basic bonding unit and the redundant bonding unit to electrically connect the first circuit and the second circuit through the basic bonding unit. The overlapping area between the region of the first conductive part electrically connected to the second conductive part and the first projection is the bonding region. The basic bonding unit and the redundant bonding unit electrically connecting the same first conductive part and the same second conductive part are both disposed in the bonding region.

[0032] In some embodiments, the provision of the second conductive portion on the second chip unit includes:

[0033] The second conductive portion is disposed on the second chip unit, wherein the area of ​​the first projection is larger than the area of ​​the region where the first conductive portion is electrically connected to the second conductive portion.

[0034] A third aspect of this application provides an electronic device, the electronic device including the three-dimensional chip as described in the first aspect.

[0035] The three-dimensional chip, fabrication method, and electronic device provided in this application embodiment, by setting the basic bonding unit and associated redundant bonding units in parallel between the same first and second circuits, can reduce the connection resistance between the connected first and second circuits and reduce the connection voltage drop, thereby reducing the connection energy consumption of the connected first and second circuits and enhancing the electrical connection stability of the connected first and second circuits. This makes the signal transmission between the connected first and second circuits more stable, reduces the connection resistance between the connected first and second circuits, and also facilitates signal transmission with varying resistance, thereby improving the performance and reliability of the three-dimensional chip. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of a three-dimensional chip provided in an embodiment of this application;

[0037] Figure 2 A partial top view of a first chip unit provided in an embodiment of this application;

[0038] Figure 3 A schematic flowchart illustrating a method for fabricating a three-dimensional chip according to an embodiment of this application;

[0039] Figure 4 This is a schematic structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0040] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0041] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0042] In 3D chips, bonding units are used to connect two chips. The only data exchange path between the two chips is the HB cell, and the number of HB cells directly affects the performance and reliability of the 3D chip. However, in existing 3D chips, the number and location of HB cells depend on the chip's port locations and the requirements of chip wiring connections, without considering the performance and reliability of the 3D chip.

[0043] In view of this, embodiments of this application provide a three-dimensional chip, a fabrication method, and an electronic device, which can improve the performance and reliability of the three-dimensional chip.

[0044] A first aspect of this application provides a three-dimensional chip. Figure 1 This is a schematic diagram of a three-dimensional chip structure provided in an embodiment of this application. Figure 1 As shown in the embodiments of this application, the three-dimensional chip includes: a first chip unit 100, on which a first circuit is disposed; a second chip unit 200, on which a second circuit is disposed; and a base bonding unit 300, through which the first circuit and the second circuit are electrically connected, wherein the base bonding unit is associated with at least one redundant bonding unit 400, and the redundant bonding unit 400 and the corresponding base bonding unit 300 are connected in parallel between the same first circuit and the same second circuit. The base bonding unit 300 and the redundant bonding unit 400 may be made of the same material and may have the same shape; the embodiments of this application do not impose specific limitations on either. Figure 1 The first chip unit 100 in the three-dimensional chip shown can be used as the bottom chip, and the second chip unit 200 can be used as the top chip. This application does not make specific limitations in the embodiments. Figure 1 The first and second circuits are not shown. Figure 1The number of redundant bonding units 400 and basic bonding units 300 shown are merely illustrative. The number of both the first and second circuits can be multiple, determined by the internal inherited circuit structure of the chip; this application does not impose specific limitations on these numbers.

[0045] It should be noted that the basic bonding unit 300 is used to meet the basic electrical connection requirements between the first circuit and the second circuit. Therefore, the number and position of the basic bonding units 300 are set according to the basic electrical requirements of the specific electrical connection between the first circuit and the second circuit, and the number and position of the basic bonding units 300 are relatively fixed. The redundant bonding unit 400 is an extra bonding unit set on the basis of setting the basic bonding unit 300 to meet the basic electrical connection requirements. The function of the redundant bonding unit 400 is to strengthen the electrical connection between the first circuit and the second circuit. The basic bonding unit 300 and the associated redundant bonding unit 400 are connected in parallel between the first circuit and the second circuit, which can reduce the connection resistance between the connected first circuit and the second circuit, reduce the connection voltage drop, reduce the connection energy consumption of the connected first circuit and the second circuit, enhance the electrical connection stability of the connected first circuit and the second circuit, make the signal transmission between the connected first circuit and the second circuit more stable, reduce the connection resistance between the connected first circuit and the second circuit, and also facilitate the signal transmission of some resistors, thereby improving the performance and reliability of the three-dimensional chip.

[0046] The three-dimensional chip provided in this application embodiment, by setting the basic bonding unit 300 and the associated redundant bonding unit 400 in parallel between the same first circuit and second circuit, can reduce the connection resistance between the connected first circuit and second circuit, reduce the connection voltage drop, reduce the connection energy consumption of the connected first circuit and second circuit, enhance the electrical connection stability of the connected first circuit and second circuit, make the signal transmission between the connected first circuit and second circuit more stable, reduce the connection resistance between the connected first circuit and second circuit, and also facilitate the signal transmission of some resistors, thereby improving the performance and reliability of the three-dimensional chip.

[0047] In some embodiments, the first circuit includes a first conductive portion, and the second circuit includes a second conductive portion. The first conductive portion and the second conductive portion are electrically connected through a base bonding unit. The orthographic projection of the second conductive portion on the first chip unit is the first projection. The overlapping area between the region where the first conductive portion, which is electrically connected to the second conductive portion, is located and the first projection is the bonding region. The base bonding unit and redundant bonding unit that electrically connect the same first conductive portion and the same second conductive portion are both disposed within the bonding region. It should be noted that the first conductive portion and the second conductive portion can be conductive lines, leads, metal pads, or conductive layers, etc., and the embodiments of this application do not specifically limit them.

[0048] For example, Figure 2 This is a partial top view of a first chip unit provided in an embodiment of this application. Figure 2 As shown, the region where the first conductive part of the first chip unit 100 is located is the first region 101, in which a basic bonding unit 300 and a redundant bonding unit 400 are disposed. The first region 101 includes a redundant region 102, in which a redundant bonding unit 400 is disposed. The orthographic projection of the second conductive part on the first chip unit 100 is the first projection 103. The overlapping region of the region where the first conductive part (the first region 101) is electrically connected to the second conductive part and the first projection 103 is the bonding region 104. The basic bonding unit 300 and the redundant bonding unit 400 that are electrically connected to the same first conductive part and the same second conductive part are both disposed in the bonding region 104. Figure 2 The positions and numbers of the basic bonding unit 300 and redundant bonding unit 400, and the size of the bonding region 104 shown are illustrative and are not intended to limit the specific implementation of this application.

[0049] In some embodiments, at least two redundant bonding units 400 are connected in parallel with the basic bonding unit 300 between the same first circuit and the same second circuit. In situations where space is limited, providing at least two redundant bonding units 400 can also enhance the stability between the connected first and second circuits.

[0050] In some embodiments, the area of ​​the first projection is larger than the area of ​​the region where the first conductive part is electrically connected to the second conductive part.

[0051] For example, refer to Figure 2The area of ​​the first projection 103 is larger than the area of ​​the region where the first conductive part is electrically connected to the second conductive part (first region 101). During the design phase of the three-dimensional chip, the area of ​​the second conductive part can be appropriately increased based on the first conductive part on the first chip unit 100, while meeting the basic electrical connection requirements. That is, the area of ​​the orthographic projection (first projection 103) of the second conductive part on the first chip unit 100 can be increased, which can increase the area of ​​the bonding region 104, that is, increase the area of ​​the redundant region 102, thus enabling the setting of a larger number of redundant bonding units.

[0052] The three-dimensional chip provided in this application embodiment, by appropriately increasing the area of ​​the second conductive part (i.e., increasing the area of ​​the orthographic projection (first projection 103) of the second conductive part on the first chip unit 100 while meeting the basic electrical connection requirements, can effectively increase the area of ​​the bonding region 104, i.e., increase the area of ​​the redundant region 102, thereby enabling the setting of a larger number of redundant bonding units 400. By setting as many redundant bonding units 400 as possible, while ensuring that the basic bonding unit 300 meets the basic electrical connection requirements between the first and second circuits, the connection resistance between the connected first and second circuits can be reduced, the connection voltage drop can be reduced, the connection energy consumption of the connected first and second circuits can be reduced, the electrical connection stability of the connected first and second circuits can be enhanced, the signal transmission between the connected first and second circuits can be made more stable, the connection resistance between the connected first and second circuits can be reduced, and the signal transmission of some resistance dimming can also be facilitated, thereby improving the performance of the three-dimensional chip.

[0053] In some implementations, redundant bonding units 400 connected in parallel with the basic bonding unit 300 between the same first circuit and the same second circuit are arranged in an array.

[0054] For example, refer to Figure 2 Multiple redundant bonding units 400 are arranged in an array, which enables relatively uniform signal transmission between each redundant bonding unit 400 and provides a stable and uniform electrical connection for the first circuit and the second circuit.

[0055] In some embodiments, the first chip unit includes a first top metal layer, within which a first conductive portion is disposed; the second chip unit includes a second top metal layer, within which a second conductive portion is disposed; a basic bonding unit and a redundant bonding unit are disposed between the first and second top metal layers. Other circuit connections may also be disposed on the first and second top metal layers; however, the embodiments in this application do not impose specific limitations on either.

[0056] The first chip unit includes a first active layer disposed on the side of the first top metal layer away from the second chip unit, and a first device disposed within the first active layer. The second chip unit includes a second active layer disposed on the side of the second top metal layer away from the first chip unit, and a second device disposed within the second active layer. A first circuit includes the first device, and the first device in the first circuit is electrically connected to a first conductive part. A second circuit includes a second device, and the second device in the second circuit is electrically connected to a second conductive part. A single first chip unit achieves circuit integration through circuit connection lines on the first top metal layer and the first device on the first active layer. A single second chip unit achieves circuit integration through circuit connection lines on the second top metal layer and the second device on the second active layer. There can be multiple first conductive parts, multiple first devices, multiple second conductive parts, and multiple second devices, depending on the design structure of the first and second circuits. This application does not impose specific limitations on these aspects. The first and second chip units may also include other film layers, which are also not specifically limited in this application.

[0057] In some implementations, the shape of the basic bonding unit and the shape of the redundant bonding unit may be the same. For example, they may both be cylindrical, square, or trapezoidal columns. This application does not impose any specific limitations on these embodiments.

[0058] In some embodiments, the dimensions of the basic bonding unit and the redundant bonding unit are the same. Dimensions may include length, width, height, radius of a circle, major and minor axes of an ellipse, and cross-sectional area, etc., and are not specifically limited in the embodiments of this application. Setting the shape or size of the basic bonding unit and the redundant bonding unit to be the same, or using the same material to fabricate the basic bonding unit and the redundant bonding unit, facilitates the simultaneous fabrication of the basic bonding unit and the redundant bonding unit without increasing the fabrication process and without increasing production costs.

[0059] A second aspect of this application provides a method for fabricating a three-dimensional chip. Figure 3 This is a schematic flowchart illustrating a method for fabricating a three-dimensional chip, as provided in an embodiment of this application. Figure 3 As shown, the method for fabricating a three-dimensional chip provided in this application embodiment is used to fabricate a three-dimensional chip as described in the first aspect. The method for fabricating a three-dimensional chip provided in this application embodiment includes:

[0060] S100: A first circuit, a basic bonding unit, and a redundant bonding unit are disposed on the first chip unit, wherein both the basic bonding unit and the redundant bonding unit are electrically connected to the first circuit. The basic bonding unit and the redundant bonding unit can be fabricated in the same process, depending on the fabrication method and materials of the basic bonding unit and the redundant bonding unit. From the perspective of saving process flow, the basic bonding unit and the redundant bonding unit can be fabricated simultaneously in the same process flow.

[0061] S200: A second circuit is set on the second chip unit.

[0062] S300: The first chip unit and the second chip unit are bonded together through a basic bonding unit and a redundant bonding unit to electrically connect the first circuit and the second circuit through the basic bonding unit. The basic bonding unit is associated with at least one redundant bonding unit, and the redundant bonding unit and the corresponding basic bonding unit are connected in parallel between the same first circuit and the same second circuit.

[0063] The method for fabricating a three-dimensional chip provided in this application embodiment, by setting a basic bonding unit and associated redundant bonding units in parallel between the same first and second circuits, can reduce the connection resistance between the connected first and second circuits and reduce the connection voltage drop, thereby reducing the connection energy consumption of the connected first and second circuits and enhancing the electrical connection stability of the connected first and second circuits. This makes the signal transmission between the connected first and second circuits more stable, reduces the connection resistance between the connected first and second circuits, and also facilitates signal transmission with varying resistance, thereby improving the performance of the three-dimensional chip.

[0064] In some embodiments, when the first circuit includes a first conductive portion and the second circuit includes a second conductive portion, step S100 may include:

[0065] A first conductive part is disposed on the first chip unit;

[0066] A basic bonding unit and a redundant bonding unit are provided in the region where the first conductive part is located, so that both the basic bonding unit and the redundant bonding unit are electrically connected to the first conductive part;

[0067] Step S200 may include:

[0068] A second conductive part is provided on the second chip unit, wherein the orthographic projection of the second conductive part on the first chip unit is the first projection, and the first projection covers the area where the basic bonding unit and the redundant bonding unit are located.

[0069] Step S300 may include:

[0070] The first chip unit and the second chip unit are bonded together by a basic bonding unit and a redundant bonding unit to electrically connect the first circuit and the second circuit through the basic bonding unit. The overlapping area between the region of the first conductive part that is electrically connected to the second conductive part and the first projection is the bonding region. The basic bonding unit and the redundant bonding unit that electrically connect the same first conductive part and the same second conductive part are both disposed in the bonding region.

[0071] In some embodiments, providing a second conductive portion on the second chip unit may include:

[0072] A second conductive portion is disposed on the second chip unit, wherein the area of ​​the first projection is larger than the area of ​​the region where the first conductive portion is electrically connected to the second conductive portion.

[0073] The method for fabricating a three-dimensional chip provided in this application embodiment, combined with Figure 2 As shown, by appropriately increasing the area of ​​the second conductive part, i.e., increasing the area of ​​the orthographic projection (first projection 103) of the second conductive part on the first chip unit 100, while meeting the basic electrical connection requirements, the area of ​​the bonding region 104 can be increased, i.e., the area of ​​the redundant region 102 can be increased, thus enabling the setting of a larger number of redundant bonding units 400. By setting as many redundant bonding units 400 as possible, while ensuring that the basic bonding unit 300 meets the basic electrical connection requirements between the first circuit and the second circuit, the connection resistance between the connected first circuit and the second circuit can be reduced, the connection voltage drop can be reduced, the connection energy consumption of the connected first circuit and the second circuit can be reduced, the electrical connection stability of the connected first circuit and the second circuit can be enhanced, making the signal transmission between the connected first circuit and the second circuit more stable, reducing the connection resistance between the connected first circuit and the second circuit, and also facilitating the signal transmission of some resistors, thereby improving the performance of the three-dimensional chip.

[0074] A third aspect of this application provides an electronic device, the electronic device including the three-dimensional chip as described in the first aspect. Figure 4 This is a schematic structural block diagram of an electronic device provided in an embodiment of this application. Figure 4 As shown, the electronic device provided in this application embodiment includes a three-dimensional chip 1000. The electronic device may also include other devices or circuits, etc., and this application embodiment does not make specific limitations.

[0075] For example, a three-dimensional chip can be disposed in a small or large electronic device as a storage device or microprocessor, etc. The electronic device can be a computer, audio and video player, game device or digital device, etc., and the embodiments of this application do not specifically limit it.

[0076] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0077] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A three-dimensional chip, characterized in that, include: A first chip unit, wherein a first circuit is provided on the first chip unit; The second chip unit has a second circuit on it; A basic bonding unit, wherein the first circuit and the second circuit are electrically connected through the basic bonding unit, the basic bonding unit is associated with at least one redundant bonding unit, and the redundant bonding unit and the corresponding basic bonding unit are connected in parallel between the same first circuit and the same second circuit; The first circuit includes a first conductive part, and the second circuit includes a second conductive part. The first conductive part and the second conductive part are electrically connected through the basic bonding unit. The orthographic projection of the second conductive part on the first chip unit is the first projection. The overlapping area between the region where the first conductive part is electrically connected to the second conductive part and the first projection is the bonding region. The basic bonding unit and the redundant bonding unit that are electrically connected to the same first conductive part and the same second conductive part are both disposed in the bonding region. The area of ​​the first projection is larger than the area of ​​the region where the first conductive part is electrically connected to the second conductive part.

2. The three-dimensional chip according to claim 1, characterized in that, The first chip unit includes a first top metal layer, and the first conductive portion is disposed within the first top metal layer; The second chip unit includes a second top metal layer, and the second conductive portion is disposed within the second top metal layer; The basic bonding unit and the redundant bonding unit are disposed between the first top metal layer and the second top metal layer.

3. The three-dimensional chip according to claim 2, characterized in that, The first chip unit includes a first active layer, which is disposed on the side of the first top metal layer away from the second chip unit, and a first device is disposed within the first active layer; The second chip unit includes a second active layer, which is disposed on the side of the second top metal layer away from the first chip unit, and a second device is disposed within the second active layer; The first circuit includes the first device, and the first device and the first conductive part in the first circuit are electrically connected; The second circuit includes the second device, and the second device and the second conductive part in the second circuit are electrically connected.

4. The three-dimensional chip according to claim 1, characterized in that, The number of redundant bonding units connected in parallel with the basic bonding unit between the same first circuit and the same second circuit is at least two.

5. The three-dimensional chip according to claim 4, characterized in that, The redundant bonding units, which are connected in parallel with the basic bonding unit between the same first circuit and the same second circuit, are arranged in an array.

6. A method for fabricating a three-dimensional chip, characterized in that, The method for preparing a three-dimensional chip as described in any one of claims 1-5 comprises: A first circuit, a basic bonding unit, and a redundant bonding unit are disposed on the first chip unit, wherein the basic bonding unit and the redundant bonding unit are both electrically connected to the first circuit; A second circuit is set on the second chip unit; The first chip unit and the second chip unit are bonded together through the basic bonding unit and the redundant bonding unit to electrically connect the first circuit and the second circuit through the basic bonding unit. The basic bonding unit is associated with at least one redundant bonding unit, and the redundant bonding unit is connected in parallel with the corresponding basic bonding unit between the same first circuit and the same second circuit.

7. The method for fabricating a three-dimensional chip according to claim 6, characterized in that, When the first circuit includes a first conductive portion and the second circuit includes a second conductive portion, the step of setting the first circuit, the basic bonding unit, and the redundant bonding unit on the first chip unit includes: A first conductive portion is disposed on the first chip unit; The basic bonding unit and the redundant bonding unit are disposed in the area where the first conductive part is located, so that both the basic bonding unit and the redundant bonding unit are electrically connected to the first conductive part; The provision of a second circuit on the second chip unit includes: A second conductive portion is disposed on the second chip unit, wherein the orthographic projection of the second conductive portion on the first chip unit is a first projection, and the first projection covers the area where the basic bonding unit and the redundant bonding unit are located; The step of bonding the first chip unit and the second chip unit together through the basic bonding unit and the redundant bonding unit to electrically connect the first circuit and the second circuit through the basic bonding unit includes: The first chip unit and the second chip unit are bonded together through the basic bonding unit and the redundant bonding unit to electrically connect the first circuit and the second circuit through the basic bonding unit. The overlapping area between the region of the first conductive part electrically connected to the second conductive part and the first projection is the bonding region. The basic bonding unit and the redundant bonding unit electrically connecting the same first conductive part and the same second conductive part are both disposed in the bonding region.

8. The method for fabricating a three-dimensional chip according to claim 7, characterized in that, The provision of a second conductive portion on the second chip unit includes: The second conductive portion is disposed on the second chip unit, wherein the area of ​​the first projection is larger than the area of ​​the region where the first conductive portion is electrically connected to the second conductive portion.

9. An electronic device, characterized in that, The electronic device includes a three-dimensional chip as described in any one of claims 1-5.

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