Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a display area, the display area comprises a first arrangement area and a second arrangement area arranged along a row direction, a gate drive circuit located in the first arrangement area, a substrate located in the second arrangement area, a light emitting element located on one side of the substrate, and a pixel circuit connected to the light emitting element in correspondence. A normal projection of the light emitting element on the substrate and a normal projection of the pixel circuit on the substrate at least partially do not overlap. Embodiments of the present application compress the size of the pixel circuit, and adjust the position of the light emitting element along the row direction, so that the normal projection of the compressed pixel circuit on the substrate and the normal projection of the light emitting element on the substrate at least partially do not overlap again, thereby leaving enough space for the gate drive circuit at the edge of the display area, and the display panel can be frameless.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel and a display device. Background Technology

[0002] With the development of display technology, gate driver on array (GOA) circuits are increasingly widely used in the field of display technology. A gate driver circuit generally includes multiple cascaded shift registers, which can be used to drive the row-by-row scanning of multiple rows of pixel units in the display panel.

[0003] The inventors of this application have discovered that in related technologies, it is usually necessary to add a non-display area (i.e., add a left bezel and / or a right bezel) to the left and / or right side of the display area of ​​the display panel to set up the gate driving circuit, which results in a wider bezel width of the display panel, which is not conducive to realizing a narrow bezel or bezel-less design of the display panel. Summary of the Invention

[0004] This application provides a display panel and a display device that enable a borderless display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, the display panel including a display area, the display area including a first arrangement area and a second arrangement area arranged along a row direction, a gate driving circuit located in the first arrangement area; a substrate located in the second arrangement area, and a light-emitting element located on one side of the substrate and a pixel circuit correspondingly connected to the light-emitting element, wherein the orthographic projection of the light-emitting element on the substrate and the orthographic projection of the pixel circuit on the substrate do not overlap at least partially.

[0006] According to an embodiment of the first aspect of this application, the distance between the orthographic projection of the first column pixel circuit adjacent to the first row in the second row and the orthographic projection of the gate driving circuit on the substrate in the row direction is a first distance, and the distance between the orthographic projection of the first column light-emitting element adjacent to the first row in the second row and the orthographic projection of the gate driving circuit on the substrate in the row direction is a second distance, and the second distance is greater than or equal to the first distance.

[0007] In this way, by compressing the size of the pixel circuit and adjusting the position of the light-emitting element along the row direction, the light-emitting element is further away from the first arrangement area (the edge of the display area) compared to the compressed pixel circuit. This avoids the light-emitting element affecting the arrangement of the gate driving circuit, thereby leaving enough space on the left and / or right edges of the display area to set up the gate driving circuit, thus achieving a borderless display panel.

[0008] According to any of the foregoing embodiments of the first aspect of this application, the display panel includes a plurality of pixel units, each pixel unit including sub-pixels of a plurality of colors, the j-th color sub-pixel including a light-emitting element of the j-th color and a pixel circuit correspondingly connected to the light-emitting element of the j-th color, the j-th color being any color among the plurality of colors, and j being a positive integer; for any i-th pixel unit among the plurality of pixel units, the plurality of pixel circuits in the i-th pixel unit are arranged sequentially along the row direction, the straight line containing the left boundary of the leftmost pixel circuit in the i-th pixel unit is the first boundary line, the straight line containing the right boundary of the rightmost pixel circuit in the i-th pixel unit is the second boundary line, and the plurality of light-emitting elements in the i-th pixel unit are located between the first boundary line and the second boundary line.

[0009] In this way, by adjusting the position of multiple light-emitting elements in each pixel unit to between the left edge of the leftmost pixel circuit and the right edge of the rightmost pixel circuit in each pixel unit, sufficient space can be left on the left and / or right edges of the display area to set up the gate driving circuit, thus achieving a borderless display panel.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the left boundary of the leftmost light-emitting element in the i-th pixel unit is located on the first boundary line, and / or, the right boundary of the rightmost light-emitting element in the i-th pixel unit is located on the second boundary line.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the left boundary of the leftmost light-emitting element in the i-th pixel unit and the right boundary of the rightmost light-emitting element in the i-th pixel unit are both located between the first boundary line and the second boundary line.

[0012] According to any of the foregoing embodiments of the first aspect of this application, each pixel unit includes three color sub-pixels, the straight line where the left boundary of the pixel circuit at the middle position of the three pixel circuits in the i-th pixel unit is the third boundary line, and the straight line where the right boundary is the fourth boundary line; at least the light-emitting element at the middle position of the three light-emitting elements in the i-th pixel unit is located between the third boundary line and the fourth boundary line.

[0013] In this way, by adjusting the position of multiple light-emitting elements in each pixel unit to move closer to the pixel circuit in the middle of each pixel unit, enough space can be left on the left and / or right edges of the display area to set up the gate driving circuit, thus achieving a borderless display panel.

[0014] According to any of the foregoing embodiments of the first aspect of this application, the center line of the orthographic projection of the pixel circuit at the middle position in the i-th pixel unit onto the substrate is on the same straight line as the center line of the orthographic projection of the light-emitting element at the middle position in the i-th pixel unit onto the substrate, and the light-emitting elements on the left and right sides of the i-th pixel unit are symmetrical along the center line.

[0015] In this way, since the multiple light-emitting elements in each pixel unit are centrally and symmetrically arranged, it is possible to ensure that sufficient space is left on the left and / or right edges of the display area to accommodate the gate driving circuit while ensuring the uniformity of the display.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the spacing between the orthographic projections of any two adjacent pixel circuits in the i-th pixel unit onto the substrate is 0.

[0017] In this way, by adjusting the spacing between any two adjacent pixel circuits in each pixel unit to 0, the spacing between any two adjacent pixel circuits becomes closer, which reduces the space occupied by the pixel circuits in the row direction. This allows more space to be left on the left and / or right edges of the display area to set up the gate drive circuit, thus achieving a borderless display panel.

[0018] According to any of the foregoing embodiments of the first aspect of this application, the second arrangement area includes N rows of light-emitting elements and N rows of pixel circuits. The first row of pixel circuits is located on the side of the first row of light-emitting elements close to the second row of light-emitting elements, and the j-th row of pixel circuits is located on the side of the j-th row of light-emitting elements close to the (j-1)-th row of light-emitting elements, where 2≤j≤N, and j and N are both integers.

[0019] In this way, by adjusting the position of the first row of pixel circuits to the side of the first row of light-emitting elements closer to the second row of light-emitting elements, that is, below the first row of light-emitting elements, it can be ensured that the first row of pixel circuits will not occupy the space in the row direction, so that enough space can be left on the left edge and / or right edge of the display area to set up the gate driving circuit, thus realizing the borderless display panel; on the other hand, it can avoid the overlap between the orthographic projection of the first row of pixel circuits on the substrate of the display panel and the orthographic projection of the first row of light-emitting elements on the substrate of the display panel, thereby preventing damage to the traces or devices in the first row of pixel circuits when bonding the first row of light-emitting elements, and preventing short circuit problems.

[0020] According to any of the foregoing embodiments of the first aspect of this application, the second arrangement area includes N rows of light-emitting elements and N rows of pixel circuits. The Nth row of pixel circuits is located on the side of the Nth row of light-emitting elements close to the (N-1)th row of light-emitting elements, and the qth row of pixel circuits is located on the side of the qth row of light-emitting elements close to the (q+1)th row of light-emitting elements, where 1≤q≤N-1, and q and N are both integers.

[0021] In this way, by adjusting the position of the Nth row pixel circuit to the side of the Nth row light-emitting element that is close to the (N-1)th row light-emitting element, that is, above the Nth row light-emitting element, it can be ensured that the Nth row pixel circuit does not occupy the space in the row direction, so that enough space can be left on the left edge and / or right edge of the display area to set up the gate driving circuit, thus realizing the borderless display panel; on the other hand, it can avoid the overlap between the orthographic projection of the Nth row pixel circuit on the substrate of the display panel and the orthographic projection of the Nth row light-emitting element on the substrate of the display panel, thereby preventing damage to the traces or devices in the Nth row pixel circuit when bonding the Nth row light-emitting element and preventing short circuit problems.

[0022] According to any of the foregoing embodiments of the first aspect of this application, the second arrangement area includes N rows of light-emitting elements and N rows of pixel circuits, with each row of pixel circuits located between two adjacent rows of light-emitting elements.

[0023] According to any of the foregoing embodiments of the first aspect of this application, the pixel circuit of the m-th row is located on the side of the light-emitting element of the m-th row that is close to the light-emitting element of the (m+1)-th row, and the pixel circuit of the n-th row is located on the side of the light-emitting element of the n-th row that is close to the light-emitting element of the (n-1)-th row, where m is an odd number and n is an even number.

[0024] In this way, by adjusting the position of each row of pixel circuits to be between adjacent rows of light-emitting elements, it can be ensured that each row of pixel circuits does not occupy too much space in the row direction, so that enough space can be left on the left and / or right edges of the display area to set up the gate driving circuit, thus realizing the borderless display panel; on the other hand, it can avoid the overlap between the orthographic projection of each row of pixel circuits on the substrate of the display panel and the orthographic projection of each row of light-emitting elements on the substrate of the display panel, thereby preventing damage to the traces or devices in each row of pixel circuits when bonding each row of light-emitting elements, and preventing short circuit problems.

[0025] According to any of the foregoing embodiments of the first aspect of this application, the first arrangement area is located on one side of the second arrangement area; the display panel includes N rows of pixel circuits and N rows of scan lines, with each row of scan lines electrically connected to a row of pixel circuits, and N being a positive integer; the gate driving circuit includes N first shift registers, with the output terminals of the N first shift registers connected one-to-one with the N rows of scan lines.

[0026] In this way, by setting the gate drive circuit on one side edge of the display area, it is possible to achieve single-sided driving of the display panel while making the display panel borderless.

[0027] According to any of the foregoing embodiments of the first aspect of this application, the first arrangement area is located on both sides of the second arrangement area, wherein a first gate driving circuit is provided on one side of the first arrangement area, and a second gate driving circuit is provided on the other side of the first arrangement area; the display panel includes N rows of pixel circuits and N rows of scan lines, wherein one row of scan lines is electrically connected to one row of pixel circuits, and N is a positive integer; the first gate driving circuit includes N first shift registers, and the output terminals of the N first shift registers are connected to the N rows of scan lines in a one-to-one correspondence; the second gate driving circuit includes N second shift registers, and the output terminals of the N second shift registers are connected to the N rows of scan lines in a one-to-one correspondence.

[0028] In this way, by setting gate drive circuits on both the left and right edges of the display area, it is possible to achieve dual-sided driving of the display panel while making the display panel borderless.

[0029] According to any of the foregoing embodiments of the first aspect of this application, the first arrangement area is located on both sides of the second arrangement area, wherein a first gate driving circuit is provided on one side of the first arrangement area, and a second gate driving circuit is provided on the other side of the first arrangement area; the display panel includes N rows of pixel circuits and N rows of scan lines, wherein one row of scan lines is electrically connected to one row of pixel circuits, and N is a positive integer; the first gate driving circuit includes Q first shift registers, the output terminals of the Q first shift registers are connected one-to-one with the scan lines of the odd-numbered rows of the N rows of scan lines, and Q < N and is a positive integer; the second gate driving circuit includes NQ second shift registers, the output terminals of the NQ second shift registers are connected one-to-one with the scan lines of the even-numbered rows of the N rows of scan lines.

[0030] In this way, by setting gate drive circuits on both the left and right edges of the display area, it is possible to achieve cross-drive of the display panel while making the display panel borderless.

[0031] Secondly, embodiments of this application provide a display device, which includes a display panel as provided in any embodiment of the first aspect.

[0032] The display panel and display device of this application embodiment include a display area, which includes a first arrangement area and a second arrangement area arranged along a row direction. The first arrangement area is arranged with gate driving circuits. The second arrangement area includes a substrate, a light-emitting element located on one side of the substrate, and a pixel circuit correspondingly connected to the light-emitting element. The orthographic projection of the light-emitting element on the substrate and the orthographic projection of the pixel circuit on the substrate do not overlap at least partially. Compared with related technologies, the embodiments of this application compress the size of the pixel circuit and adjust the position of the light-emitting element along the row direction, so that the orthographic projection of the compressed pixel circuit on the substrate and the orthographic projection of the light-emitting element on the substrate no longer overlap at least partially. This leaves sufficient space on the left edge and / or right edge of the display area to accommodate the gate driving circuits, thereby achieving a borderless display panel. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a display panel structure in related technologies;

[0035] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0036] Figure 3 A cross-sectional schematic diagram of a partial area of ​​a display panel provided in an embodiment of this application;

[0037] Figure 4 Another structural schematic diagram of the display panel provided in the embodiments of this application;

[0038] Figure 5 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0039] Figure 6 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0040] Figure 7 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0041] Figure 8 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0042] Figure 9 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0043] Figure 10A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0044] Figure 11 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0045] Figure 12 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0046] Figure 13 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0047] Figure 14 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0048] Figure 15 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0049] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0050] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0051] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0052] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0053] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the prior art:

[0054] As mentioned above, the inventors of this application have discovered that the related technologies have a problem where the bezel width of the display panel is relatively wide, which is not conducive to realizing a narrow bezel or bezel-less design of the display panel.

[0055] Specifically, such as Figure 1 As shown, in related technologies, the display panel 10' includes a display area AA' and a non-display area NA' surrounding the display area AA'. The display area AA' is provided with a light-emitting element 101' and a pixel circuit 102', which... Figure 1 As can be seen, the pixel circuit 102' in the related technology is relatively large, and the orthographic projection of the pixel circuit 102' on the substrate of the display panel 10' completely surrounds the orthographic projection of the light-emitting element 101' on the substrate of the display panel 10'. This determines that there is not enough space in the display area AA' to place the gate driving circuit 103'. Therefore, the gate driving circuit 103' is usually located in the non-display area NA' located to the left and / or right of the display area AA', resulting in a wider bezel width of the display panel 10', which is not conducive to realizing a narrow bezel or bezel-less design of the display panel.

[0056] In view of the inventors’ above-mentioned research findings, the present application provides a display panel and a display device that can solve the above-mentioned technical problems existing in the related art.

[0057] The technical concept of this application embodiment is: by compressing the size of the pixel circuit and adjusting the position of the light-emitting element along the row direction, the orthographic projection of the compressed pixel circuit on the substrate and the orthographic projection of the light-emitting element on the substrate no longer overlap at least partially, thereby leaving enough space on the left edge and / or right edge of the display area to set the gate driving circuit, thus realizing the borderless display panel.

[0058] The display panel provided in the embodiments of this application will be described below.

[0059] like Figure 2 As shown, the display panel 30 provided in this embodiment includes a display area AA, and the display area AA includes areas along the row direction ( Figure 2 The first and second arrangement areas AA1 and AA2 are arranged in the X direction (as shown). The first arrangement area AA1 is equipped with a gate driving circuit 310. The gate driving circuit 310 may include multiple cascaded shift registers, which can be arranged along the column direction (as shown). Figure 2 The shift registers (as shown in the Y direction) are arranged sequentially, and each shift register can be electrically connected to the grid lines of one or more rows of sub-pixels in the display panel 30 to provide scan drive signals.

[0060] Combination Figure 2 and Figure 3 As shown, the second arrangement area AA2 may include a substrate 300 and a light-emitting element 320 and a pixel circuit 330 located on one side of the substrate 300. In the embodiments of this application, the light-emitting element 320 may include, for example, a light-emitting diode (LED), a micro LED, and a sub-millimeter light-emitting diode (Mini LED). Correspondingly, the display panel 30 may include an LED display panel, a Micro LED display panel, and a Mini LED display panel. It is worth noting that, by comparison... Figure 1 and Figure 3 As can be seen, the size of the pixel circuit 330 in this embodiment is smaller than that of pixel circuits in related technologies, and the orthographic projection of the light-emitting element 320 on the substrate 300 and the orthographic projection of the pixel circuit 330 on the substrate do not overlap at least partially. "At least partially overlapping" can be understood as only partially overlapping or not overlapping at all. In some specific examples, for instance, the orthographic projection of the light-emitting element 320 on the substrate 300 and the orthographic projection of the pixel circuit 330 on the substrate may not overlap at all. This prevents damage to the traces or devices in the pixel circuit during bonding or attaching of the light-emitting element, thus preventing short circuits.

[0061] In this way, by compressing the size of the pixel circuit 330, the orthographic projection of the compressed pixel circuit 330 on the substrate and the orthographic projection of the light-emitting element 320 on the substrate no longer overlap at least partially, thereby leaving enough space on the left and / or right edges of the display area AA to set the gate driving circuit 310, thus achieving a borderless display panel.

[0062] During the research and development process, the inventors of this application also considered and studied a scheme for a horizontally positioned gate drive circuit. However, through their research, the inventors of this application discovered that, as Figure 4As shown, if the gate driving circuit 103' is placed horizontally between the light-emitting elements 101' in adjacent rows, the orthographic projection of the gate driving circuit 103' on the substrate of the display panel 10' and the orthographic projection of the pixel circuit 102' on the substrate of the display panel 10' will completely overlap in reality. This will significantly increase the risk of electrostatic discharge in the circuits of the display panel 10'. Furthermore, since the overlapping area of ​​the gate driving circuit 103' and the pixel circuit 102' forms a parasitic capacitance, the resulting parasitic capacitance will significantly increase the load on the pixel circuit traces, affecting the display effect of the display panel 10'.

[0063] Therefore, embodiments of this application propose a scheme in which the gate driving circuit is vertically arranged at the left edge and / or right edge of the display area. To ensure sufficient space at the left edge and / or right edge of the display area for the gate driving circuit, in some embodiments, embodiments of this application also adjust the position / arrangement of the light-emitting elements. Specifically, as... Figure 5 As shown in the embodiments of this application, both the light-emitting element 320 and the pixel circuit 330 can be arranged in an array. It is worth noting that the first spacing L1 in the row direction between the orthographic projection of the first column of pixel circuits 330 adjacent to the first arrangement area AA1 in the second arrangement area AA2 onto the substrate 300 and the orthographic projection of the gate driving circuit 310 onto the substrate 300 is greater than 0. Furthermore, by comparison... Figure 1 and Figure 4 As can be seen, in this embodiment, the position of the light-emitting element 320 is shifted towards the center of the display panel 30 along the row direction. After the shift, the second distance L2 in the row direction between the orthographic projection of the first column of light-emitting elements 320 adjacent to the first row area AA1 in the second row area AA2 and the orthographic projection of the gate driving circuit 310 on the substrate 300 is greater than or equal to the first distance L1. That is, compared with the compressed pixel circuit 330, the position of the light-emitting element 320 is further away from the first row area AA1.

[0064] In this way, based on the size of the compressed pixel circuit 330, the position of the light-emitting element 320 is adjusted along the row direction, so that the light-emitting element 320 is further away from the first arrangement area (the edge of the display area) compared to the compressed pixel circuit. This avoids the influence of the light-emitting element on the arrangement of the gate driving circuit 310, thereby leaving enough space on the left edge and / or right edge of the display area AA to set the gate driving circuit 310, and realizing the borderless display panel.

[0065] Furthermore, compared to a scheme where the gate driving circuit is horizontally positioned, since the gate driving circuit 310 is vertically positioned at the left edge and / or right edge of the display area AA, the gate driving circuit 310 will not overlap with the pixel circuit 330, for example, positioned between adjacent row light-emitting elements 320. Therefore, the risk of electrostatic discharge in the lines of the display panel can be reduced, the load on the traces of the pixel circuit 330 can be reduced, and the display effect of the display panel can be improved.

[0066] like Figure 6 As shown, according to some embodiments of this application, optionally, the display panel 30 may include a plurality of pixel units PX. Each pixel unit PX may include sub-pixels PX1 to PXn of multiple colors, where n is a positive integer. For any color among the multiple colors (the j-th color, where j is a positive integer), the sub-pixels PX1 of the j-th color are... i It may include a light-emitting element 320 of the j-th color and a pixel circuit 330 connected to the light-emitting element 320 of the j-th color. i It can be any one of PX1 to PXn. That is, each color sub-pixel PX i Each pixel can be driven independently by a separate pixel circuit 330. For example, for a red sub-pixel, the red sub-pixel may include a red-emitting light-emitting element 320 and a pixel circuit 330 connected to the red-emitting light-emitting element 320. For a green sub-pixel, the green sub-pixel may include a green-emitting light-emitting element 320 and a pixel circuit 330 connected to the green-emitting light-emitting element 320. For a blue sub-pixel, the blue sub-pixel may include a blue-emitting light-emitting element 320 and a pixel circuit 330 connected to the blue-emitting light-emitting element 320.

[0067] It is worth noting that, Figure 6 In the illustrated embodiment, for any i-th pixel unit PX among a plurality of pixel units PX, the light-emitting element 320 and pixel circuit 330 in the i-th pixel unit PX can be along the column direction ( Figure 6 The pixel circuits 330 in the i-th pixel unit PX are arranged along the row direction (as shown in the Y direction). Figure 6 The elements (in the X direction shown) are arranged sequentially, where i is a positive integer. The straight line containing the left boundary of the leftmost pixel circuit 330 in the i-th pixel unit PX is the first boundary line B1, and the straight line containing the right boundary of the rightmost pixel circuit 330 in the i-th pixel unit PX is the second boundary line B2. All the light-emitting elements 320 in the i-th pixel unit PX can be located between the first boundary line B1 and the second boundary line B2.

[0068] In this way, based on the size of the compressed pixel circuit 330, by adjusting the position of the multiple light-emitting elements 320 in each pixel unit PX to between the left edge of the leftmost pixel circuit and the right edge of the rightmost pixel circuit in each pixel unit PX, sufficient space can be left on the left edge and / or right edge of the display area to set up the gate driving circuit 310, thereby achieving a borderless display panel.

[0069] See also Figure 6 In some specific embodiments, optionally, the left boundary of the leftmost light-emitting element 320 in the i-th pixel unit PX and the right boundary of the rightmost light-emitting element 320 in the i-th pixel unit PX can both be located between the first boundary line B1 and the second boundary line B2.

[0070] like Figure 7 As shown, in some other specific embodiments, optionally, the left boundary of the leftmost light-emitting element 320 in the i-th pixel unit PX may be located on the first boundary line B1, and / or, the right boundary of the rightmost light-emitting element 320 in the i-th pixel unit PX may be located on the second boundary line B2.

[0071] In this way, based on the size of the compressed pixel circuit 330, by adjusting the position of the multiple light-emitting elements 320 in each pixel unit PX to between the left boundary of the leftmost pixel circuit and the right boundary of the rightmost pixel circuit in each pixel unit PX, sufficient space can be left on the left edge and / or right edge of the display area to set up the gate driving circuit 310, thereby achieving a borderless display panel.

[0072] like Figure 8 As shown, in some specific embodiments, each pixel unit PX may include, for example, three color sub-pixels PX1 to PX3, namely, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. That is, each pixel unit PX may include a red-emitting light-emitting element, a green-emitting light-emitting element, a blue-emitting light-emitting element, and three pixel circuits 330 connected to the three color light-emitting elements 320. It is worth noting that in... Figure 8In the illustrated embodiment, the straight line containing the left boundary of the middle pixel circuit 330 among the three pixel circuits 330 of the i-th pixel unit PX is the third boundary line B3, and the straight line containing the right boundary of the middle pixel circuit 330 is the fourth boundary line B4. At least the middle light-emitting element 320 among the three light-emitting elements 320 of the i-th pixel unit PX is located between the third boundary line B3 and the fourth boundary line B4. In some specific examples, for instance, the spacing L3 between the orthographic projections of any two adjacent light-emitting elements 320 in the i-th pixel unit PX onto the substrate of the display panel 30 can be reduced to less than half of the width w of a pixel circuit PX along the row direction, i.e., L3 ≤ w / 2.

[0073] It should be noted that at least the middle light-emitting element 320 of the three light-emitting elements 320 in the i-th pixel unit PX is located between the third boundary line B3 and the fourth boundary line B4. This can include the following scenarios: for example, all three colors of light-emitting elements 320 in each pixel unit PX may be located between the third boundary line B3 and the fourth boundary line B4; or, any one of the left and right light-emitting elements 320 in each pixel unit PX and the middle light-emitting element 320 may be located between the third boundary line B3 and the fourth boundary line B4; or, only the middle light-emitting element 320 in each pixel unit PX may be located between the third boundary line B3 and the fourth boundary line B4. Alternatively, a portion of the left and / or right light-emitting elements 320 in each pixel unit PX and the middle light-emitting element 320 may be located between the third boundary line B3 and the fourth boundary line B4.

[0074] In this way, by adjusting the positions of multiple light-emitting elements 320 in each pixel unit PX to move closer to the pixel circuit 330 in the middle position of each pixel unit PX, and reducing the spacing between any two adjacent light-emitting elements 320, sufficient space can be left on the left edge and / or right edge of the display area to set up the gate driving circuit, thereby achieving a borderless display panel.

[0075] See also Figure 8 In some specific examples, the center line z1 of the orthographic projection of the pixel circuit 330 at the middle position in the i-th pixel unit PX onto the substrate of the display panel is on the same straight line as the center line z2 of the orthographic projection of the light-emitting element 320 at the middle position in the i-th pixel unit PX onto the substrate of the display panel, and the light-emitting element 320 on the left and the light-emitting element 320 on the right in the i-th pixel unit PX are symmetrical along the center line z1 (z2).

[0076] In this way, since the multiple light-emitting elements 320 in each pixel unit PX are centrally and symmetrically arranged, it is possible to ensure that sufficient space is left on the left and / or right edges of the display area to set up the gate driving circuit while ensuring the uniformity of the display.

[0077] like Figure 8 As shown, by adjusting the positions of the three-color light-emitting elements 320 in the pixel unit PX, for example, the three-color light-emitting elements 320 originally distributed in three sub-pixel regions are concentrated into one sub-pixel region. Figure 8 The dashed box in the image allows sufficient space to be provided on the left and / or right edges of the display area for the gate drive circuit.

[0078] See also Figure 8 According to some embodiments of this application, optionally, the spacing between the orthographic projections of any two adjacent pixel circuits 330 in the i-th pixel unit PX onto the substrate of the display panel is 0. That is, in the row direction of the display panel 30, there is no spacing between any two adjacent pixel circuits 330 in each pixel unit PX.

[0079] In this way, by adjusting the spacing between any two adjacent pixel circuits 330 in each pixel unit PX to 0, the two adjacent pixel circuits 330 are made closer together, which reduces the space occupied by the pixel circuits 330 in the row direction. This allows more space to be left on the left and / or right edges of the display area to set up the gate driving circuit, thus achieving a borderless display panel.

[0080] The arrangement of the light-emitting element 320 and the pixel circuit 330 will be described below with reference to some embodiments of this application.

[0081] like Figure 9 As shown, according to some embodiments of this application, optionally, the second arrangement area AA2 may include N rows of light-emitting elements 320 and N rows of pixel circuits 330. The first row of pixel circuits 330 may be located on the side of the first row of light-emitting elements 320 closest to the second row of light-emitting elements 320. Except for the first row of pixel circuits 330, for each row of pixel circuits 330 in the second to Nth rows (i.e., the j-th row of pixel circuits 330), the j-th row of pixel circuits 330 may be located on the side of the j-th row of light-emitting elements 320 closest to the (j-1)-th row of light-emitting elements 320, where 2 ≤ j ≤ N, and j and N are both integers. In other words, in Figure 9 In the embodiment shown, the first row pixel circuit 330 is located below the first row light-emitting element 320, and the other row pixel circuits 330 are located above the corresponding row light-emitting element 320.

[0082] In this way, by adjusting the position of the first row of pixel circuits to the side of the first row of light-emitting elements closer to the second row of light-emitting elements, that is, below the first row of light-emitting elements, it can be ensured that the first row of pixel circuits does not occupy the space in the row direction, thus ensuring that enough space is left on the left and / or right edges of the display area to set up the gate driving circuit, achieving a borderless display panel. On the other hand, since the space above the first row of light-emitting elements is limited, placing the first row of pixel circuits below the first row of light-emitting elements can avoid the orthographic projection of the first row of pixel circuits on the substrate of the display panel overlapping with the orthographic projection of the first row of light-emitting elements on the substrate of the display panel. This prevents damage to the traces or devices in the first row of pixel circuits when bonding or attaching the first row of light-emitting elements, and prevents short circuit problems.

[0083] like Figure 10 As shown, according to some other embodiments of this application, optionally, the second arrangement area AA2 may include N rows of light-emitting elements 320 and N rows of pixel circuits 330. The Nth row of pixel circuits 330 may be located on the side of the Nth row of light-emitting elements 320 closest to the (N-1)th row of light-emitting elements 320, that is, the last row of pixel circuits 330 may be located above the last row of light-emitting elements 320. Except for the Nth row of pixel circuits 330, for each row of pixel circuits 330 from the 1st to the (N-1)th row (i.e., the qth row of pixel circuits 330), the qth row of pixel circuits 330 may be located on the side of the qth row of light-emitting elements 320 closest to the (q+1)th row of light-emitting elements 320, where 1 ≤ q ≤ N-1, and q and N are both integers. In other words, in Figure 10 In the embodiment shown, the last row of pixel circuits 330 is located above the last row of light-emitting elements 320, and the other row of pixel circuits 330 are located below the corresponding row of light-emitting elements 320.

[0084] In this way, by adjusting the position of the Nth row pixel circuit to the side of the Nth row light-emitting element that is close to the (N-1)th row light-emitting element, that is, above the Nth row light-emitting element, it can be ensured that the Nth row pixel circuit does not occupy the space in the row direction, thus ensuring that enough space is left on the left and / or right edges of the display area to set up the gate driving circuit, achieving a borderless display panel. On the other hand, since the space below the Nth row light-emitting element is limited, placing the Nth row pixel circuit above the Nth row light-emitting element can avoid the overlap between the orthographic projection of the Nth row pixel circuit on the substrate of the display panel and the orthographic projection of the Nth row light-emitting element on the substrate of the display panel, thereby preventing damage to the traces or devices in the Nth row pixel circuit when bonding the Nth row light-emitting element and preventing short circuit problems.

[0085] like Figure 11As shown, according to some embodiments of this application, optionally, the second arrangement area AA2 may include N rows of light-emitting elements 320 and N rows of pixel circuits 330, with each row of pixel circuits 330 located between two adjacent rows of light-emitting elements 320. For example, the m-th row of pixel circuits is located on the side of the m-th row of light-emitting elements closest to the (m+1)-th row of light-emitting elements, and the n-th row of pixel circuits is located on the side of the n-th row of light-emitting elements closest to the (n-1)-th row of light-emitting elements, where m is an odd number and n is an even number. For example, the 1st row of pixel circuits is located on the side of the 1st row of light-emitting elements closest to the 2nd row of light-emitting elements, the 2nd row of pixel circuits is located on the side of the 2nd row of light-emitting elements closest to the 1st row of light-emitting elements, the 3rd row of pixel circuits is located on the side of the 3rd row of light-emitting elements closest to the 4th row of light-emitting elements, and the 4th row of pixel circuits is located on the side of the 4th row of light-emitting elements closest to the 3rd row of light-emitting elements.

[0086] In this way, by adjusting the position of each row of pixel circuits to be between adjacent rows of light-emitting elements, it can be ensured that each row of pixel circuits does not occupy too much space in the row direction, so that enough space can be left on the left and / or right edges of the display area to set up the gate driving circuit, thus realizing the borderless display panel; on the other hand, it can avoid the overlap between the orthographic projection of each row of pixel circuits on the substrate of the display panel and the orthographic projection of each row of light-emitting elements on the substrate of the display panel, thereby preventing damage to the traces or devices in each row of pixel circuits when bonding each row of light-emitting elements, and preventing short circuit problems.

[0087] The arrangement of the gate drive circuit 310 will be described below with reference to some embodiments of this application.

[0088] like Figure 12 As shown, according to some embodiments of this application, optionally, the first arrangement area AA1 can be located on one side of the second arrangement area AA2. For example, the first arrangement area AA1 can be located to the left of the second arrangement area AA2, or the first arrangement area AA1 can be located to the right of the second arrangement area AA2. A gate driving circuit 310 can be provided in the first arrangement area AA1. The gate driving circuit 310 can include N first shift registers 310a, which are arranged along the column direction, i.e., vertically, where N is a positive integer. The display panel 30 can include N rows of pixel circuits 330 and N rows of scan lines S (gate lines). A row of scan lines S can be electrically connected to a row of pixel circuits 330, and the output terminals of the N first shift registers 310a can be electrically connected to the N rows of scan lines S one-to-one. The first shift registers 310a can provide scan signals to the pixel circuits 330 through the scan lines S to control the on / off state of the transistors in the pixel circuits 330.

[0089] In this way, by setting the gate driving circuit in the first arrangement area (such as the left edge area or the right edge area) in the display area AA, it is possible to achieve a borderless display panel while realizing single-sided driving of the display panel.

[0090] like Figure 13 As shown, with Figure 12 Unlike the illustrated embodiment, in some other embodiments of this application, optionally, the first arrangement area AA1 can be located on both sides of the second arrangement area AA2, that is, the first arrangement area AA1 can be located simultaneously on the left and right sides of the second arrangement area AA2. One side of the first arrangement area AA1 is provided with a first gate driving circuit 310A, and the other side of the first arrangement area AA1 is provided with a second gate driving circuit 310B. The first gate driving circuit 310A may include N first shift registers 310a, which are arranged along the column direction, i.e., vertically, where N is a positive integer. The second gate driving circuit 310B may include N second shift registers 310b, which are arranged along the column direction, i.e., vertically.

[0091] The display panel 30 may include N rows of pixel circuits 330 and N rows of scan lines S, with each scan line S electrically connected to one row of pixel circuits 330. The outputs of N first shift registers 310a can be electrically connected one-to-one with the N rows of scan lines S, and the outputs of N second shift registers 310b can also be electrically connected one-to-one with the N rows of scan lines S. Figure 13 In the embodiment shown, the first shift register 310a and the second shift register 310b can provide scanning signals to the pixel circuit 330 through the same scan line S to control the turn-on / turn-off of the transistors in the pixel circuit 330, thereby realizing the dual-sided driving of the display panel 30.

[0092] In this way, by setting gate driving circuits in the first arrangement area (such as the left edge area and the right edge area) in the display area AA, it is possible to achieve a borderless display panel while realizing dual-sided driving of the display panel.

[0093] like Figure 14 As shown, with Figure 13 Similar to the illustrated embodiment, according to some other embodiments of this application, optionally, the first arrangement area AA1 can be located on both sides of the second arrangement area AA2, that is, the first arrangement area AA1 can be simultaneously located on the left and right sides of the second arrangement area AA2. One side of the first arrangement area AA1 is provided with a first gate driving circuit 310A, and the other side of the first arrangement area AA1 is provided with a second gate driving circuit 310B. However, similar to... Figure 13The difference in the illustrated embodiment is that the first gate driving circuit 310A may include Q first shift registers 310a, which are arranged vertically along the column direction, i.e., Q < N and are positive integers. The second gate driving circuit 310B may include NQ second shift registers 310b, which are arranged vertically along the column direction. That is, the sum of the number of first shift registers 310a and second shift registers 310b in the display panel 30 can be equal to N.

[0094] exist Figure 14 In the illustrated embodiment, the display panel 30 may include N rows of pixel circuits 330 and N rows of scan lines S, with each scan line S electrically connected to one row of pixel circuits 330. The outputs of Q first shift registers 310a are electrically connected one-to-one with the scan lines S in the odd-numbered rows of the N scan lines S, and the outputs of NQ second shift registers 310b are electrically connected one-to-one with the scan lines S in the even-numbered rows of the N scan lines S. Alternatively, in other examples, the outputs of Q first shift registers 310a may be electrically connected one-to-one with the scan lines S in the even-numbered rows of the N scan lines S, and the outputs of NQ second shift registers 310b may be electrically connected one-to-one with the scan lines S in the odd-numbered rows of the N scan lines S. Figure 11 In the illustrated embodiment, for example, the first shift register 310a provides a scan signal to the odd-numbered row pixel circuit 330 to control the on / off state of the transistors in the odd-numbered row pixel circuit 330; the second shift register 310b provides a scan signal to the even-numbered row pixel circuit 330 to control the on / off state of the transistors in the even-numbered row pixel circuit 330, thereby realizing the cross-driving of the display panel 30.

[0095] In this way, by setting gate drive circuits in the first arrangement area (such as the left edge area and the right edge area) in the display area AA, it is possible to achieve a borderless display panel while realizing cross-drive of the display panel.

[0096] Based on the display panel provided in the above embodiments, this application also provides a display device. For example... Figure 15 As shown, the display device 1000 may include a device body 20 and a display panel 30 as described in the above embodiments, with the display panel 30 covering the device body 20. The device body 20 may contain various components, such as sensors and processing devices, and is not limited thereto. Specifically, the display device 1000 may be a mobile phone, computer, tablet computer, digital camera, television, electronic paper, or other device with display functionality, and is not limited thereto.

[0097] It should be clarified that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. For the display panel embodiments and display device embodiments, relevant parts can be referred to the description sections of the pixel driving circuit embodiments and array substrate embodiments. This application is not limited to the specific structures described above and shown in the figures. Those skilled in the art can make various changes, modifications, and additions after understanding the spirit of this application. Furthermore, for the sake of brevity, detailed descriptions of known technologies are omitted here.

[0098] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. No reference numerals in the claims should be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A display panel, characterized in that, The display panel includes a display area, which comprises a first row area and a second row area arranged along a row direction. The gate driving circuit located in the first arrangement area has multiple cascaded shift registers arranged along the column direction within the same gate driving circuit. In the row direction, there is no pixel circuit on the side of the gate driving circuit away from the second arrangement area. The substrate located in the second arrangement area, the light-emitting element located on one side of the substrate, and the pixel circuit connected to the light-emitting element, wherein the orthographic projection of any light-emitting element on the substrate and the orthographic projection of any pixel circuit on the substrate do not overlap at least partially, and the size of each pixel circuit is equal; The display panel includes multiple pixel units, each pixel unit includes sub-pixels of multiple colors, the j-th color sub-pixel includes the light-emitting element of the j-th color and the pixel circuit corresponding to the light-emitting element of the j-th color, the j-th color is any color among the multiple colors, and j is a positive integer; For any i-th pixel unit among the plurality of pixel units, the plurality of pixel circuits in the i-th pixel unit are arranged sequentially along the row direction, the straight line containing the left boundary of the leftmost pixel circuit in the i-th pixel unit is the first boundary line, the straight line containing the right boundary of the rightmost pixel circuit in the i-th pixel unit is the second boundary line, and the plurality of light-emitting elements in the i-th pixel unit are located between the first boundary line and the second boundary line; the i-th pixel unit includes the first column of pixel units and / or the last column of pixel units; Each pixel unit includes three color sub-pixels. The straight line containing the left boundary of the middle pixel circuit in the i-th pixel unit is the third boundary line, and the straight line containing the right boundary is the fourth boundary line. At least the middle light-emitting element in the i-th pixel unit is located between the third boundary line and the fourth boundary line. The spacing between the orthographic projections of any two adjacent light-emitting elements in the i-th pixel unit onto the substrate is L3. The width of the pixel circuit in the row direction is w, and L3 ≤ w / 2.

2. The display panel according to claim 1, characterized in that, The distance between the orthographic projection of the pixel circuit in the first column adjacent to the first arrangement area on the substrate and the orthographic projection of the gate driving circuit on the substrate in the row direction in the second arrangement area is a first distance. The distance between the orthographic projection of the light-emitting element in the first column adjacent to the first arrangement area on the substrate and the orthographic projection of the gate driving circuit on the substrate in the row direction in the second arrangement area is a second distance. The second distance is greater than or equal to the first distance.

3. The display panel according to claim 1, characterized in that, The left boundary of the leftmost light-emitting element in the i-th pixel unit is located on the first boundary line, and / or the right boundary of the rightmost light-emitting element in the i-th pixel unit is located on the second boundary line.

4. The display panel according to claim 1, characterized in that, The left boundary of the leftmost light-emitting element in the i-th pixel unit and the right boundary of the rightmost light-emitting element in the i-th pixel unit are both located between the first boundary line and the second boundary line.

5. The display panel according to claim 1, characterized in that, The center line of the orthographic projection of the pixel circuit at the middle position in the i-th pixel unit onto the substrate is on the same straight line as the center line of the orthographic projection of the light-emitting element at the middle position in the i-th pixel unit onto the substrate, and the light-emitting elements on the left and right sides of the i-th pixel unit are symmetrical along the center line.

6. The display panel according to claim 1, characterized in that, The spacing between the orthographic projections of any two adjacent pixel circuits in the i-th pixel unit onto the substrate is 0.

7. The display panel according to claim 1, characterized in that, The second arrangement area includes N rows of light-emitting elements and N rows of pixel circuits. The pixel circuits in the first row are located on the side of the first row of light-emitting elements close to the second row of light-emitting elements. The pixel circuits in the j-th row are located on the side of the j-th row of light-emitting elements close to the (j-1)-th row of light-emitting elements. 2≤j≤N, and j and N are both integers.

8. The display panel according to claim 1, characterized in that, The second arrangement area includes N rows of light-emitting elements and N rows of pixel circuits. The pixel circuits in the Nth row are located on the side of the light-emitting elements in the Nth row that are close to the light-emitting elements in the (N-1)th row. The pixel circuits in the qth row are located on the side of the light-emitting elements in the qth row that are close to the light-emitting elements in the (q+1)th row. 1≤q≤N-1, and q and N are both integers.

9. The display panel according to claim 1, characterized in that, The second arrangement area includes N rows of light-emitting elements and N rows of pixel circuits, with each row of pixel circuits located between two adjacent rows of light-emitting elements.

10. The display panel according to claim 9, characterized in that, The pixel circuit in row m is located on the side of the light-emitting element in row m+1 that is close to the light-emitting element in row m+1, and the pixel circuit in row n is located on the side of the light-emitting element in row n-1 that is close to the light-emitting element in row n-1, where m is an odd number and n is an even number.

11. The display panel according to claim 1, characterized in that, The first layout area is located on one side of the second layout area; The display panel includes N rows of pixel circuits and N rows of scan lines, with each row of scan lines electrically connected to a row of pixel circuits, where N is a positive integer. The gate drive circuit includes N first shift registers, and the output terminals of the N first shift registers are connected one-to-one with the N rows of scan lines.

12. The display panel according to claim 1, characterized in that, The first arrangement area is located on both sides of the second arrangement area, with a first gate driving circuit provided on one side of the first arrangement area and a second gate driving circuit provided on the other side of the first arrangement area. The display panel includes N rows of pixel circuits and N rows of scan lines, with each row of scan lines electrically connected to a row of pixel circuits, where N is a positive integer.

13. The display panel according to claim 12, characterized in that, The first gate driving circuit includes N first shift registers, the output terminals of which are connected one-to-one with the N rows of scan lines; the second gate driving circuit includes N second shift registers, the output terminals of which are connected one-to-one with the N rows of scan lines.

14. The display panel according to claim 12, characterized in that, The first gate driving circuit includes Q first shift registers, the output terminals of the Q first shift registers are connected one-to-one with the odd-numbered rows of the N rows of the scan lines, where Q < N and is a positive integer; the second gate driving circuit includes NQ second shift registers, the output terminals of the NQ second shift registers are connected one-to-one with the even-numbered rows of the N rows of the scan lines.

15. A display device, characterized in that, The display device includes a display panel as claimed in any one of claims 1-14.

Images