An enhancement-mode GaN HEMT with low gate leakage current and a method of fabricating the same

Abstract

The application discloses a kind of low grid leakage current's enhanced GaN HEMTs and preparation method thereof, the GaN HEMTs include substrate, buffer layer, channel layer, barrier layer, source contact electrode, drain contact electrode, p-GaN-based self-aligned T-shaped gate control structure and passivation layer, p-GaN-based self-aligned T-shaped gate control structure includes P-GaN cap layer, gate passivation layer and gate metal;Buffer layer, channel layer, barrier layer and P-GaN cap layer are sequentially arranged on substrate from bottom to top, source contact electrode and drain contact electrode are both arranged on the partial upper surface of barrier layer, and respectively located at the two sides of p-GaN-based self-aligned T-shaped gate control structure, gate metal is arranged on the partial upper surface of P-GaN cap layer, gate passivation layer is arranged on the upper surface of P-GaN cap layer remaining part and the upper surface of barrier layer remaining part, passivation layer is arranged on the upper surface of gate passivation layer.The application not only can effectively reduce the grid leakage current under the forward high grid voltage, simultaneously effectively avoids the introduction of additional grid capacitance, obtains high reliability gate structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to an enhanced GaNHEMT with low gate leakage current and its preparation method. Background Technology

[0002] Third-generation semiconductor GaN materials possess excellent properties such as wide bandgap, high breakdown field strength, high saturated electron drift velocity, and high-concentration heterojunction two-dimensional electron gas. They are the preferred structure for fabricating high-power, high-breakdown-voltage, and high-frequency power electronic devices, and have important application prospects in wireless communication, power systems, detection, and other fields.

[0003] In recent years, gallium nitride-based high electron mobility transistors (HNTs) have provided solutions for discrete transistors, integrated circuits, and multi-chip modules for aerospace applications, offering wider power ranges and operating frequencies. Currently, the mainstream enhancement-mode device is the P-type GaN cap-structured GaN HNT, widely used in rectifier circuits, inverter bridges, and switching regulator circuits. Under high voltage, gate leakage current has become a significant factor affecting device reliability. The main source of gate leakage current is the defect level introduced by P-GaN cap-layer etching damage. To address the etching damage problem, researchers both domestically and internationally have employed various growth methods to grow single-layer or multi-layer passivation structures of HfO2, ZrO2, Si3N4, SiO2, Al2O3, and AlNO to improve the etching interface. However, the passivation layer introduces additional parasitic capacitance during practical applications, and unstable dielectric quality can introduce new defects within the dielectric, leading to a decrease in device reliability and yield. Therefore, developing a GaN-based high electron mobility transistor that effectively improves the etching interface without introducing additional parasitic capacitance is of great significance for practical applications. Summary of the Invention

[0004] Technical problem solved: To address the above-mentioned technical problems, this invention provides an enhanced GaNHEMT with low gate leakage current and its preparation method, which can effectively solve the shortcomings of the above methods, such as large gate leakage current and the introduction of additional parasitic capacitance.

[0005] Technical Solution: In a first aspect, the present invention provides an enhancement-mode GaN HEMT with low gate leakage current, comprising a substrate, a buffer layer, a channel layer, a barrier layer, a source contact electrode, a drain contact electrode, a p-GaN-based self-aligned T-type gate control structure, and a passivation layer. The p-GaN-based self-aligned T-type gate control structure includes a P-GaN cap layer, a gate passivation layer, and a gate metal. The buffer layer, channel layer, barrier layer, and P-GaN cap layer are sequentially disposed on the substrate from bottom to top. The source contact electrode and drain contact electrode are both disposed on a portion of the upper surface of the barrier layer and are located on opposite sides of the p-GaN-based self-aligned T-type gate control structure, respectively. The gate metal is disposed on a portion of the upper surface of the P-GaN cap layer. The gate passivation layer is disposed on the remaining portion of the upper surface of the P-GaN cap layer and the remaining portion of the upper surface of the barrier layer. The passivation layer is disposed on the upper surface of the gate passivation layer.

[0006] Preferably, the substrate is one of SiC, Si, sapphire, diamond, or GaN self-supporting substrates; the buffer layer is AlN or AlGa x N (1-x) A single-layer or multi-layer structure composed of one or more of GaN; the channel layer is one of GaN, AlN, or AlGaN; the barrier layer is AlGaN. x N (1-x) AlIn x N (1-x) Or one of AlN.

[0007] Preferably, the source contact electrode and the drain contact electrode are low work function metals, and the low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy or Ti-Al-Mo-Au alloy.

[0008] Preferably, the gate passivation layer is a single-layer structure or a multi-layer structure of HfO2, ZrO2, Si3N4, SiO2, Al2O3, and AlNO, and the total thickness is 1~100nm.

[0009] Preferably, the gate metal is a high work function metal, which is one of W, Ni, Pt or TiN.

[0010] Preferably, the passivation layer is one or more of SiO2, Si3N4, and Al2O3.

[0011] In a second aspect, the present invention provides a method for fabricating enhanced GaN HEMTs with low gate leakage current as described in the first aspect, comprising the following steps:

[0012] S1. A buffer layer, a channel layer, a barrier layer, and a p-GaN epitaxial layer are sequentially grown on the upper surface of the substrate using an epitaxial growth method.

[0013] S2. Define a mask for the P-GaN cap layer on the upper surface of the p-GaN epitaxial layer, and then form the P-GaN cap layer by etching.

[0014] S3. A gate passivation layer and a metal Ti layer are grown sequentially on the upper surface of the barrier layer and the P-GaN cap layer. Then, a mask is defined on the upper surface of the P-GaN cap layer, and the metal Ti layer and the gate passivation layer are etched to form a contact via of the gate metal.

[0015] S4. Define a mask for the gate metal in the contact via of the gate metal and on part of the upper surface of the metal Ti layer. Deposit a high work function metal by evaporation or sputtering. Form the gate metal by a stripping process. Remove the metal Ti layer with an etching solution to form a self-aligned T-type gate control structure consisting of a P-GaN cap layer, a gate passivation layer and a gate metal.

[0016] S5. Define the opening mask for the source contact electrode and the drain contact electrode on the upper surface of the gate passivation layer, and etch the gate passivation layer to form the opening by etching.

[0017] S6. Define a mask for the source contact electrode and the drain contact electrode on the upper surface of the gate passivation layer, deposit a low work function metal by evaporation or sputtering, and form the source contact electrode and the drain contact electrode by a stripping annealing process.

[0018] S7. An active region mask is fabricated on the upper surface of the barrier layer, and then isolated by etching or ion implantation to form the active region.

[0019] S8. Deposit a passivation layer on the upper surface of the source contact electrode, drain contact electrode, gate passivation layer and gate metal;

[0020] S9. Define an interconnect aperture mask on the upper surface of the source contact electrode, drain contact electrode, and gate metal, and form interconnect apertures by etching the passivation layer.

[0021] Preferably, the epitaxial growth method is any one of metal-organic chemical vapor deposition, molecular beam epitaxy, or hydride vapor phase epitaxy.

[0022] Preferably, the mask is fabricated by optical lithography or electron beam direct writing, and the etching method is either dry etching or wet etching.

[0023] Preferably, the passivation layer is grown by any one of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition.

[0024] Beneficial effects: 1) Conventional GaN-based high electron mobility transistors use a method of etching the metal and gate dielectric together when forming the gate structure. This causes the electric field to concentrate at the etched gate edge under a high gate bias voltage, resulting in the formation of a leakage channel. However, the T-shaped gate control structure used in this invention has a narrower bottom of the gate contact metal compared to the P-GaN cap layer. This allows the electric field to concentrate at the etched gate edge under a high gate bias voltage, thereby effectively reducing the gate leakage current.

[0025] 2) The present invention uses a combination of gate dielectric passivation layer and metal Ti layer as a mask to obtain a structure in which the upper part of T-shaped gate metal is separated from the gate passivation layer, effectively avoiding parasitic capacitance introduced by the contact between metal and passivation layer.

[0026] 3) The present invention adopts a step-by-step etching method with a difference in width between the p-GaN cap layer and the gate contact metal, which can increase the range of width selection of the p-GaN cap layer, thereby reducing the photolithographic registration requirements of the gate contact metal opening, and thus achieving a more refined gate contact metal process with higher fault tolerance. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of an enhanced GaN HEMT with low gate leakage current according to the present invention.

[0028] Figure 2 This is a schematic diagram of the fabrication process of a low-gate leakage current enhanced GaN HEMTs according to the present invention.

[0029] The numbers in the figure are: 1. Substrate, 2. Buffer layer, 3. Channel layer, 4. Barrier layer, 5. Source contact electrode, 6. Drain contact electrode, 7. P-GaN cap layer, 8. Gate passivation layer, 9. Gate metal, 10. Passivation layer. Detailed Implementation

[0030] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments:

[0031] Example 1

[0032] like Figure 1 As shown, an enhancement-mode GaN HEMT with low gate leakage current includes a GaN substrate 1, a GaN buffer layer 2, a GaN channel layer 3, and an AlGaN core. x N (1-x)Barrier layer 4, Ti-Al alloy source contact electrode 5, Ti-Al-Ni-Au alloy drain contact electrode 6, p-GaN-based self-aligned T-type gate structure and Si3N4 passivation layer 10; the p-GaN-based self-aligned T-type gate structure includes a P-GaN cap layer 7, a 50nm thick gate passivation layer 8 composed of Al2O3 and AlNO, and W gate metal 9; GaN buffer layer 2, GaN channel layer 3, AlGa x N (1-x) Barrier layer 4 and P-GaN cap layer 7 are sequentially disposed on GaN substrate 1 from bottom to top. Ti-Al alloy source contact electrode 5 and Ti-Al-Ni-Au alloy drain contact electrode 6 are both disposed on AlGaN substrate 1. x N (1-x) The barrier layer 4 is partially located on the upper surface of the self-aligned T-type gate structure based on p-GaN, and the gate metal 9 is disposed on a portion of the upper surface of the p-GaN cap layer 7. The gate passivation layer 8, composed of Al2O3 and AlNO with a thickness of 50 nm, is disposed on the remaining upper surface of the p-GaN cap layer 7 and AlGaN cap layer 7. x N (1-x) On the remaining upper surface of the barrier layer 4, a Si3N4 passivation layer 10 is disposed on the upper surface of the gate passivation layer 8, which is composed of Al2O3 and AlNO and has a thickness of 50 nm.

[0033] Example 2

[0034] like Figure 2 As shown, the preparation method of GaN HEMTs in Example 1 includes the following steps:

[0035] S1, such as Figure 2 As shown in Figure a, a GaN buffer layer 2, a GaN channel layer 3, and an AlGaN layer are sequentially grown on the upper surface of a GaN substrate 1 using metal-organic chemical vapor deposition. x N (1-x) Barrier layer 4 and p-GaN epitaxial layer;

[0036] S2, such as Figure 2 As shown in Figure b, a mask for a P-GaN cap layer 7 is defined on the upper surface of the p-GaN epitaxial layer, and then the P-GaN cap layer 7 is formed by dry etching.

[0037] S3, in AlGa x N (1-x) On the upper surfaces of the barrier layer 4 and the P-GaN cap layer 7, a gate passivation layer 8 composed of Al2O3 and AlNO and a metal Ti layer are grown sequentially. The thickness of Al2O3 is 20nm and the thickness of AlNO is 30nm. Then, a mask is defined on the upper surface of the P-GaN cap layer 7, and the contact via of the gate metal 9 is formed by etching the metal Ti layer and the gate passivation layer 8 composed of Al2O3 and AlNO.

[0038] S4, such as Figure 2 As shown in Figure c, a mask for the gate metal 9 is defined in the contact via of the gate metal 9 and on part of the upper surface of the metal Ti layer. The W metal is deposited by evaporation or sputtering, and the W gate metal 9 is formed by a stripping process. The metal Ti layer is removed by an etching solution, thereby forming a self-aligned T-type gate control structure composed of a P-GaN cap layer 7, a gate passivation layer 8 composed of Al2O3 and AlNO, and the W gate metal 9.

[0039] S5, such as Figure 2 As shown in Figure d, an opening mask for the source contact electrode 5 and the drain contact electrode 6 is defined on the upper surface of the gate passivation layer 8 composed of Al2O3 and AlNO, and the opening is formed by wet etching of the gate passivation layer 8 composed of Al2O3 and AlNO.

[0040] S6, such as Figure 2 As shown in Figure e, a mask for the source contact electrode 5 and the drain contact electrode 6 is defined on the upper surface of the gate passivation layer 8 composed of Al2O3 and AlNO. Ti-Al alloy and Ti-Al-Ni-Au alloy are deposited by sputtering, respectively, and Ti-Al alloy source contact electrode 5 and Ti-Al-Ni-Au alloy drain contact electrode 6 are formed by a stripping annealing process.

[0041] S7, in AlGa x N (1-x) An active region mask is fabricated on the upper surface of barrier layer 4, and then isolated by etching or ion implantation to form the active region;

[0042] S8, such as Figure 2 As shown in Figure f, an atomic layer deposition method is used to deposit a Si3N4 passivation layer 10 on the upper surface of the Ti-Al alloy source contact electrode 5, the Ti-Al-Ni-Au alloy drain contact electrode 6, the gate passivation layer 8 composed of Al2O3 and AlNO, and the gate metal 9.

[0043] S9. Define an interconnection aperture mask on the upper surface of the Ti-Al alloy source contact electrode 5, the Ti-Al-Ni-Au alloy drain contact electrode 6 and the W gate metal 9, and form interconnection apertures by dry etching the Si3N4 passivation layer 10.

[0044] Example 3

[0045] An enhancement-mode GaN HEMT with low gate leakage current includes a GaN substrate 1, a GaN buffer layer 2, a GaN channel layer 3, and an AlIn layer 4. x N (1-x)Barrier layer 4, Ti-Al alloy source contact electrode 5, Ti-Al-Ni-Au alloy drain contact electrode 6, p-GaN-based self-aligned T-type gate structure and Si3N4 passivation layer 10; the p-GaN-based self-aligned T-type gate structure includes a P-GaN cap layer 7, a 50nm thick gate passivation layer 8 composed of Al2O3 and AlNO, and a TiN gate metal 9; GaN buffer layer 2, GaN channel layer 3, AlIn x N (1-x) Barrier layer 4 and P-GaN cap layer 7 are sequentially disposed on GaN substrate 1 from bottom to top. Ti-Al-Ti-Ni alloy source contact electrode 5 and Ti-Al-Ni-Au alloy drain contact electrode 6 are both disposed on AlIn x N (1-x) The barrier layer 4 is partially located on the upper surface of the self-aligned T-type gate structure based on p-GaN, and TiN gate metal 9 is disposed on a portion of the upper surface of the p-GaN cap layer 7. A 50nm thick gate passivation layer 8 composed of Al2O3 and AlNO is disposed on the remaining upper surface of the p-GaN cap layer 7 and AlIn. x N (1-x) On the remaining upper surface of the barrier layer 4, a Si3N4 passivation layer 10 is disposed on the upper surface of the gate passivation layer 8, which is composed of Al2O3 and AlNO and has a thickness of 50 nm.

[0046] Example 4

[0047] The preparation method of GaN HEMTs in Example 3 includes the following steps:

[0048] S1. On the upper surface of GaN substrate 1, GaN buffer layer 2, GaN channel layer 3, and AlIn are sequentially grown using metal-organic chemical vapor deposition. x N (1-x) Barrier layer 4 and p-GaN epitaxial layer;

[0049] S2. Define a mask for the P-GaN cap layer 7 on the upper surface of the p-GaN epitaxial layer, and then form the P-GaN cap layer 7 by dry etching;

[0050] S3, in AlGa x N (1-x) On the upper surfaces of the barrier layer 4 and the P-GaN cap layer 7, a gate passivation layer 8 composed of Al2O3 and AlNO and a metal Ti layer are grown sequentially. The thickness of Al2O3 is 20nm and the thickness of AlNO is 30nm. Then, a mask is defined on the upper surface of the P-GaN cap layer 7, and the contact via of the gate metal 9 is formed by etching the metal Ti layer and the gate passivation layer 8 composed of Al2O3 and AlNO.

[0051] S4. Define a mask for the gate metal 9 in the contact via and on part of the Ti layer. Deposit TiN by evaporation or sputtering. Form TiN gate metal by stripping process. Remove the Ti layer with etching solution to form a self-aligned T-type gate structure consisting of P-GaN cap layer 7, gate passivation layer 8 composed of Al2O3 and AlNO and TiN gate metal 9.

[0052] S5. Define the opening mask for the source contact electrode 5 and the drain contact electrode 6 on the upper surface of the gate passivation layer 8 composed of Al2O3 and AlNO, and form the opening by wet etching of the gate passivation layer 8 composed of Al2O3 and AlNO.

[0053] S6. Define a mask for source contact electrode 5 and drain contact electrode 6 on the upper surface of the gate passivation layer 8 composed of Al2O3 and AlNO. Deposit Ti-Al-Ti-Ni alloy and Ti-Al-Ni-Au alloy respectively by sputtering. Form Ti-Al-Ti-Ni alloy source contact electrode 5 and Ti-Al-Ni-Au alloy drain contact electrode 6 by peeling annealing process.

[0054] S7, in AlIn x N (1-x) An active region mask is fabricated on the upper surface of barrier layer 4, and then isolated by etching or ion implantation to form the active region;

[0055] S8. On the upper surface of Ti-Al-Ti-Ni alloy source contact electrode 5, Ti-Al-Ni-Au alloy drain contact electrode 6, gate passivation layer 8 composed of Al2O3 and AlNO and TiN gate metal 9, an atomic layer deposition method is used to deposit Si3N4 passivation layer 10.

[0056] S9. Define an interconnection aperture mask on the upper surface of the Ti-Al-Ti-Ni alloy source contact electrode 5, the Ti-Al-Ni-Au alloy drain contact electrode 6, and the TiN gate metal 9, and form interconnection apertures by dry etching the Si3N4 passivation layer 10.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating enhancement-mode GaN HEMTs with low gate leakage current, characterized in that, The enhanced GaN HEMTs include a substrate (1), a buffer layer (2), a channel layer (3), a barrier layer (4), a source contact electrode (5), a drain contact electrode (6), a p-GaN-based self-aligned T-type gate structure, and a passivation layer (10). The p-GaN-based self-aligned T-type gate structure includes a P-GaN cap layer (7), a gate passivation layer (8), and a gate metal (9). The buffer layer (2), channel layer (3), barrier layer (4), and P-GaN cap layer (7) are arranged sequentially from bottom to top. On the substrate (1), the source contact electrode (5) and the drain contact electrode (6) are both disposed on a portion of the upper surface of the barrier layer (4) and are located on both sides of the self-aligned T-type gate control structure based on p-GaN, respectively. The gate metal (9) is disposed on a portion of the upper surface of the P-GaN cap layer (7), the gate passivation layer (8) is disposed on the remaining upper surface of the P-GaN cap layer (7) and the remaining upper surface of the barrier layer (4), and the passivation layer (10) is disposed on the upper surface of the gate passivation layer (8). The preparation method includes the following steps: S1. A buffer layer (2), a channel layer (3), a barrier layer (4) and a p-GaN epitaxial layer are grown sequentially on the upper surface of the substrate (1) using an epitaxial growth method. S2. Define a mask for the P-GaN cap layer (7) on the upper surface of the p-GaN epitaxial layer, and then form the P-GaN cap layer (7) by etching. S3. A gate passivation layer (8) and a metal Ti layer are grown sequentially on the upper surfaces of the barrier layer (4) and the P-GaN cap layer (7). Then, a mask is defined on the upper surface of the P-GaN cap layer (7) to form a contact via of the gate metal (9) by etching the metal Ti layer and the gate passivation layer (8). S4. Define a mask for the gate metal (9) in the contact via of the gate metal (9) and on the surface of part of the metal Ti layer. Deposit a high work function metal by evaporation or sputtering. Form the gate metal (9) by a stripping process. Remove the metal Ti layer with an etching solution to form a self-aligned T-type gate control structure consisting of a P-GaN cap layer (7), a gate passivation layer (8), and the gate metal (9). S5. Define the opening mask of the source contact electrode (5) and the drain contact electrode (6) on the upper surface of the gate passivation layer (8), and etch the gate passivation layer (8) to form the opening by etching. S6. Define a mask for the source contact electrode (5) and the drain contact electrode (6) on the upper surface of the gate passivation layer (8), deposit a low work function metal by evaporation or sputtering, and form the source contact electrode (5) and the drain contact electrode (6) by a stripping annealing process. S7. An active region mask is fabricated on the upper surface of the barrier layer (4), and then isolated by etching or ion implantation to form an active region. S8. A passivation layer (10) is deposited on the upper surface of the source contact electrode (5), the drain contact electrode (6), the gate passivation layer (8), and the gate metal (9). S9. Define an interconnect opening mask on the upper surface of the source contact electrode (5), the drain contact electrode (6) and the gate metal (9), and form interconnect openings by etching the passivation layer (10) using an etching method.

2. The preparation method according to claim 1, characterized in that: The substrate (1) is one of SiC, Si, sapphire, diamond, or GaN self-supporting substrates; the buffer layer (2) is AlN or AlGa x N (1-x) The structure is a single-layer or multi-layer structure composed of one or more of GaN, AlN, or AlGaN; the channel layer (3) is one of GaN, AlN, or AlGaN; the barrier layer (4) is AlGaN. x N (1-x) AlIn x N (1-x) Or one of AlN.

3. The preparation method according to claim 1, characterized in that: The source contact electrode (5) and the drain contact electrode (6) are low work function metals, which are one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy or Ti-Al-Mo-Au alloy.

4. The preparation method according to claim 1, characterized in that: The gate passivation layer (8) is a single-layer structure or multiple stacked structures of HfO2, ZrO2, Si3N4, SiO2, Al2O3, and AlNO, and the total thickness is 1~100nm.

5. The preparation method according to claim 1, characterized in that: The gate metal (9) is a high work function metal, which is one of W, Ni, Pt or TiN.

6. The preparation method according to claim 1, characterized in that: The passivation layer (10) is one or more of SiO2, Si3N4, and Al2O3.

7. The preparation method according to claim 1, characterized in that: The epitaxial growth method is any one of metal-organic chemical vapor deposition, molecular beam epitaxy, or hydride vapor phase epitaxy.

8. The preparation method according to claim 1, characterized in that: The mask is fabricated by optical lithography or electron beam direct writing, and the etching method is either dry etching or wet etching.

9. The preparation method according to claim 1, characterized in that: The passivation layer is grown using any one of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition.

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