An apparatus for implementing an NMOS tube acceleration drive

Abstract

The application provides a device for implementing NMOS tube acceleration driving, wherein the device comprises a power supply module, a voltage boosting module and a control module; a first output end of the power supply module is connected with an input end of the voltage boosting module; an output end of the voltage boosting module is connected with a first input end of the control module; a second output end of the power supply module is connected with a second input end of the control module; and an output end of the control module is connected with a gate of a target NMOS tube; the power supply module provides a first initial current to the input end of the voltage boosting module through the first output end and provides a second initial current to the second input end of the control module through the second output end; the voltage boosting module boosts the first initial current to obtain a first target current and outputs the first target current to the first input end of the control module; and the control module drives the target NMOS tube according to the second initial current and the first target current through the output end.

Description

Technical Field

[0001] This invention relates to the field of circuit driving, and more specifically, to a device for accelerating the driving of NMOS transistors. Background Technology

[0002] In the design of drive circuits, ground-side drive and power-side drive are two typical requirements. Ground-side drive is mainly divided into driving N-type power devices and driving P-type power devices. However, in practical applications, because N-type power devices have better current capability than P-type devices, but require a higher voltage to turn on to control N-type devices, ground-side drive circuits are more commonly used for driving N-type power devices.

[0003] There are two common methods. One is circuit bootstrapping. Bootstrapping is the use of bootstrap capacitors and diodes to boost the voltage. For example, in a synchronous buck converter (BUCK) circuit, Cboot+ diode. Bootstrapping technology is widely used in switching power supply circuits. Another approach utilizes a charge pump to provide a stable high-voltage environment (not a switching circuit, but a linear boost). This boost method is more common in power path and ideal diode linear boost applications. However, limited by the current supply capability of the built-in charge pump, this method can achieve a drive voltage tens of volts higher than the supply voltage, but the drive current is only a few hundred microamps. In common chip-based built-in charge pump implementations, a MHz clock combined with a pF-level charge pump typically provides only tens of microamps or even less of external current. However, the input capacitance of common power NMOS transistors is tens of nF or even hundreds of nF. It can be estimated that the setup time required for a charge pump boost method to fully turn on an external N-type power device is around ms. This setup time far exceeds the ground-side drive setup time or the power-side drive time for P-type devices. In other words, it takes a significant amount of time to drive the NMOS transistor. Therefore, shortening the time required to drive the NMOS transistor has become a pressing issue. Summary of the Invention

[0004] In view of this, the object of the present invention is to provide an apparatus for accelerating the driving of NMOS transistors, so as to shorten the time required to drive NMOS transistors.

[0005] In a first aspect, embodiments of this application provide an apparatus for accelerating the driving of an NMOS transistor. The apparatus includes a power supply module, a boost module, and a control module. The first output terminal of the power supply module is connected to the input terminal of the boost module, the output terminal of the boost module is connected to the first input terminal of the control module, the second output terminal of the power supply module is connected to the second input terminal of the control module, and the output terminal of the control module is connected to the gate of the target NMOS transistor. The power module is used to provide a first initial current to the input terminal of the boost module through the first output terminal of the power module, and is also used to provide a second initial current to the second input terminal of the control module through the second output terminal of the power module, wherein there is a voltage difference between the power domain of the first initial current and the power domain of the second initial current; The boost module is used to boost the first initial current to obtain a first target current, and output the first target current to the first input terminal of the control module through its output terminal. The control module is used to power the target NMOS transistor through its output terminal according to the second initial current and the first target current, so as to drive the target NMOS transistor.

[0006] Optionally, the control module includes an enable signal generation module, a timing signal generation module, and a timing switch module. The first input terminal of the enable signal generation module is connected to the output terminal of the boost module, the second input terminal of the enable signal generation module is connected to the second output terminal of the power supply module, the output terminal of the enable signal generation module is connected to the input terminal of the timing signal generation module, the output terminal of the timing signal generation module is connected to the input terminal of the timing switch module, and the output terminal of the timing switch module is connected to the gate of the target NMOS transistor.

[0007] Optionally, the enable signal generation module is used to generate an enable signal based on the second initial current and the first target current, and is also used to output the enable signal to the first input terminal of the timing signal generation module through the output terminal of the enable signal generation module; The timing signal generation module is used to generate a timing control signal according to the enable signal, and is also used to output the timing control signal to the input terminal of the timing switch module through the output terminal of the timing signal generation module. The timing switch module is used to drive the target NMOS transistor according to the timing control signal.

[0008] Optionally, the timing switch module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a first energy storage capacitor; The first output terminal of the timing signal generation module is connected to the gate of the first NMOS transistor, the second output terminal of the timing signal generation module is connected to the gate of the second NMOS transistor, the third output terminal of the timing signal generation module is connected to the gate of the third NMOS transistor, and the fourth output terminal of the timing signal generation module is connected to the gate of the first PMOS transistor. The sources of the first NMOS transistor and the first PMOS transistor are both connected to the first output terminal of the power supply module. The drain of the first NMOS transistor is connected to the upper plate of the first energy storage capacitor and the source of the third NMOS transistor, respectively. The drain of the third NMOS transistor is connected to the gate of the target NMOS transistor. The drain of the first PMOS transistor is connected to the lower plate of the first energy storage capacitor and the drain of the second NMOS transistor, respectively. The source of the second NMOS transistor is connected to the second output terminal of the power supply module.

[0009] Optionally, the timing signal generation module includes a non-overlapping clock generation module, a falling delay module, a rising delay module, a first level conversion module, and a second level conversion module, and the timing control signal includes a first control signal, a second control signal, a third control signal, and a fourth control signal; The input terminal of the non-overlapping clock generation module is connected to the output terminal of the enable signal generation module. The first output terminal of the non-overlapping clock generation module is connected to the gate of the first PMOS transistor and the input terminal of the fall delay module. The second output terminal of the non-overlapping clock generation module is connected to the gate of the second NMOS transistor and the input terminal of the rise delay module. The output terminal of the fall delay module is connected to the input terminal of the first level conversion module. The output terminal of the rise delay module is connected to the input terminal of the second level conversion module. The output terminal of the first level conversion module is connected to the gate of the third NMOS transistor, and the output terminal of the second level conversion module is connected to the gate of the first NMOS transistor.

[0010] Optionally, the non-overlapping clock generation module is configured to generate the first control signal and the second control signal according to the enable signal, and is further configured to send the first control signal to the gate of the first PMOS transistor and the input of the fall delay module through the first output terminal of the non-overlapping clock generation module, and to send the second control signal to the gate of the second NMOS transistor and the input of the rise delay module through the second output terminal of the non-overlapping clock generation module, wherein the first control signal is used to control the driving state of the first PMOS transistor, and the second control signal is used to control the driving state of the second NMOS transistor; The falling delay module is used to generate a time delay on the falling edge of the first control signal to obtain a third initial signal; The first level conversion module is used to convert the power domain of the third initial signal to obtain the third control signal, wherein the third control signal is used to control the driving state of the third NMOS transistor; The rising delay module is used to generate a time delay on the rising edge of the second control signal to obtain a fourth initial signal; The second level conversion module is used to convert the power domain of the fourth initial signal to obtain the fourth control signal, wherein the fourth control signal is used to control the driving state of the first NMOS transistor.

[0011] Optionally, the control module further includes a constant current source, the input terminal of which is connected to the output terminal of the boost module, and the output terminal of which is connected to the gate of the target NMOS transistor. The constant current source is used to provide pull-up current to the gate of the target NMOS transistor through its output terminal.

[0012] Optionally, the timing switch module includes at least one timing switch controller, at least one timing switch, and a second energy storage capacitor. Each output terminal of the timing signal generation module is connected to a timing switch controller, and each timing switch controller is connected to a timing switch. The at least one timing switch and the second energy storage capacitor form a charging and discharging circuit. The first input terminal of the charging and discharging circuit is connected to the first output terminal of the power module, the second input terminal of the charging and discharging circuit is connected to the second output terminal of the power module, the first output terminal of the charging and discharging circuit is connected to the gate of the target NMOS transistor, and the second output terminal of the charging and discharging circuit is connected to the source of the target NMOS transistor. For each of the at least one timing switch controller, the timing switch controller is used to control the timing switch connected to it to close or open according to the timing control signal; The charging and discharging circuit is used to discharge to the target NMOS transistor through the second energy storage capacitor according to the open or closed state of each of the timing switches, so as to drive the target NMOS transistor.

[0013] Optionally, the boost module includes a charge pump booster, the input terminal of which is connected to the first output terminal of the power module, and the output terminal of which is connected to the first input terminal of the control module.

[0014] Optionally, the voltage difference between the power supply domain of the first initial current and the power supply domain of the second initial current can be in the range of [3,5].

[0015] The technical solution provided in this application includes, but is not limited to, the following beneficial effects: The device provided in this application improves the driving method of NMOS transistors by using a power supply module, a boost module, and a control module to boost the current used to drive the target NMOS transistor, and simultaneously driving the target NMOS transistor based on the currents with different power domains before and after the boost, thereby shortening the time required to drive the NMOS transistor.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a device for accelerating NMOS transistor driving provided in Embodiment 1 of the present invention is shown. Figure 2 A schematic diagram of the structure of the second NMOS transistor driving device provided in Embodiment 1 of the present invention is shown; Figure 3 A schematic diagram of the third NMOS transistor driving device provided in Embodiment 1 of the present invention is shown; Figure 4 A schematic diagram illustrating the relationship between timing signals and the energization state of a MOS transistor, provided in Embodiment 1 of the present invention, is shown. Figure 5 A schematic diagram of the structure of the fourth NMOS transistor driving device provided in Embodiment 1 of the present invention is shown; Figure 6 This diagram shows a structural schematic of a non-overlapping clock generation module provided in Embodiment 1 of the present invention; Figure 7 This shows a schematic diagram of the structure of a fallback delay module provided in Embodiment 1 of the present invention; Figure 8 This diagram illustrates the structure of a rise delay module provided in Embodiment 1 of the present invention. Figure 9 This shows a schematic diagram of the structure of the first level conversion module provided in Embodiment 1 of the present invention; Figure 10 A schematic diagram of the structure of the second level conversion module provided in Embodiment 1 of the present invention is shown; Figure 11 A schematic diagram of the level conversion circuit provided in Embodiment 1 of the present invention is shown; Figure 12 A schematic diagram of the fifth NMOS transistor driving device provided in Embodiment 1 of the present invention is shown; Figure 13 A schematic diagram of the sixth NMOS transistor driving device provided in Embodiment 1 of the present invention is shown; Figure 14 A schematic diagram of the seventh NMOS transistor driving device provided in Embodiment 1 of the present invention is shown. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0020] Example 1 To facilitate understanding of this application, the following is combined with... Figure 1 The schematic diagram of the device for accelerating NMOS transistor driving shown in Embodiment 1 of the present invention will be described in detail for Embodiment 1 of this application.

[0021] See Figure 1 As shown, Figure 1 The diagram shows a schematic of a device for accelerating the driving of an NMOS transistor according to Embodiment 1 of the present invention. The device includes a power supply module 1, a boost module 2, and a control module 3. The first output terminal of the power supply module 1 is connected to the input terminal of the boost module 2, the output terminal of the boost module 2 is connected to the first input terminal of the control module 3, the second output terminal of the power supply module 1 is connected to the second input terminal of the control module 3, and the output terminal of the control module 3 is connected to the gate of the target NMOS transistor. The power module 1 is used to provide a first initial current to the input terminal of the boost module 2 through the first output terminal of the power module 1, and is also used to provide a second initial current to the second input terminal of the control module 3 through the second output terminal of the power module 1, wherein there is a voltage difference between the power domain of the first initial current and the power domain of the second initial current. The boost module 2 is used to boost the first initial current to obtain a first target current, and output the first target current to the first input terminal of the control module 3 through its output terminal. The control module 3 is used to supply power to the target NMOS transistor through its output terminal according to the second initial current and the first target current, so as to drive the target NMOS transistor.

[0022] Specifically, the power module outputs a first initial current from the first output terminal and a second initial current from the second output terminal. The voltage difference between the power domain of the first initial current and the power domain of the second initial current is... The boost module boosts the first initial current to obtain the first target current, and outputs the first target current to the first input terminal of the control module through its output terminal, so that the control module can supply power to the target NMOS transistor according to the second initial current and the first target current, thereby driving the target NMOS transistor.

[0023] In one feasible implementation plan, see Figure 2 As shown, Figure 2 The diagram illustrates a second type of device for accelerating NMOS transistor driving according to Embodiment 1 of the present invention. The control module 3 includes an enable signal generation module 31, a timing signal generation module 32, and a timing switch module 33. The first input terminal of the enable signal generation module 31 is connected to the output terminal of the boost module 2, the second input terminal of the enable signal generation module 31 is connected to the second output terminal of the power supply module 1, the output terminal of the enable signal generation module 31 is connected to the input terminal of the timing signal generation module 32, the output terminal of the timing signal generation module 32 is connected to the input terminal of the timing switch module 33, and the output terminal of the timing switch module 33 is connected to the gate of the target NMOS transistor.

[0024] In one feasible implementation, the enable signal generation module 31 is used to generate an enable signal according to the second initial current and the first target current, and is also used to output the enable signal to the first input terminal of the timing signal generation module 32 through the output terminal of the enable signal generation module 31. The timing signal generation module 32 is used to generate a timing control signal according to the enable signal, and is also used to output the timing control signal to the input terminal of the timing switch module 33 through the output terminal of the timing signal generation module 32. The timing switch module 33 is used to drive the target NMOS transistor according to the timing control signal.

[0025] Specifically, after receiving the second initial current and the first target current, the control module generates an enable signal based on the second initial current and the first target current, the timing signal generation module generates a timing control signal based on the enable signal, and the timing switch module drives the target NMOS transistor based on the timing control signal.

[0026] In one feasible implementation plan, see Figure 3 As shown, Figure 3 The diagram shows a third type of device for accelerating NMOS transistor drive provided in Embodiment 1 of the present invention. The timing switch module 33 includes a first NMOS transistor 331, a second NMOS transistor 332, a third NMOS transistor 333, a first PMOS transistor 334, and a first energy storage capacitor 335. The first output terminal of the timing signal generation module 32 is connected to the gate of the first NMOS transistor 331, the second output terminal of the timing signal generation module 32 is connected to the gate of the second NMOS transistor 332, the third output terminal of the timing signal generation module 32 is connected to the gate of the third NMOS transistor 333, the fourth output terminal of the timing signal generation module 32 is connected to the gate of the first PMOS transistor 334, the source of the first NMOS transistor 331 and the source of the first PMOS transistor 334 are both connected to the first output terminal of the power supply module 1, the drain of the first NMOS transistor 331 is connected to the upper plate of the first energy storage capacitor 335 and the source of the third NMOS transistor 333, the drain of the third NMOS transistor 333 is connected to the gate of the target NMOS transistor, the drain of the first PMOS transistor 334 is connected to the lower plate of the first energy storage capacitor 335 and the drain of the second NMOS transistor 332, and the source of the second NMOS transistor 332 is connected to the second output terminal of the power supply module 1.

[0027] For details, see Figure 4 As shown, Figure 4 The diagram illustrates the relationship between timing signals and the on-state of MOS transistors according to Embodiment 1 of the present invention. Before the control module sends the enable signal, the first and second NMOS transistors are in the on state, while the third NMOS transistor and the first PMOS transistor are in the off state. At this time, the potential of the upper plate CT of the first energy storage capacitor is... satisfy: ; Potential of the lower plate CB satisfy: ; The amount of charge stored in the first energy storage capacitor satisfy: ; in, The voltage value of the first initial current. The voltage difference between the first initial current and the second initial current. This is the capacitance value of the first energy storage capacitor. The following describes the actions taken after the enable signal is issued: Step 1: The second NMOS transistor is turned off, and the lower plate of the capacitor loses its connection with the second output terminal of the power module.

[0028] Step 2: The first NMOS transistor is disconnected, the upper plate of the capacitor loses its connection with the first output terminal of the power module, and the whole thing is in a floating state.

[0029] Step 3: The first PMOS transistor is turned on, the lower plate of the capacitor is connected to the first output terminal of the power module, and the potential of the upper plate changes abruptly. .

[0030] Step 4: The third NMOS transistor is turned on, and the upper plate of the capacitor is connected to the gate of the target NMOS transistor. The charge on the first energy storage capacitor shares the charge with the gate of the target NMOS transistor.

[0031] The gate voltage of the target NMOS transistor will change abruptly due to the introduction of the first energy storage capacitor, and the drive voltage value of the target NMOS transistor will also change. satisfy: ; in, This is the capacitance value of the first energy storage capacitor. The voltage difference between the first initial current and the second initial current. The value of the gate capacitance of the target NMOS transistor.

[0032] In actual circuits, the capacitance of the first energy storage capacitor is much larger than the input capacitance of the target NMOS transistor. The following describes the actions that occur after the enable signal disappears: Step 5: The first PMOS transistor is disconnected, and the lower plate of the first energy storage capacitor loses its connection with the first output terminal of the power module.

[0033] Step 6: The third NMOS transistor is turned off, and the upper plate of the first energy storage capacitor loses its connection with the gate of the target NMOS transistor, and the whole is in a floating state.

[0034] Step 7: The second NMOS transistor is turned on, and the lower plate of the first energy storage capacitor is connected to the second output terminal of the power module, but the voltage difference between the upper and lower plates remains unchanged.

[0035] Step 8: The first NMOS transistor is turned on, and the upper plate of the capacitor is connected to the first output terminal of the power module. The first output terminal of the power module replenishes the charge of the first energy storage capacitor.

[0036] Finally, the potentials of the upper and lower plates of the first energy storage capacitor return to the state before the enable signal was issued. At this point, the connection between the first energy storage capacitor and the gate of the target NMOS transistor is broken, and the rapid setup process ends.

[0037] In one feasible implementation plan, see Figure 5 As shown, Figure 5 The diagram shows a fourth type of device for accelerating NMOS transistor driving provided in Embodiment 1 of the present invention. The timing signal generation module 32 includes a non-overlapping clock generation module 321, a falling delay module 322, a rising delay module 323, a first level conversion module 324, and a second level conversion module 325. The timing control signal includes a first control signal, a second control signal, a third control signal, and a fourth control signal. The input terminal of the non-overlapping clock generation module 321 is connected to the output terminal of the enable signal generation module 31. The first output terminal of the non-overlapping clock generation module 321 is connected to the gate of the first PMOS transistor 334 and the input terminal of the fall delay module 322. The second output terminal of the non-overlapping clock generation module 321 is connected to the gate of the second NMOS transistor 332 and the input terminal of the rise delay module 323. The output terminal of the fall delay module 322 is connected to the input terminal of the first level conversion module 324. The output terminal of the rise delay module 323 is connected to the input terminal of the second level conversion module 325. The output terminal of the first level conversion module 324 is connected to the gate of the third NMOS transistor 333, and the output terminal of the second level conversion module 325 is connected to the gate of the first NMOS transistor 331.

[0038] For details, see Figure 6 As shown, Figure 6The diagram shows a structural schematic of a non-overlapping clock generation module provided in Embodiment 1 of the present invention. The non-overlapping clock generation module includes a first NOT gate circuit 3211, a second NOT gate circuit 3212, a first NAND gate circuit 3213, a second NAND gate circuit 3214, a second PMOS transistor 3215, a fourth NMOS transistor 3216, a third PMOS transistor 3217, a fifth NMOS transistor 3218, a first pull-up resistor 3219, a second pull-up resistor 32210, a first pull-down resistor 32211, a second pull-down resistor 32212, a first Schmitt trigger 32213, a second Schmitt trigger 32214, a third NOT gate circuit 32215, a fourth NOT gate circuit 32216, a first non-inverting buffer 32217, a second non-inverting buffer 32218, a fifth NOT gate circuit 32219, and a sixth NOT gate circuit 32220.

[0039] The input terminal of the first NOT gate 3211 is connected to the output terminal of the enable signal generation module 31. The output terminal of the first NOT gate 3211 is connected to the input terminal of the second NOT gate 3212 and the first input terminal of the second NAND gate 3214. The output terminal of the second NOT gate 3212 is connected to the first input terminal of the first NAND gate 3213. The output terminal of the first NAND gate 3213 is connected to the gate of the second PMOS transistor 3215 and the gate of the fourth NMOS transistor 3216. The source of the second PMOS transistor 3215 is connected to the first terminal of the first pull-up resistor 3219. The second terminal of the first pull-up resistor 3219 is connected to the first input terminal of the power supply module 1. The drains of the second PMOS transistor 3215 and the fourth NMOS transistor 3216 are connected to the input of the first Schmitt trigger 32213 and the first end of the first pull-down resistor 32211. The second end of the first pull-down resistor 32211 is grounded. The source of the fourth NMOS transistor 3216 is connected to the second output of the power module 1. The output of the first Schmitt trigger 32213 is connected to the input of the third NOT gate 32215. The output of the third NOT gate 32215 is connected to the input of the fourth NOT gate 32216. The output of the fourth NOT gate 32216 is connected to the input of the fall-delay module 322. The input terminal of the first non-inverting buffer 32217 is connected to the input terminal of the first non-inverting buffer 32217 and the gate of the first PMOS transistor 3218. The output terminal of the first non-inverting buffer 32217 is connected to the second input terminal of the second NAND gate circuit 3214. The output terminal of the second NAND gate circuit 3214 is connected to the gate of the third PMOS transistor 3217 and the gate of the fifth NMOS transistor 3218. The source of the third PMOS transistor 3217 is connected to the first terminal of the second pull-up resistor 32210. The second terminal of the second pull-up resistor 32210 is connected to the first output terminal of the power module 1. The drains of the third PMOS transistor 3217 and the fifth NMOS transistor 3218 are both connected to the first input terminal of the power module 1. The input terminal of the second Schmitt trigger 32214 and the first terminal of the second pull-down resistor 32212 are connected. The second terminal of the second pull-down resistor 32212 is grounded. The output terminal of the second Schmitt trigger 32214 is connected to the input terminal of the second non-inverting buffer 32218. The output terminal of the second non-inverting buffer 32218 is connected to the input terminal of the fifth NOT gate 32219. The output terminal of the fifth NOT gate 32219 is connected to the input terminal of the sixth NOT gate 32220, the rise delay module 323, and the second NMOS transistor 332. The output terminal of the sixth NOT gate 32220 is connected to the second input terminal of the first NAND gate 3213.This stage is a variation of the non-overlapping clock generation circuit, designed to generate two NMOS transistors and a first PMOS transistor with a specific turn-on or turn-off sequence.

[0040] See Figure 7 As shown, Figure 7 The diagram shows a schematic of a fall delay module provided in Embodiment 1 of the present invention. The fall delay module includes a third in-phase buffer 3221, a fourth PMOS transistor 3222, a sixth NMOS transistor 3223, a third pull-up resistor 3224, a third pull-down resistor 3225, a third Schmitt trigger 3226, and a seventh NOT gate circuit 3227.

[0041] The input terminal of the third non-inverting buffer 3221 is connected to the output terminal of the fourth NOT gate circuit 32216. The output terminal of the third non-inverting buffer 3221 is connected to the gate of the fourth PMOS transistor 3222 and the gate of the sixth NMOS transistor 3223, respectively. The source of the fourth PMOS transistor 3222 is connected to the first terminal of the third pull-up resistor 3224. The second terminal of the third pull-up resistor 3224 is connected to the first output terminal of the power module 1. The drains of the fourth PMOS transistor 3222 and the sixth NMOS transistor 3223 are both connected to the input terminal of the third Schmitt trigger 3226 and the first terminal of the third pull-down resistor 3225. The second terminal of the third pull-down resistor 3225 is grounded. The output terminal of the third Schmitt trigger 3226 is connected to the input terminal of the seventh NOT gate circuit 3227. The output terminal of the seventh NOT gate circuit 3227 is connected to the input terminal of the first level conversion module.

[0042] See Figure 8 As shown, Figure 8 The diagram shows a schematic of a rising delay module provided in Embodiment 1 of the present invention. The rising delay module includes an eighth NOT gate circuit 3231, a fifth PMOS transistor 3232, a seventh NMOS transistor 3233, a fourth pull-up resistor 3234, a fourth pull-down resistor 3235, a fourth Schmitt trigger 3236, and a ninth NOT gate circuit 3237.

[0043] The input terminal of the eighth NOT gate circuit 3231 is connected to the output terminal of the fifth NOT gate circuit 32219. The output terminal of the eighth NOT gate circuit 3231 is connected to the gate of the fifth PMOS transistor 3232 and the gate of the seventh NMOS transistor 3233. The source of the fifth PMOS transistor 3232 is connected to the first terminal of the fourth pull-up resistor 3234. The second terminal of the fourth pull-up resistor 3234 is connected to the first output terminal of the power module 1. The drains of the fifth PMOS transistor 3232 and the seventh NMOS transistor 3233 are both connected to the input terminal of the fourth Schmitt trigger 3236 and the first terminal of the fourth pull-down resistor 3235. The second terminal of the fourth pull-down resistor 3235 is grounded. The output terminal of the fourth Schmitt trigger 3236 is connected to the input terminal of the ninth NOT gate circuit 3237. The output terminal of the ninth NOT gate circuit 3237 is connected to the input terminal of the second level conversion module.

[0044] The fall delay module or rise delay module performs different delay processing on the first PMOS transistor and the second NMOS transistor. For the first PMOS transistor signal, a fall delay processing is performed, and for the second NMOS transistor signal, a rise edge processing is performed. The purpose is to reduce the cost of the subsequent stage.

[0045] See Figure 9 As shown, Figure 9 A schematic diagram of the structure of the first level conversion module provided in Embodiment 1 of the present invention is shown, wherein the first low-level input terminal of the first level conversion module 324 is connected to the first output terminal of the power supply module 1, the second low-level input terminal of the first level conversion module 324 is connected to the second output terminal of the power supply module 1, the first high-level input terminal of the first level conversion module 324 is connected to an external power supply, the second high-level input terminal of the first level conversion module 324 is connected to the first output terminal of the power supply module 1, and the output terminal of the first level conversion module 324 is connected to the gate of the third NMOS transistor 333.

[0046] See Figure 10 As shown, Figure 10 A schematic diagram of the structure of the second level conversion module provided in Embodiment 1 of the present invention is shown, wherein the first low-level input terminal of the second level conversion module 325 is connected to the first output terminal of the power supply module 1, the second low-level input terminal of the second level conversion module 325 is connected to the second output terminal of the power supply module 1, the first high-level input terminal of the second level conversion module 325 is connected to the external power supply, the second high-level input terminal of the second level conversion module 325 is connected to the first output terminal of the power supply module 1, and the output terminal of the second level conversion module 325 is connected to the gate of the first NMOS transistor 331.

[0047] The level shifting module shifts the signals of the delayed first PMOS transistor and second NMOS transistor to ensure that they meet the sequential requirements in the time domain and also meet the requirements in the power domain. Otherwise, it will be impossible to turn on or off devices in other power domains.

[0048] See Figure 11 As shown, Figure 11 A schematic diagram of the level conversion circuit provided in Embodiment 1 of the present invention is shown, wherein the level conversion circuit includes a sixth PMOS transistor 401, a seventh PMOS transistor 402, an eighth PMOS transistor 403, a ninth PMOS transistor 404, a tenth PMOS transistor 405, an eleventh PMOS transistor 406, a twelfth PMOS transistor 407, an eighth NMOS transistor 408, a ninth NMOS transistor 409, a tenth NMOS transistor 410, an eleventh NMOS transistor 411, a twelfth NMOS transistor 412, a third energy storage capacitor 413, a tenth NOT gate circuit 414, and a built-in current source 415.

[0049] The source of the sixth PMOS transistor 401, the upper plate of the third energy storage capacitor 413, the source of the seventh PMOS transistor 402, the source of the eighth PMOS transistor 403, the source of the ninth PMOS transistor 404, the source of the eleventh PMOS transistor 406, and the source of the twelfth PMOS transistor 407 are all connected to the external power supply. The gate of the sixth PMOS transistor 401 is connected to the gate of the seventh PMOS transistor 402 and the gate of the eighth PMOS transistor 403, respectively. The gate of the ninth PMOS transistor 404 is connected to the gate of the ninth PMOS transistor 406. The drain of the OS transistor 404 is connected to the source of the tenth PMOS transistor 405. The gate of the tenth PMOS transistor 405 is connected to the drain of the tenth PMOS transistor 405, the drain of the eighth PMOS transistor 403, the drain of the twelfth NMOS transistor 412, and the gate of the eleventh PMOS transistor 406. The drain of the sixth PMOS transistor 401 is connected to the drain of the tenth NMOS transistor 410 and the gate of the tenth NMOS transistor 410. The drain of the seventh PMOS transistor 402 is connected to the gate of the seventh PMOS transistor 402. The drain of the eleventh NMOS transistor 411 is connected to the gate of the eleventh PMOS transistor 406, which is connected to the drain of the eighth NMOS transistor 408, the gate of the twelfth PMOS transistor 407, and the gate of the ninth NMOS transistor 409. The drains of the twelfth PMOS transistor 407 and the ninth NMOS transistor 409 are both connected to the input terminal of the third NMOS transistor or the input terminal of the first NMOS transistor. The sources of the ninth NMOS transistor 409, the eighth NMOS transistor 408, and the tenth NMOS transistor 410 are also connected to the gate of the eleventh PMOS transistor 406. The lower plate of the third energy storage capacitor 413 is connected to the first output terminal of the power module. The gate of the eleventh NMOS transistor 411 is connected to the output terminal of the second NMOS transistor or the output terminal of the first PMOS transistor and the input terminal of the tenth NOT gate circuit 414. The output terminal of the tenth NOT gate circuit 414 is connected to the gate of the twelfth NMOS transistor 412. The source of the twelfth NMOS transistor 412 is connected to the source of the eleventh NMOS transistor 411 and the input terminal of the built-in current source 415. The output terminal of the built-in current source 415 is grounded.

[0050] The floating power domain is VCC, VCC-Δ (the power domain of signal A). Signal A is converted from voltage to current through a differential pair structure. The current signal crosses the power domain to a new power domain VCC+δ, VCC (the power domain of signal A after conversion by the level conversion unit, where δ is the voltage change). It is then restored to a voltage signal. After being further shaped by a first-level buffer, signal B with a very short delay but a changed power domain is obtained.

[0051] In one feasible implementation, the non-overlapping clock generation module 321 is configured to generate the first control signal and the second control signal according to the enable signal, and is further configured to send the first control signal to the gate of the first PMOS transistor 334 and the input of the fall delay module 322 through the first output terminal of the non-overlapping clock generation module 321, and to send the second control signal to the gate of the second NMOS transistor 332 and the input of the rise delay module 323 through the second output terminal of the non-overlapping clock generation module 321, wherein the first control signal is used to control the driving state of the first PMOS transistor 334, and the second control signal is used to control the driving state of the second NMOS transistor 332; The falling delay module 322 is used to generate a time delay on the falling edge of the first control signal to obtain a third initial signal; The first level conversion module 324 is used to convert the power domain of the third initial signal to obtain the third control signal, wherein the third control signal is used to control the driving state of the third NMOS transistor 333; The rising delay module 323 is used to generate a time delay on the rising edge of the second control signal to obtain a fourth initial signal; The second level conversion module 325 is used to convert the power domain of the fourth initial signal to obtain the fourth control signal, wherein the fourth control signal is used to control the driving state of the first NMOS transistor 331.

[0052] Specifically, the falling delay module is used to generate a time delay on the falling edge of the first control signal, but not on the rising edge of the first control signal, and the signal obtained after processing is the third initial signal; the rising delay module is used to generate a time delay on the rising edge of the second control signal, but not on the falling edge of the second control signal, and the signal obtained after processing is the fourth initial signal.

[0053] In one feasible implementation plan, see Figure 12 As shown, Figure 12 The diagram shows a fifth type of device for accelerating NMOS transistor driving provided in Embodiment 1 of the present invention. The control module 3 further includes a constant current source 34. The input terminal of the constant current source 34 is connected to the output terminal of the boost module 2, and the output terminal of the constant current source 34 is connected to the gate of the target NMOS transistor. The constant current source 34 is used to provide pull-up current to the gate of the target NMOS transistor through its output terminal.

[0054] In one feasible implementation plan, see Figure 13 As shown, Figure 13 The diagram shows a sixth type of device for accelerating NMOS transistor driving provided in Embodiment 1 of the present invention. The timing switch module 33 includes at least one timing switch controller 336, at least one timing switch 337, and a second energy storage capacitor 338. Each output terminal of the timing signal generation module 32 is connected to a timing switch controller 336, and each timing switch controller 336 is connected to a timing switch 337. The at least one timing switch 337 and the second energy storage capacitor 338 form a charging / discharging circuit 339. The first input terminal of the charging / discharging circuit 339 is connected to the first output terminal of the power module 1, and the second input terminal of the charging / discharging circuit 339 is connected to the second output terminal of the power module 1. The first output terminal of the charging / discharging circuit 339 is connected to the gate of the target NMOS transistor, and the second output terminal of the charging / discharging circuit 339 is connected to the source of the target NMOS transistor. For each of the at least one timing switch controller 336, the timing switch controller 336 is used to control the timing switch 337 connected thereto to close or open according to the timing control signal; The charging and discharging circuit 339 is used to discharge the target NMOS transistor through the second energy storage capacitor 338 according to the open or closed state of each of the timing switches 337, so as to drive the target NMOS transistor.

[0055] In one feasible implementation plan, see Figure 14 As shown, Figure 14 The diagram shows a seventh type of device for accelerating NMOS transistor driving provided in Embodiment 1 of the present invention. The boost module 2 includes a charge pump booster 21. The input terminal of the charge pump booster 21 is connected to the first output terminal of the power supply module 1, and the output terminal of the charge pump booster 21 is connected to the first input terminal of the control module 3.

[0056] In one feasible implementation, the voltage difference between the power supply domain of the first initial current and the power supply domain of the second initial current ranges from [3,5].

[0057] The NMOS transistor driving device provided in this embodiment of the invention can be specific hardware on a device or software or firmware installed on the device. The implementation principle and technical effects of the device provided in this embodiment of the invention are the same as those in the foregoing method embodiments. For the sake of brevity, any parts not mentioned in the device embodiments can be referred to the corresponding content in the foregoing method embodiments. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can all be referred to the corresponding processes in the above method embodiments, and will not be repeated here.

[0058] In the embodiments provided by this invention, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0059] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0060] In addition, the functional units in the embodiments provided by the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0061] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0062] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0063] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. All should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A device for accelerating the drive of an NMOS transistor, characterized in that, The device includes a power supply module, a boost module, and a control module. The first output terminal of the power supply module is connected to the input terminal of the boost module, the output terminal of the boost module is connected to the first input terminal of the control module, the second output terminal of the power supply module is connected to the second input terminal of the control module, and the output terminal of the control module is connected to the gate of the target NMOS transistor. The power module is used to provide a first initial current to the input terminal of the boost module through the first output terminal of the power module, and is also used to provide a second initial current to the second input terminal of the control module through the second output terminal of the power module, wherein there is a voltage difference between the power domain of the first initial current and the power domain of the second initial current; The boost module is used to boost the first initial current to obtain a first target current, and output the first target current to the first input terminal of the control module through its output terminal; the control module is used to power the target NMOS transistor through its output terminal according to the second initial current and the first target current, so as to drive the target NMOS transistor; The control module includes an enable signal generation module, a timing signal generation module, and a timing switch module. The first input terminal of the enable signal generation module is connected to the output terminal of the boost module, the second input terminal of the enable signal generation module is connected to the second output terminal of the power supply module, the output terminal of the enable signal generation module is connected to the input terminal of the timing signal generation module, the output terminal of the timing signal generation module is connected to the input terminal of the timing switch module, and the output terminal of the timing switch module is connected to the gate of the target NMOS transistor. The timing switch module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a first energy storage capacitor. The first output terminal of the timing signal generation module is connected to the gate of the first NMOS transistor, the second output terminal of the timing signal generation module is connected to the gate of the second NMOS transistor, the third output terminal of the timing signal generation module is connected to the gate of the third NMOS transistor, and the fourth output terminal of the timing signal generation module is connected to the gate of the first PMOS transistor. The sources of the first NMOS transistor and the first PMOS transistor are both connected to the first output terminal of the power supply module. The drain of the first NMOS transistor is connected to the upper plate of the first energy storage capacitor and the source of the third NMOS transistor, respectively. The drain of the third NMOS transistor is connected to the gate of the target NMOS transistor. The drain of the first PMOS transistor is connected to the lower plate of the first energy storage capacitor and the drain of the second NMOS transistor, respectively. The source of the second NMOS transistor is connected to the second output terminal of the power supply module.

2. The apparatus according to claim 1, characterized in that, The enable signal generation module is used to generate an enable signal based on the second initial current and the first target current, and is also used to output the enable signal to the first input terminal of the timing signal generation module through the output terminal of the enable signal generation module. The timing signal generation module is used to generate a timing control signal according to the enable signal, and is also used to output the timing control signal to the input terminal of the timing switch module through the output terminal of the timing signal generation module. The timing switch module is used to drive the target NMOS transistor according to the timing control signal.

3. The apparatus according to claim 2, characterized in that, The timing signal generation module includes a non-overlapping clock generation module, a falling delay module, a rising delay module, a first level conversion module, and a second level conversion module. The timing control signal includes a first control signal, a second control signal, a third control signal, and a fourth control signal. The input terminal of the non-overlapping clock generation module is connected to the output terminal of the enable signal generation module. The first output terminal of the non-overlapping clock generation module is connected to the gate of the first PMOS transistor and the input terminal of the fall delay module. The second output terminal of the non-overlapping clock generation module is connected to the gate of the second NMOS transistor and the input terminal of the rise delay module. The output terminal of the fall delay module is connected to the input terminal of the first level conversion module. The output terminal of the rise delay module is connected to the input terminal of the second level conversion module. The output terminal of the first level conversion module is connected to the gate of the third NMOS transistor, and the output terminal of the second level conversion module is connected to the gate of the first NMOS transistor.

4. The apparatus according to claim 3, characterized in that, The non-overlapping clock generation module is used to generate the first control signal and the second control signal according to the enable signal, and is also used to send the first control signal to the gate of the first PMOS transistor and the input of the fall delay module through the first output terminal of the non-overlapping clock generation module, and to send the second control signal to the gate of the second NMOS transistor and the input of the rise delay module through the second output terminal of the non-overlapping clock generation module, wherein the first control signal is used to control the driving state of the first PMOS transistor, and the second control signal is used to control the driving state of the second NMOS transistor; The falling delay module is used to generate a time delay on the falling edge of the first control signal to obtain a third initial signal; The first level conversion module is used to convert the power domain of the third initial signal to obtain the third control signal, wherein the third control signal is used to control the driving state of the third NMOS transistor; The rising delay module is used to generate a time delay on the rising edge of the second control signal to obtain a fourth initial signal; The second level conversion module is used to convert the power domain of the fourth initial signal to obtain the fourth control signal, wherein the fourth control signal is used to control the driving state of the first NMOS transistor.

5. The apparatus according to claim 1, characterized in that, The control module further includes a constant current source, the input terminal of which is connected to the output terminal of the boost module, and the output terminal of which is connected to the gate of the target NMOS transistor. The constant current source is used to provide pull-up current to the gate of the target NMOS transistor through its output terminal.

6. The apparatus according to claim 2, characterized in that, The timing switch module includes at least one timing switch controller, at least one timing switch, and a second energy storage capacitor. Each output terminal of the timing signal generation module is connected to a timing switch controller, and each timing switch controller is connected to a timing switch. The at least one timing switch and the second energy storage capacitor form a charging and discharging circuit. The first input terminal of the charging and discharging circuit is connected to the first output terminal of the power module, the second input terminal of the charging and discharging circuit is connected to the second output terminal of the power module, the first output terminal of the charging and discharging circuit is connected to the gate of the target NMOS transistor, and the second output terminal of the charging and discharging circuit is connected to the source of the target NMOS transistor. For each of the at least one timing switch controller, the timing switch controller is used to control the timing switch connected to it to close or open according to the timing control signal; The charging and discharging circuit is used to discharge to the target NMOS transistor through the second energy storage capacitor according to the open or closed state of each of the timing switches, so as to drive the target NMOS transistor.

7. The apparatus according to claim 1, characterized in that, The boost module includes a charge pump booster, the input terminal of which is connected to the first output terminal of the power module, and the output terminal of which is connected to the first input terminal of the control module.

8. The apparatus according to claim 1, characterized in that, The voltage difference between the power source domain of the first initial current and the power source domain of the second initial current ranges from [3, 5].

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