Control circuit and control method of fully differential capacitor feedback amplifier

Abstract

This invention discloses a control circuit and control method for a fully differential capacitor feedback amplifier. The control circuit includes: a controllable impedance pseudo-resistor comprising multiple MOSFETs, each MOSFET's gate interconnected with a source follower and a current source bias circuit for controlling the pseudo-resistance's charging; one end of the source follower is connected to the output of the current source bias circuit and the gate of the controllable impedance pseudo-resistance, with the source follower's gate connected to a reference potential; the other end of the source follower is connected to a gate control circuit for controlling the gate of the controllable impedance pseudo-resistance, causing the pseudo-resistance to enter the weak inversion region; the source or drain of the controllable impedance pseudo-resistance is connected to a capacitor-coupled amplifier. The solution provided by this invention can achieve the technical effects of shortening the input steady-state time and overall startup time of a low-noise, feedback-resistance-free fully differential capacitor feedback amplifier.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology applications, and in particular to a control circuit and control method for a fully differential capacitor feedback amplifier. Background Technology

[0002] Figure 1 This is a schematic diagram of a low-noise, feedback-free, capacitor-feedback fully differential amplifier in the prior art; such as... Figure 1 As shown, a feedback-free, low-noise, capacitor-feedback fully differential amplifier in the prior art includes: capacitors C1 and C2, an operational transconductance amplifier (OTA), and a bias resistor R2, based on... Figure 1 The structure of a low-noise, feedback-free, capacitor-feedback fully differential amplifier uses a pseudo-resistor structure to achieve high impedance. This pseudo-resistor structure has extremely high impedance, which results in a long input steady-state time. In applications requiring fast response, feedback-free capacitor-feedback has an inherent limitation: it requires a longer startup time, thus failing to meet the needs of fast-response applications.

[0003] There is currently no effective solution to the problem of long startup time caused by the excessively long input steady-state time in existing low-noise, feedback-resistor-free, fully differential capacitor feedback amplifiers. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention aims to provide a control circuit and control method for a fully differential capacitor feedback amplifier, thereby at least solving the problem of long startup time caused by the excessively long input steady-state time in existing low-noise, feedback-resistor-free fully differential capacitor feedback amplifiers.

[0005] The technical solution of this invention is implemented as follows:

[0006] In a first aspect, embodiments of the present invention provide a control circuit for a fully differential capacitor feedback amplifier, comprising: a capacitor-coupled amplifier, a controllable impedance pseudo-resistor, a source follower, a current source bias circuit, and a gate control circuit. The controllable impedance pseudo-resistor includes multiple MOS transistors, each with its gate interconnected with the source follower and the current source bias circuit for controlling the pseudo-resistance to charge. One end of the source follower is connected to the output of the current source bias circuit and the gate of the controllable impedance pseudo-resistor, respectively. The gate of the source follower is connected to a reference potential. The other end of the source follower is connected to the gate control circuit for controlling the gate of the controllable impedance pseudo-resistor, causing the controllable impedance pseudo-resistance to enter the weak inversion region. The source or drain of the controllable impedance pseudo-resistor is connected to the capacitor-coupled amplifier.

[0007] Optionally, the controllable impedance pseudo-resistor includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, and an eighth MOSFET. When the controllable impedance pseudo-resistor is a PMOS transistor, the gates of the first MOSFET, second MOSFET, third MOSFET, fourth MOSFET, fifth MOSFET, sixth MOSFET, seventh MOSFET, and eighth MOSFET are interconnected; the source of the first MOSFET is connected to the drain of the second MOSFET and connected to a reference potential; the drain of the first MOSFET is connected to the source of the third MOSFET, and the source of the second MOSFET is connected to the drain of the fourth MOSFET; the drain of the third MOSFET and the source of the fourth MOSFET are connected to a capacitively coupled amplifier; the drain of the fifth MOSFET and the source of the sixth MOSFET are connected to a capacitively coupled amplifier; the source of the fifth MOSFET and the drain of the seventh MOSFET are connected, and the drain of the sixth MOSFET and the source of the eighth MOSFET are connected and connected to a reference potential.

[0008] Further, optionally, when the controllable impedance pseudo-resistor is an NMOS transistor, the source of the first MOS transistor and the drain of the second MOS transistor are connected to a reference potential; the drain of the first MOS transistor and the source of the third MOS transistor are connected; the drain of the third MOS transistor is connected to the first terminal of the transconductance amplifier in the capacitively coupled amplifier; the source of the second MOS transistor and the drain of the fourth MOS transistor are connected; the source of the fourth MOS transistor is connected to the first terminal of the transconductance amplifier in the capacitively coupled amplifier; the source of the fifth MOS transistor is connected to the second terminal of the transconductance amplifier in the capacitively coupled amplifier; the drain of the fifth MOS transistor and the source of the seventh MOS transistor are connected to a reference potential; the drain of the eighth MOS transistor and the source of the sixth MOS transistor are connected; the drain of the sixth MOS transistor is connected to the second terminal of the transconductance amplifier in the capacitively coupled amplifier.

[0009] Optionally, the gate control circuit includes: a first voltage source, a second voltage source, and a ninth MOS transistor, wherein, when the source follower is an NMOS transistor, the first voltage source is connected to the gate of the ninth MOS transistor, the second voltage source is connected to the source of the ninth MOS transistor, and the drain of the ninth MOS transistor is connected to the drain of the source follower.

[0010] Furthermore, optionally, when the source follower is a PMOS transistor, the drain of the source follower is connected to the drain of the ninth MOS transistor, the gate of the ninth MOS transistor is connected to the first voltage source, the source of the ninth MOS transistor is grounded, and the source of the source follower is connected to the gate of the controllable impedance pseudo-resistor.

[0011] Optionally, the current source bias circuit includes: a current source, a tenth MOSFET, and an eleventh MOSFET. When the source follower is an NMOS transistor, the output of the current source is connected to the drain, gate, and gate of the tenth MOSFET, the gate of the tenth MOSFET is connected to the gate of the eleventh MOSFET, the source of the tenth MOSFET and the source of the eleventh MOSFET are grounded, and the drain of the eleventh MOSFET is connected to the source of the source follower.

[0012] Furthermore, optionally, when the source follower is a PMOS transistor, in the current source bias circuit, the source of the tenth MOS transistor is connected to the second voltage source, the drain and gate of the tenth MOS transistor are connected to the current source, the gate of the tenth MOS transistor is connected to the gate of the eleventh MOS transistor, the source of the eleventh MOS transistor is connected to the second voltage source, the drain of the eleventh MOS transistor is connected to the source of the source follower, and the gate of the source follower is connected to the reference potential.

[0013] Optionally, the capacitively coupled amplifier includes: a first input voltage, a second input voltage, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a transconductance amplifier. When the controllable impedance pseudo-resistance is a PMOS transistor, one end of the first capacitor is connected to the first input voltage, and the other end of the first capacitor is connected to one end of the third capacitor and connected to the first terminal of the transconductance amplifier. The other end of the third capacitor is connected to the fourth terminal of the transconductance amplifier. One end of the second capacitor is connected to the second input voltage, and the other end of the second capacitor is connected to one end of the fourth capacitor and connected to the second terminal of the transconductance amplifier. The other end of the fourth capacitor is connected to the third terminal of the transconductance amplifier. The first terminal of the transconductance amplifier is also connected to the drain of the third MOS transistor and the source of the fourth MOS transistor. The second terminal of the transconductance amplifier is also connected to the drain of the fifth MOS transistor and the source of the sixth MOS transistor.

[0014] Further, optionally, when the controllable impedance pseudo-resistance is an NMOS transistor, the drain of the third MOS transistor is connected to the first terminal of the transconductance amplifier, the source of the fourth MOS transistor is connected to the first terminal of the transconductance amplifier, the source of the fifth MOS transistor is connected to the second terminal of the transconductance amplifier, and the drain of the sixth MOS transistor is connected to the second terminal of the transconductance amplifier; the first capacitor is connected to the first input voltage, the other end of the first capacitor and one end of the third capacitor are connected to the first terminal of the transconductance amplifier, the other end of the third capacitor is connected to the fourth terminal of the transconductance amplifier, the second capacitor is connected to the second input voltage, the other end of the second capacitor and one end of the fourth capacitor are connected to the second terminal of the transconductance amplifier, and the other end of the fourth capacitor is connected to the third terminal of the transconductance amplifier.

[0015] Optionally, the reference voltage of the reference potential is generated by a reference potential generator or obtained by resistor voltage division.

[0016] Secondly, embodiments of the present invention provide a control method for a control circuit of a fully differential capacitor feedback amplifier, applied to the control circuit of the aforementioned fully differential capacitor feedback amplifier, comprising: controlling the gate of a controllable impedance pseudo-resistor through a source follower, and controlling the source voltage of the source follower through a current source bias circuit and a reference potential; controlling the charging of the controllable impedance pseudo-resistor according to the source voltage of the controllable source follower; wherein, the controllable impedance pseudo-resistor is used to control the weak inversion region; the controllable impedance pseudo-resistor is a linear resistor, and the linear resistor is used to change the resistance value by arbitrarily adding or removing MOS transistors in series.

[0017] This invention provides a control circuit and method for a fully differential capacitor feedback amplifier. The controllable impedance pseudo-resistor includes multiple MOSFETs, each with its gate interconnected with a source follower and a current source bias circuit to control the pseudo-resistance's charging. One end of the source follower is connected to the output of the current source bias circuit and the gate of the controllable impedance pseudo-resistor, respectively. The gate of the source follower is connected to a reference potential, and the other end is connected to a gate control circuit to control the gate of the controllable impedance pseudo-resistance, causing it to enter the weak inversion region. The source or drain of the controllable impedance pseudo-resistance is connected to a capacitively coupled amplifier, thereby achieving the technical effects of shortening the input steady-state time and overall startup time of the low-noise, feedback-resistance-free fully differential capacitor feedback amplifier. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0019] Figure 1 This is a schematic diagram of a capacitor-feedback fully differential amplifier with no feedback and low noise in the prior art.

[0020] Figure 2 This is a schematic diagram of the control circuit of a fully differential capacitor feedback amplifier provided in Embodiment 1 of the present invention;

[0021] Figure 3 This is a schematic diagram of a control circuit for a fully differential capacitor feedback amplifier provided in Embodiment 1 of the present invention, in which the controllable impedance pseudo-resistor is an NMOS transistor and the source follower is a PMOS transistor.

[0022] Figure 4 This is a simulation diagram of the control circuit of a fully differential capacitor feedback amplifier provided in Embodiment 1 of the present invention before the improvement of the scheme;

[0023] Figure 5 This is a simulation diagram of the improved control circuit scheme of a fully differential capacitor feedback amplifier provided in Embodiment 1 of the present invention;

[0024] Figure 6 This is a flowchart illustrating the control method of a control circuit for a fully differential capacitor feedback amplifier provided in Embodiment 2 of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish different objects, rather than to limit a specific order.

[0027] It should also be noted that the various embodiments of the present invention described below can be executed individually or in combination with each other, and the embodiments of the present invention do not impose specific limitations in this regard.

[0028] Example 1

[0029] In a first aspect, embodiments of the present invention provide a control circuit for a fully differential capacitor feedback amplifier. Figure 2 This is a schematic diagram of the control circuit of a fully differential capacitor feedback amplifier provided in Embodiment 1 of the present invention; as shown. Figure 2 As shown, the control circuit of the fully differential capacitor feedback amplifier in this embodiment includes:

[0030] The system comprises a capacitively coupled amplifier, a controllable impedance pseudo-resistor, a source follower, a current source bias circuit, and a gate control circuit. The controllable impedance pseudo-resistor includes multiple MOSFETs, each with its gate interconnected with the source follower and the current source bias circuit to control the charging of the pseudo-resistor. One end of the source follower is connected to the output of the current source bias circuit and the gate of the controllable impedance pseudo-resistor, with its gate connected to a reference potential. The other end of the source follower is connected to the gate control circuit to control the gate of the controllable impedance pseudo-resistor, causing it to enter the weak inversion region. The source or drain of the controllable impedance pseudo-resistor is connected to the capacitively coupled amplifier.

[0031] Optionally, the controllable impedance pseudo-resistor includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, and an eighth MOSFET. When the controllable impedance pseudo-resistor is a PMOS transistor, the gates of the first MOSFET, second MOSFET, third MOSFET, fourth MOSFET, fifth MOSFET, sixth MOSFET, seventh MOSFET, and eighth MOSFET are interconnected; the source of the first MOSFET is connected to the drain of the second MOSFET and connected to a reference potential; the drain of the first MOSFET is connected to the source of the third MOSFET, and the source of the second MOSFET is connected to the drain of the fourth MOSFET; the drain of the third MOSFET and the source of the fourth MOSFET are connected to a capacitively coupled amplifier; the drain of the fifth MOSFET and the source of the sixth MOSFET are connected to a capacitively coupled amplifier; the source of the fifth MOSFET and the drain of the seventh MOSFET are connected, and the drain of the sixth MOSFET and the source of the eighth MOSFET are connected and connected to a reference potential.

[0032] Specifically, such as Figure 2 As shown, when the MOS transistor in the controllable impedance pseudo resistor is a PMOS transistor, the controllable impedance pseudo resistor in this embodiment of the application is composed of a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor. The first MOS transistor is denoted as M5, the second MOS transistor as M9, the third MOS transistor as M6, the fourth MOS transistor as M10, the fifth MOS transistor as M7, the sixth MOS transistor as M11, the seventh MOS transistor as M8, the eighth MOS transistor as M12, and the reference potential is denoted as REF.

[0033] like Figure 2 As shown, the gates of M5, M9, M6, M10, M7, M11, M8, and M12 are interconnected and connected to the source of the source follower (denoted as M2). The source of M5 is connected to the drain of M9 and connected to the reference potential. The source of M6 is connected to the drain of M5, and the drain of M6 is connected to the capacitively coupled amplifier. The source of M9 is connected to the drain of M10, and the source of M10 is connected to the capacitively coupled amplifier. The drain of M7 is connected to the capacitively coupled amplifier, and the source of M7 is connected to the drain of M8. The source of M8 is connected to the drain of M12 and connected to the reference potential. The source of M12 is connected to the drain of M11, and the source of M11 is connected to the capacitively coupled amplifier.

[0034] Optionally, the gate control circuit includes: a first voltage source, a second voltage source, and a ninth MOS transistor, wherein, when the source follower is an NMOS transistor, the first voltage source is connected to the gate of the ninth MOS transistor, the second voltage source is connected to the source of the ninth MOS transistor, and the drain of the ninth MOS transistor is connected to the drain of the source follower.

[0035] Specifically, such as Figure 2 As shown, the first voltage source is denoted as VC, the second voltage source as VDD, and the ninth MOSFET as M1. VC is connected to the gate of M1, VDD is connected to the source of M1, and the drain of M1 is connected to the drain of the source follower (denoted as M2).

[0036] Specifically, such as Figure 2 As shown, the source follower is denoted as M2.

[0037] Optionally, the current source bias circuit includes: a current source, a tenth MOSFET, and an eleventh MOSFET. When the source follower is an NMOS transistor, the output of the current source is connected to the drain, gate, and gate of the tenth MOSFET, the gate of the tenth MOSFET is connected to the gate of the eleventh MOSFET, the source of the tenth MOSFET and the source of the eleventh MOSFET are grounded, and the drain of the eleventh MOSFET is connected to the source of the source follower.

[0038] Specifically, such as Figure 2 As shown, in this embodiment of the application, the current source bias circuit consists of a current source, a tenth MOSFET, and an eleventh MOSFET. The current source is denoted as I1, the tenth MOSFET is denoted as M4, and the eleventh MOSFET is denoted as M3. The output terminal of I1 is connected to the drain and gate of M4, the source of M4 is grounded, the gate of M4 is connected to the gate of M3, the source of M3 is grounded, the drain of M3 is connected to the source of M2, and is connected to the gate of the MOSFET in the controllable impedance pseudo-resistor.

[0039] Optionally, the capacitively coupled amplifier includes: a first input voltage, a second input voltage, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a transconductance amplifier. When the controllable impedance pseudo-resistance is a PMOS transistor, one end of the first capacitor is connected to the first input voltage, and the other end of the first capacitor is connected to one end of the third capacitor and connected to the first terminal of the transconductance amplifier. The other end of the third capacitor is connected to the fourth terminal of the transconductance amplifier. One end of the second capacitor is connected to the second input voltage, and the other end of the second capacitor is connected to one end of the fourth capacitor and connected to the second terminal of the transconductance amplifier. The other end of the fourth capacitor is connected to the third terminal of the transconductance amplifier. The first terminal of the transconductance amplifier is also connected to the drain of the third MOS transistor and the source of the fourth MOS transistor. The second terminal of the transconductance amplifier is also connected to the drain of the fifth MOS transistor and the source of the sixth MOS transistor.

[0040] Specifically, such as Figure 2As shown in the embodiment of this application, the first input voltage is denoted as VIP, the second input voltage is denoted as VIN, the first capacitor is denoted as C2, the second capacitor is denoted as C1, the third capacitor is denoted as C3, the fourth capacitor is denoted as C4, and the transconductance amplifier is denoted as OTA. Among them, C2 is connected to VIP, the drain of M6 and the source of M10, together with C2 and C3, are connected to the first terminal of OTA, the other end of C3 is connected to the fourth terminal of OTA, C1 is connected to VIN, C1 and the drain of M7 and the source of M11, and C4 is connected to the second terminal of OTA, and the other end of C4 is connected to the third terminal of OTA.

[0041] Optionally, the reference voltage of the reference potential is generated by a reference potential generator or obtained by resistor voltage division.

[0042] The reference voltage is usually generated by a reference potential generator, such as a BANDGAP circuit, or by a fixed resistor voltage divider, as long as it is a stable and reliable reference source.

[0043] It should be noted that the above examples in the control circuit of the fully differential capacitor feedback amplifier provided in the embodiments of this application are only optimal examples shown, and are intended to implement the control circuit of the fully differential capacitor feedback amplifier provided in the embodiments of this application. No specific limitations are made.

[0044] Specifically, such as Figure 2 As shown, in the control circuit of the fully differential capacitor feedback amplifier provided in this application embodiment, the gates of the controllable impedance pseudo resistors (M5-M12) are connected together to control the pseudo impedance, thereby achieving the purpose of fast charging.

[0045] To control the gate of the controllable impedance pseudo-resistors (M5-M12), an N-type input-source follower (M2) is added, along with a gate control circuit (M1) to pull the controllable impedance pseudo-resistors (M5-M12) low. Initially, VC is controlled to a high level, making M1 the cut-off region. Therefore, VG will naturally discharge to zero, and the controllable impedance pseudo-resistors (M5-M12) operate in the triode region during the initial working phase. After the initial rapid discharge, VC is controlled to a low level, allowing M1 to enter the triode region. In this source follower (M2), the gate is connected to the reference potential. Therefore, the DC level of the source of M2 will be the reference voltage level minus VGS (the potential difference between the gate and the source). The VG level is determined by the magnitude of the I1 current and the aspect ratio of M2-M4. This allows for simple control of the source voltage of the N-type input source follower, enabling the controllable impedance pseudo-resistors (M5-M12) to enter the weak inversion region to achieve a fast charging scheme.

[0046] The process of controlling the controllable impedance pseudo resistors (M5-M12) in the control circuit of the fully differential capacitor feedback amplifier provided in this application embodiment is as follows:

[0047] like Figure 2 As shown, in the initial stage, the control circuit of the fully differential capacitor feedback amplifier provided in this application embodiment is as follows: the source follower (M2) is in the off stage (VC=VDD), VG=0, the gate PMOS (M5-M12) with controllable impedance pseudo-resistance is VGS>|VTP|, |VDS|<|VGS|-|VT|, the controllable impedance pseudo-resistance PMOS works in the triode region, and its impedance is smaller than that of the cut-off resistor, so the charging speed is fast.

[0048] The control circuit of the fully differential capacitor feedback amplifier provided in this application embodiment is in the source follower (M2) turn-on stage (VC=0, the output of the source follower is VG=REF-VGS). The N-type source follower output voltage is (pseudo-resistance gate voltage level) REF-VGS, and the controllable impedance pseudo-resistance PMOS (M5-M12) VGS<|VTP|, which is in the weak inversion region and has a large impedance.

[0049] also, Figure 3 This is a schematic diagram of a control circuit for a fully differential capacitor feedback amplifier provided in Embodiment 1 of the present invention, in which the controllable impedance pseudo-resistor is an NMOS transistor and the source follower is a PMOS transistor; as shown... Figure 3 As shown, different from Figure 2 The control circuit of the fully differential capacitor feedback amplifier shown is configured with an NMOS transistor as the controllable impedance pseudo-resistor and a PMOS transistor as the source follower:

[0050] Optionally, when the controllable impedance pseudo-resistor is an NMOS transistor, the source of the first MOS transistor and the drain of the second MOS transistor are connected to a reference potential. The drain of the first MOS transistor and the source of the third MOS transistor are connected. The drain of the third MOS transistor is connected to the first terminal of the transconductance amplifier in the capacitively coupled amplifier. The source of the second MOS transistor and the drain of the fourth MOS transistor are connected. The source of the fourth MOS transistor is connected to the first terminal of the transconductance amplifier in the capacitively coupled amplifier. The source of the fifth MOS transistor is connected to the second terminal of the transconductance amplifier in the capacitively coupled amplifier. The drain of the fifth MOS transistor and the source of the seventh MOS transistor are connected to a reference potential. The drain of the eighth MOS transistor and the source of the sixth MOS transistor are connected. The drain of the sixth MOS transistor is connected to the second terminal of the transconductance amplifier in the capacitively coupled amplifier.

[0051] Optionally, when the source follower is a PMOS transistor, the drain of the source follower is connected to the drain of the ninth MOS transistor, the gate of the ninth MOS transistor is connected to the first voltage source, the source of the ninth MOS transistor is grounded, and the source of the source follower is connected to the gate of the controllable impedance pseudo-resistor.

[0052] Optionally, when the source follower is a PMOS transistor, in the current source bias circuit, the source of the tenth MOS transistor is connected to the second voltage source, the drain and gate of the tenth MOS transistor are connected to the current source, the gate of the tenth MOS transistor is connected to the gate of the eleventh MOS transistor, the source of the eleventh MOS transistor is connected to the second voltage source, the drain of the eleventh MOS transistor is connected to the source of the source follower, and the gate of the source follower is connected to the reference potential.

[0053] Optionally, when the controllable impedance pseudo-resistor is an NMOS transistor, the drain of the third MOS transistor is connected to the first terminal of the transconductance amplifier, the source of the fourth MOS transistor is connected to the first terminal of the transconductance amplifier, the source of the fifth MOS transistor is connected to the second terminal of the transconductance amplifier, and the drain of the sixth MOS transistor is connected to the second terminal of the transconductance amplifier; the first capacitor is connected to the first input voltage, the other end of the first capacitor and one end of the third capacitor are connected to the first terminal of the transconductance amplifier, the other end of the third capacitor is connected to the fourth terminal of the transconductance amplifier, the second capacitor is connected to the second input voltage, the other end of the second capacitor and one end of the fourth capacitor are connected to the second terminal of the transconductance amplifier, and the other end of the fourth capacitor is connected to the third terminal of the transconductance amplifier.

[0054] like Figure 3 As shown, in the current source bias circuit, the source of M4 is connected to VDD, the drain and gate of M4 are connected to current source I1, the gate of M4 is connected to the gate of M3, the source of M3 is connected to VDD, the drain of M3 is connected to the source of M2, the gate of M2 is connected to REF, the drain of M2 is connected to the drain of M1, the gate of M1 is connected to VC, the source of M1 is grounded, the source of M2 is connected to the gate of the controllable impedance pseudo-resistors (M5-M12), in the controllable impedance pseudo-resistors (M5-M12), the source of M5 is connected to the drain of M9 and connected to REF, the drain of M5 is connected to the source of M6, and the drain of M6 is connected to OTA. The first terminal of the OTA is connected to the source of M9 and the drain of M10. The source of M10 is connected to the first terminal of the OTA. The source of M7 is connected to the second terminal of the OTA. The drain of M7 is connected to the source of M8. The drain of M8 is connected to the source of M12 and connected to REF. The drain of M12 is connected to the source of M11. The drain of M11 is connected to the second terminal of the OTA. C2 is connected to VIP. The other end of C2 and one end of C3 are connected to the first terminal of the OTA. The other end of C3 is connected to the fourth terminal of the OTA. C1 is connected to VIN. The other end of C1 and one end of C4 are connected to the second terminal of the OTA. The other end of C4 is connected to the third terminal of the OTA.

[0055] Based on the above, the simulation results of the control circuit of the fully differential capacitor feedback amplifier provided in the embodiments of this application are as follows: Figure 4 As shown, Figure 4 This is a simulation diagram of the control circuit of a fully differential capacitor feedback amplifier provided in Embodiment 1 of the present invention before the improvement scheme; before the improvement scheme was added, the settling time was 0.4s; Figure 5 This is a simulation diagram illustrating the improved control circuit design of a fully differential capacitor feedback amplifier according to Embodiment 1 of the present invention; as shown below. Figure 5 As shown, after adding the improvement scheme, the stabilization time is 500us, which greatly improves the problem of slow charging.

[0056] This invention provides a control circuit for a fully differential capacitor feedback amplifier. The controllable impedance pseudo-resistor includes multiple MOSFETs, with the gates of each MOSFET interconnected and connected to a source follower and a current source.

[0057] A bias circuit is used to control the charging of the pseudo-impedance. One end of the source follower is connected to the output of the current source bias circuit and the gate of the controllable impedance pseudo-resistor. The gate of the source follower is connected to the reference potential. The other end of the source follower is connected to the gate control circuit to control the gate of the controllable impedance pseudo-resistance so that the controllable impedance pseudo-resistance enters the weak inversion region. The source or drain of the controllable impedance pseudo-resistance is connected to the capacitor-coupled amplifier, thereby achieving the technical effect of shortening the input steady-state time of the low-noise, feedback-free, fully differential capacitor feedback amplifier and shortening the overall startup time.

[0058] Example 2

[0059] Secondly, embodiments of the present invention provide a control method for a control circuit of a fully differential capacitor feedback amplifier, applied to the control circuit of the aforementioned fully differential capacitor feedback amplifier. Figure 6 This is a flowchart illustrating the control method of a control circuit for a fully differential capacitor feedback amplifier provided in Embodiment 2 of the present invention; as shown.

[0060] Figure 6 As shown, the control method 5 of the control circuit of the fully differential capacitor feedback amplifier provided in this application embodiment includes:

[0061] Step S602: The gate of the controllable impedance pseudo-resistor is controlled by the source follower, and the source voltage of the source follower is controlled by the current source bias circuit and the reference potential.

[0062] Step S604: The controllable impedance pseudo-resistance is charged according to the source voltage of the controllable source follower;

[0063] In the middle, the controllable impedance pseudo-resistor is used to control the weak inversion region; the controllable impedance pseudo-resistor is a linear resistor, and the linear 0 resistor is used to change the resistance value by arbitrarily adding or removing MOSFETs in series.

[0064] Specifically, the control method of the control circuit of the fully differential capacitor feedback amplifier provided in this application embodiment is applied to the control circuit of the fully differential capacitor feedback amplifier in Embodiment 1, such as... Figure 2 As shown in Figure 3, the gates of the controllable impedance pseudo-resistors (M5-M12) are connected together to control the pseudo-impedance, thereby achieving the purpose of fast charging.

[0065] 5. In order to control the gate of the controllable impedance pseudo-resistors (M5-M12), an N-type input source follower is added.

[0066] The circuit (M1) is equipped with a gate control circuit (M1) that pulls down the controllable impedance pseudo-resistors (M5-M12). In the initial state, VC is controlled to a high level, making M1 the cut-off region. Therefore, VG will naturally discharge to zero level. The controllable impedance pseudo-resistors (M5-M12) work in the triode region during the initial working stage. After the initial fast discharge, VC is controlled to a low level, making M1 enter the triode region. The gate of this source follower (M2) is connected to the reference potential. Therefore, the DC level of the source of M2 will be the reference voltage level minus VGS (the potential difference between the gate and the source). The VG level is determined by the magnitude of the I1 current and the aspect ratio of M2-M4. Thus, it is very simple to control the source voltage of the N-type input source follower, so that the controllable impedance pseudo-resistors (M5-M12) enter the weak inversion region to achieve a fast charging scheme.

[0067] The process of controlling the controllable impedance pseudo resistors (M5-M12) in the control circuit of the fully differential capacitor feedback amplifier provided in this application embodiment is as follows:

[0068] like Figure 2 As shown in Figure 3, in the initial stage, the control circuit of the fully differential capacitor feedback amplifier provided in this application embodiment is as follows: the source follower (M2) is in the off stage (VC = VDD), VG = 0, the gate PMOS (M5-M12) with controllable impedance pseudo-resistance is VGS > |VTP|, |VDS| < |VGS| - |VT|, the controllable impedance pseudo-resistance PMOS works in the triode region, and its impedance is smaller than that of the cut-off resistor, thus the charging speed is fast.

[0069] The control circuit of the fully differential capacitor feedback amplifier provided in this application embodiment is in the source follower (M2) turn-on stage (VC=0, the output of the source follower is VG=REF-VGS). The N-type source follower output voltage is (pseudo-resistance gate voltage level) REF-VGS, and the controllable impedance pseudo-resistance PMOS (M5-M12) VGS<|VTP|, which is in the weak inversion region and has a large impedance.

[0070] This invention provides a control method for a control circuit of a fully differential capacitor feedback amplifier. Based on the control circuit of the fully differential capacitor feedback amplifier, the gate of a controllable impedance pseudo-resistor is controlled by a source follower, and the source voltage of the source follower is controlled by a current source bias circuit and a reference potential. The charging of the controllable impedance pseudo-resistor is controlled according to the source voltage of the source follower, thereby achieving the technical effect of shortening the input steady-state time and overall startup time of the low-noise, feedback-resistance-free fully differential capacitor feedback amplifier.

[0071] This invention provides a control circuit for a fully differential capacitor feedback amplifier. In a current source bias circuit including a current source and a first MOSFET, and a controllable impedance pseudo-resistor including a second MOSFET, the output of the current source is connected to the gate and drain of the first MOSFET, the gate of the first MOSFET is connected to the gate of the second MOSFET, and the source of the first MOSFET is connected to the source of the second MOSFET. The drain of the second MOSFET is connected to a capacitively coupled amplifier, used to adjust the second MOSFET's position according to the aspect ratio of the first and second MOSFETs, so that the second MOSFET enters the weak inversion region. This achieves the technical effect of shortening the input steady-state time and overall startup time of the low-noise, feedback-resistance-free fully differential capacitor feedback amplifier.

[0072] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0073] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0074] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A control circuit for a fully differential capacitor feedback amplifier, characterized in that, include: The circuit includes a capacitively coupled amplifier, a controllable impedance pseudo-resistor, a source follower, a current source bias circuit, and a gate control circuit. The controllable impedance pseudo-resistor includes multiple MOS transistors, and the gates of each MOS transistor are interconnected with the source follower and the current source bias circuit to control the charging of the controllable impedance pseudo-resistor. One end of the source follower is connected to the output of the current source bias circuit and the gate of the controllable impedance pseudo resistor, respectively. The gate of the source follower is connected to the reference potential. The other end of the source follower is connected to the gate control circuit to control the gate of the controllable impedance pseudo resistor so that the controllable impedance pseudo resistor enters the weak reversal region. The source or drain of the controllable impedance pseudo-resistor is connected to the capacitively coupled amplifier. The controllable impedance pseudo-resistor includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, and an eighth MOSFET, wherein, When the controllable impedance pseudo-resistor is a PMOS transistor, the gates of the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are interconnected; The source of the first MOSFET is connected to the drain of the second MOSFET and connected to the reference potential; the drain of the first MOSFET is connected to the source of the third MOSFET, and the source of the second MOSFET is connected to the drain of the fourth MOSFET. The drain of the third MOS transistor and the source of the fourth MOS transistor are connected to the first terminal of the capacitively coupled amplifier. The drain of the fifth MOS transistor and the source of the sixth MOS transistor are connected to the second terminal of the capacitively coupled amplifier; the source of the fifth MOS transistor and the drain of the seventh MOS transistor are connected, the source of the seventh MOS transistor is connected to the drain of the eighth MOS transistor and connected to the reference potential, and the drain of the sixth MOS transistor is connected to the source of the eighth MOS transistor. When the controllable impedance pseudo-resistor is an NMOS transistor, the source of the first MOS transistor and the drain of the second MOS transistor are connected to the reference potential. The drain of the first MOS transistor and the source of the third MOS transistor are connected, and the drain of the third MOS transistor is connected to the first terminal of the transconductance amplifier in the capacitively coupled amplifier. The source of the second MOS transistor and the drain of the fourth MOS transistor are connected, and the source of the fourth MOS transistor is connected to the first terminal of the transconductance amplifier in the capacitively coupled amplifier. The source of the fifth MOS transistor is connected to the second terminal of the transconductance amplifier in the capacitively coupled amplifier. The drain of the fifth MOS transistor and the source of the seventh MOS transistor are connected to the reference potential. The drain of the eighth MOS transistor and the source of the sixth MOS transistor are connected, and the drain of the sixth MOS transistor is connected to the second terminal of the transconductance amplifier in the capacitively coupled amplifier.

2. The control circuit of the fully differential capacitor feedback amplifier according to claim 1, characterized in that, The gate control circuit includes: a first voltage source, a second voltage source, and a ninth MOS transistor, wherein, When the source follower is an NMOS transistor, the first voltage source is connected to the gate of the ninth MOS transistor, the second voltage source is connected to the source of the ninth MOS transistor, and the drain of the ninth MOS transistor is connected to the drain of the source follower.

3. The control circuit of the fully differential capacitor feedback amplifier according to claim 2, characterized in that, When the source follower is a PMOS transistor, the drain of the source follower is connected to the drain of the ninth MOS transistor, the gate of the ninth MOS transistor is connected to the first voltage source, the source of the ninth MOS transistor is grounded, and the source of the source follower is connected to the gate of the controllable impedance pseudo resistor.

4. The control circuit of the fully differential capacitor feedback amplifier according to claim 2, characterized in that, The current source bias circuit includes: a current source, a tenth MOSFET, and an eleventh MOSFET, wherein... When the source follower is an NMOS transistor, the output of the current source is connected to the drain of the tenth MOS transistor, the gate of the tenth MOS transistor, and the gate of the eleventh MOS transistor. The sources of the tenth MOS transistor and the eleventh MOS transistor are grounded, and the drain of the eleventh MOS transistor is connected to the source of the source follower.

5. The control circuit of the fully differential capacitor feedback amplifier according to claim 4, characterized in that, When the source follower is a PMOS transistor, in the current source bias circuit, the source of the tenth MOS transistor is connected to the second voltage source, the drain and gate of the tenth MOS transistor are connected to the current source, the gate of the tenth MOS transistor is connected to the gate of the eleventh MOS transistor, the source of the eleventh MOS transistor is connected to the second voltage source, the drain of the eleventh MOS transistor is connected to the source of the source follower, and the gate of the source follower is connected to the reference potential.

6. The control circuit of the fully differential capacitor feedback amplifier according to claim 1, characterized in that, The capacitively coupled amplifier includes: a first input voltage, a second input voltage, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a transconductance amplifier, wherein, When the controllable impedance pseudo-resistance is a PMOS transistor, one end of the first capacitor is connected to the first input voltage, the other end of the first capacitor is connected to one end of the third capacitor and connected to the first terminal of the transconductance amplifier, and the other end of the third capacitor is connected to the fourth terminal of the transconductance amplifier. One end of the second capacitor is connected to the second input voltage, the other end of the second capacitor is connected to one end of the fourth capacitor and connected to the second terminal of the transconductance amplifier, and the other end of the fourth capacitor is connected to the third terminal of the transconductance amplifier; The first terminal of the transconductance amplifier is also connected to the drain of the third MOS transistor and the source of the fourth MOS transistor; The second terminal of the transconductance amplifier is also connected to the drain of the fifth MOS transistor and the source of the sixth MOS transistor.

7. The control circuit of the fully differential capacitor feedback amplifier according to claim 6, characterized in that, When the controllable impedance pseudo-resistor is an NMOS transistor, the drain of the third MOS transistor is connected to the first terminal of the transconductance amplifier, the source of the fourth MOS transistor is connected to the first terminal of the transconductance amplifier, the source of the fifth MOS transistor is connected to the second terminal of the transconductance amplifier, and the drain of the sixth MOS transistor is connected to the second terminal of the transconductance amplifier; the first capacitor is connected to the first input voltage, the other end of the first capacitor and one end of the third capacitor are connected to the first terminal of the transconductance amplifier, the other end of the third capacitor is connected to the fourth terminal of the transconductance amplifier, the second capacitor is connected to the second input voltage, the other end of the second capacitor and one end of the fourth capacitor are connected to the second terminal of the transconductance amplifier, and the other end of the fourth capacitor is connected to the third terminal of the transconductance amplifier.

8. The control circuit of the fully differential capacitor feedback amplifier according to claim 1, characterized in that, The reference voltage of the reference potential is generated by a reference potential generator or obtained by resistor voltage division.

9. A control method for a control circuit of a fully differential capacitor feedback amplifier, characterized in that, The control circuit applied to the fully differential capacitor feedback amplifier according to any one of claims 1 to 8 includes: The gate of the controllable impedance pseudo-resistor is controlled by a source follower, and the source voltage of the source follower is controlled by a current source bias circuit and a reference potential. The controllable impedance pseudo-resistance is charged based on the source voltage of the source follower. The controllable impedance pseudo-resistor is used to control the weak inversion region; the controllable impedance pseudo-resistor is a linear resistor, and the linear resistor is used to change the resistance value by arbitrarily adding or removing MOS transistors in series.

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