A current-controllable pre-pre-amplification latch comparator circuit and device

Abstract

The application provides a current-controllable pre-amplification latch comparator circuit and device, which comprises a pre-amplifier module and a latch module, the pre-amplifier module is connected with a clock circuit generating a clock signal, the pre-amplifier module comprises a differential amplification submodule and a source follower amplification submodule, the differential amplification submodule is connected with the source follower amplification submodule, the source follower amplification submodule is connected with the latch module, the differential amplification submodule and the source follower amplification submodule each comprise a current control unit, when the clock signal is in one of the level states, the current control unit reduces the total current in the pre-amplifier module based on the clock signal, the differential amplification submodule forms a negative feedback based on the clock signal and generates a common-mode bias. The application meets the requirements of speed and accuracy, and the overall static power consumption is low.

Description

Technical Field

[0001] This invention belongs to the field of comparator circuit technology, specifically relating to a current-controllable preamplifier latch comparator circuit and device. Background Technology

[0002] With the rapid development of analog integrated circuits, analog-to-digital converters (ADCs) are widely used in communication systems. Pipeline ADCs, which can simultaneously meet the requirements of high speed, high precision, and low power consumption, are well-suited to the development of modern communications and have therefore attracted much attention and research.

[0003] As the core module of a pipelined ADC, the comparator must also meet the requirements of high speed and high precision. The challenges for comparators used in all pipelined ADCs are speed and accuracy, but with technological advancements, power consumption requirements are also gradually increasing. When designing a comparator, power consumption, speed, accuracy, noise, and offset are all primary considerations. Pure dynamic latch comparators and pre-amplified latch comparators are frequently used in high-speed, high-precision ADCs. Pure dynamic comparators can meet high-speed requirements and have no static power consumption, but due to structural limitations, they are not easy to achieve high precision, and they also have relatively high kickback noise and offset voltage. Pre-amplified latch comparators, by adding an amplifier stage, can simultaneously meet the requirements of speed and accuracy well, but this structure introduces static power consumption, resulting in higher overall power consumption. Summary of the Invention

[0004] This invention provides a current-controllable preamplifier latch comparator circuit and device.

[0005] In a first aspect, the present invention provides a current-controllable preamplifier latch comparator circuit, the circuit comprising a preamplifier module and a latch module, the preamplifier module being connected to a clock circuit that generates a clock signal, the preamplifier module comprising a differential amplifier submodule and a source follower amplifier submodule, the differential amplifier submodule being connected to the source follower amplifier submodule, the source follower amplifier submodule being connected to the latch module, and both the differential amplifier submodule and the source follower amplifier submodule comprising a current control unit, wherein when the clock signal is at one of its levels, the current control unit reduces the total current in the preamplifier module based on the clock signal, and the differential amplifier submodule forms negative feedback based on the clock signal and generates a common-mode bias.

[0006] Optionally, the current control unit includes a first current control unit, and the differential amplifier submodule further includes PMOS transistors M1, M2, M3, M4, M5, M6, M7, and M8, and a negative feedback unit. The source of PMOS transistor M1 is connected to the power supply, the drain of PMOS transistor M1 is connected to the source of PMOS transistor M2, the drain of PMOS transistor M2 is connected to the drain of NMOS transistor M3, the source of NMOS transistor M3 is grounded, the gate of NMOS transistor M3 is connected to the gate of NMOS transistor M4, the first current control unit, and the source follower amplifier submodule, the source of NMOS transistor M4 is grounded, the drain of NMOS transistor M4 is connected to the negative feedback unit, and the first current control unit is connected to the negative feedback unit.

[0007] The negative feedback unit is connected to the drain of PMOS transistor M7 and the drain of PMOS transistor M8. The gates of PMOS transistors M1 and M2 are both connected to the gates of PMOS transistors M7 and M8. The source of PMOS transistor M7 is connected to the drain of PMOS transistor M5. The drain of PMOS transistor M7 is connected to the gate of PMOS transistor M5 and the source follower amplifier submodule. The source of PMOS transistor M8 is connected to the drain of PMOS transistor M6 and the source follower amplifier submodule. The drain of PMOS transistor M8 is connected to the gate of PMOS transistor M6. The sources of PMOS transistors M5 and M6 are both connected to the power supply and the source follower amplifier submodule.

[0008] Optionally, the negative feedback unit includes NMOS transistors M9 and M10, switch K1, and switch K2. The drain of NMOS transistor M4 is connected to the source of NMOS transistor M9, the source of NMOS transistor M10, and the first current control unit. The gate of NMOS transistor M9 is connected to the input terminal Vip and one end of switch K1. The other end of switch K1 is connected to the drain of NMOS transistor M9 and the drain of PMOS transistor M7. The gate of NMOS transistor M10 is connected to the input terminal Vin and one end of switch K2. The other end of switch K2 is connected to the drain of NMOS transistor M10 and the drain of PMOS transistor M8.

[0009] Optionally, the current control unit further includes a second current control unit and a third current control unit. The source follower amplification submodule includes capacitors C1, C2, C3, and C4, switches K3 and K4, NMOS transistors M11, M12, M13, M14, M15, and M16, a first pre-charge unit, and a second pre-charge unit. One end of the differential amplification submodule is connected to the gate of NMOS transistor M11, the second current control unit, the gate of NMOS transistor M14, and the third current control unit. The other end of the differential amplification submodule is connected to the PMOS transistor M16. The source of S-channel transistor M13, the first pre-charge unit, the source of PMOS transistor M16, and the second pre-charge unit are connected. The drain of NMOS transistor M11 is connected to the second current control unit and the source of NMOS transistor M12. The gate of NMOS transistor M12 is connected to one end of switch K3 and one end of capacitor C1. The other end of switch K3 and the other end of capacitor C1 are both connected to the differential amplifier submodule. The first pre-charge unit is also connected to the gate of PMOS transistor M13, the source of NMOS transistor M12, the output terminal Von, and one end of capacitor C3. The other end of capacitor C3 is grounded.

[0010] The drain of the NMOS transistor M14 is connected to the third current control unit and the source of the NMOS transistor M15. The gate of the NMOS transistor M15 is connected to one end of the switch K4 and one end of the capacitor C2. The other end of the switch K4 and the other end of the capacitor C2 are both connected to the differential amplifier submodule. The second precharge unit is also connected to the gate of the PMOS transistor M16, the source of the NMOS transistor M15, the output terminal Vop, and one end of the capacitor C4. The other end of the capacitor C4 is grounded.

[0011] Optionally, the first pre-charge unit is a PMOS transistor Ma, the source of which is connected to the source of PMOS transistor M13, the gate of which is connected to the gate of PMOS transistor M13, and the drain of which is connected to the output terminal Von. The second pre-charge unit is a PMOS transistor Mb, the source of which is connected to the source of PMOS transistor M16, the gate of which is connected to the gate of PMOS transistor M16, and the drain of which is connected to the output terminal Vop.

[0012] Optionally, the current control unit includes a switch K0 and an NMOS transistor M0. The gate of the NMOS transistor M0 is connected to the gate of the NMOS transistor M3. The source of the NMOS transistor M0 is grounded, and the drain of the NMOS transistor M0 is connected to the switch K0. The total current in the preamplifier module is controlled by the switch K0.

[0013] Optionally, switches K0, K1, K2, K3, and K4 are all connected to the clock circuit. When the clock signal is low, switch K0 is closed, and switches K1, K2, K3, and K4 are open; when the clock signal is high, switch K0 is open, and switches K1, K2, K3, and K4 are closed.

[0014] Optionally, the latch module includes two inverters connected in parallel, and the input of one inverter is connected to the output of the other inverter.

[0015] Optionally, the circuit further includes an isolating switch, with the preamplifier module connected to one end of the isolating switch and the latch module connected to the other end of the isolating switch.

[0016] In a second aspect, the present invention also provides an apparatus comprising a current-controllable preamplifier latch comparator circuit as described in the first aspect.

[0017] The beneficial effects of this invention are as follows: The circuit of this invention includes a preamplifier module and a latch module. The preamplifier module is connected to a clock circuit that generates a clock signal. The preamplifier module includes a differential amplifier submodule and a source follower amplifier submodule. The differential amplifier submodule is connected to the source follower amplifier submodule, and the source follower amplifier submodule is connected to the latch module. Both the differential amplifier submodule and the source follower amplifier submodule include a current control unit. When the clock signal is in one of the level states, the current control unit reduces the total current in the preamplifier module based on the clock signal. The differential amplifier submodule forms negative feedback based on the clock signal and generates a common-mode bias.

[0018] The circuit of this invention employs a latch structure. The positive feedback connection of the latch structure itself has high-speed characteristics. Furthermore, the preamplifier module in this invention's circuit includes a two-stage architecture: a differential amplifier submodule and a source follower amplifier submodule. The source follower amplifier submodule acts as a buffer to reduce noise in the circuit, thereby improving accuracy. The current control unit of this invention reduces the total current in the preamplifier module based on a clock signal. The differential amplifier submodule forms negative feedback based on the clock signal and generates a common-mode bias, thereby providing voltage to the external sampling network and reducing the overall static power consumption of the circuit. Attached Figure Description

[0019] Figure 1 This is a circuit diagram of a current-controllable preamplifier latch comparator in one embodiment of the present invention.

[0020] Figure 2 This is a circuit diagram of a preamplifier module in one embodiment of the present invention.

[0021] Explanation of reference numerals in the attached figures:

[0022] 1. Preamplifier module; 2. Latch module; 11. Differential amplifier submodule; 12. Source follower amplifier submodule; 101. Current control unit; 121. Precharge unit. Detailed Implementation

[0023] This invention discloses a current-controllable preamplifier latch comparator circuit.

[0024] In one embodiment of the present invention, reference is made to... Figure 1 The circuit includes a preamplifier module and a latch module. The input terminals of the preamplifier module are connected to the signal input terminal and the reference voltage input terminal through filter capacitors. The signal input terminal includes Vinp and Vinn terminals, and the reference voltage input terminal includes Vreft and Vrefb terminals. The output terminal of the preamplifier module is connected to the latch module through an isolating switch K4, which serves as an isolation switch in the circuit. In this embodiment, the latch module adopts a positive feedback connection, specifically including two inverters connected in parallel, with the input terminal of one inverter connected to the output terminal of the other inverter. The input and output terminals of the preamplifier module are short-circuited by a control switch K1, which controls the operating state of the preamplifier module.

[0025] In one embodiment of the present invention, reference is made to... Figure 1 and Figure 2The preamplifier module is connected to the clock circuit that generates the clock signal. The preamplifier module includes a differential amplifier submodule and a source follower amplifier submodule. The differential amplifier submodule is connected to the source follower amplifier submodule, and the source follower amplifier submodule is connected to the latch module. Both the differential amplifier submodule and the source follower amplifier submodule include a current control unit. When the clock signal is at one of the two levels, the current control unit reduces the total current in the preamplifier module based on the clock signal. The differential amplifier submodule forms negative feedback based on the clock signal and generates a common-mode bias.

[0026] The preamplifier module in this embodiment comprises a two-stage architecture: the first stage uses a differential amplifier submodule, and the second stage uses a source follower amplifier submodule. Since kickback noise is a major factor affecting the accuracy of high-speed comparators, transient charging and discharging currents are generated at the feedback node during comparison, resulting in kickback noise. Therefore, in addition to the isolation switch K4 for isolation, the source follower amplifier submodule further isolates the preamplifier submodule and the latch module to further reduce noise, thereby improving the comparator's accuracy. Simultaneously, the source follower amplifier submodule itself can provide a large current, improving drive capability and, to some extent, increasing the overall transmission speed of the circuit.

[0027] The current control unit includes a first current control unit, a second current control unit, and a third current control unit, where "first," "second," and "third" are used only for distinguishing names and have no other meaning. In this embodiment, the differential amplifier submodule also includes PMOS transistors M1, M2, M3, M4, M5, M6, M7, and M8, and a negative feedback unit. The source of PMOS transistor M1 is connected to the power supply, the drain of PMOS transistor M1 is connected to the source of PMOS transistor M2, the drain of PMOS transistor M2 is connected to the drain of NMOS transistor M3, the source of NMOS transistor M3 is grounded, the gate of NMOS transistor M3 is connected to the gate of NMOS transistor M4, the first current control unit, and the source follower amplifier submodule, the source of NMOS transistor M4 is grounded, the drain of NMOS transistor M4 is connected to the negative feedback unit, and the first current control unit is connected to the negative feedback unit.

[0028] The negative feedback unit is connected to the drain of PMOS transistor M7 and the drain of PMOS transistor M8. The gates of PMOS transistors M1 and M2 are both connected to the gates of PMOS transistors M7 and M8. The source of PMOS transistor M7 is connected to the drain of PMOS transistor M5. The drain of PMOS transistor M7 is connected to the gate of PMOS transistor M5 and the source follower amplifier submodule. The source of PMOS transistor M8 is connected to the drain of PMOS transistor M6 and the source follower amplifier submodule. The drain of PMOS transistor M8 is connected to the gate of PMOS transistor M6. The sources of PMOS transistors M5 and M6 are both connected to the power supply and the source follower amplifier submodule.

[0029] In this embodiment, the negative feedback unit includes NMOS transistors M9 and M10, switch K1 and switch K2. The drain of NMOS transistor M4 is connected to the source of NMOS transistor M9, the source of NMOS transistor M10 and the first current control unit. The gate of NMOS transistor M9 is connected to the input terminal Vip and one end of switch K1. The other end of switch K1 is connected to the drain of NMOS transistor M9 and the drain of PMOS transistor M7. The gate of NMOS transistor M10 is connected to the input terminal Vin and one end of switch K2. The other end of switch K2 is connected to the drain of NMOS transistor M10 and the drain of PMOS transistor M8.

[0030] In this embodiment, the pre-charge unit includes a first pre-charge unit and a second pre-charge unit, where "first" and "second" are used only for name differentiation and have no other meaning. The source follower amplifier submodule includes capacitors C1, C2, C3, and C4, switches K3 and K4, NMOS transistors M11, M12, M13, M14, M15, and M16. One end of the differential amplifier submodule is connected to the gate of NMOS transistor M11, the second current control unit, the gate of NMOS transistor M14, and the third current control unit. The other end of the differential amplifier submodule is connected to the source of PMOS transistor M13, the first pre-charge unit, the source of PMOS transistor M16, and the second pre-charge unit.

[0031] The drain of NMOS transistor M11 is connected to the second current control unit and the source of NMOS transistor M12. The gate of NMOS transistor M12 is connected to one end of switch K3 and one end of capacitor C1. The other end of switch K3 and the other end of capacitor C1 are both connected to the differential amplifier submodule. The first precharge unit is also connected to the gate of PMOS transistor M13, the source of NMOS transistor M12, the output terminal Von, and one end of capacitor C3. The other end of capacitor C3 is grounded. The drain of NMOS transistor M14 is connected to the third current control unit and the source of NMOS transistor M15. The gate of NMOS transistor M15 is connected to one end of switch K4 and one end of capacitor C2. The other end of switch K4 and the other end of capacitor C2 are both connected to the differential amplifier submodule. The second precharge unit is also connected to the gate of PMOS transistor M16, the source of NMOS transistor M15, the output terminal Vop, and one end of capacitor C4. The other end of capacitor C4 is grounded.

[0032] Reference Figure 2 In this embodiment, the preamplifier module adopts a two-stage structure, using a clock signal to control switches K1, K2, K3, and K4, thereby achieving pre-amplification based on the charge transfer principle and through capacitors C1 and C2. The amplification principle is as follows:

[0033] Amplification stage: (V) inp ×A v1 -V xn )×C=Q1,(V inn ×A v1 -V xn )×C=Q1;

[0034] Maintenance phase: (V) cmn -V c )×C=Q1,(V cmp -V c )×C=Q1;

[0035] In the formula, V cmn =V cmp V cmn and V cmp These are the self-biased voltages generated at ports Vo1 and Vo2 during the sampling phase, i.e., when switches K1 and K2 are closed. A v1 For the gain of the first-stage differential amplifier submodule, A v2 This is the gain of the second-stage source follower amplification submodule. Based on the amplification stage and the principle of charge conservation during the stage, we can obtain:

[0036] Vx = A v1 *Vin, Von-Vop = A v1 *A v2 *Vin.

[0037] In this embodiment, the first pre-charge unit is a PMOS transistor Ma. The source of PMOS transistor Ma is connected to the source of PMOS transistor M13, the gate of PMOS transistor Ma is connected to the gate of PMOS transistor M13, and the drain of PMOS transistor Ma is connected to the output terminal Von. The second pre-charge unit is a PMOS transistor Mb. The source of PMOS transistor Mb is connected to the source of PMOS transistor M16, the gate of PMOS transistor Mb is connected to the gate of PMOS transistor M16, and the drain of PMOS transistor Mb is connected to the output terminal Vop. Pre-charging is performed by differentially outputting Vop and Von through PMOS transistors Ma and Mb. Due to the parasitic capacitance caused by capacitors C3 and C4, the outputs of PMOS transistors Ma and Mb charge capacitors C3 and C4. This charging process consumes time and increases the circuit slew rate. Therefore, by pre-charging PMOS transistors Ma and Mb, the charging time of capacitors C3 and C4 at output terminals Vop and Von is reduced, thereby further reducing the propagation time of the preamplifier and thus improving the overall circuit propagation speed.

[0038] In this embodiment, the current control unit includes a switch K0 and an NMOS transistor M0. The gate of the NMOS transistor M0 is connected to the gate of the NMOS transistor M3. The source of the NMOS transistor M0 is grounded, and the drain of the NMOS transistor M0 is connected to the switch K0. The total current in the preamplifier module is controlled by the switch K0. Switches K0, K1, K2, K3, and K4 are all connected to the clock circuit. When the clock signal is low, switch K0 is closed, and switches K1, K2, K3, and K4 are open. At this time, the total current in the preamplifier module is I0+I1+I2+I3+I4+I5+I6. When the clock signal is high, switch K0 is open, and switches K1, K2, K3, and K4 are closed. At this time, due to the opening of switch K0, the total current in the preamplifier module is I0+I1+I3+I5. The total current decreases in this state. However, due to the closing of switches K1 and K2, the gate and drain of NMOS transistors M9 and M10 in the negative feedback unit are shorted, thus forming negative feedback, generating a common-mode bias voltage and providing it to the external sampling network. Therefore, no additional common-mode generation circuit is needed, achieving the effect of reducing the static power consumption of the circuit.

[0039] The implementation principle of this method is as follows:

[0040] The circuit in this invention includes a preamplifier module and a latch module. The preamplifier module is connected to a clock circuit that generates a clock signal. The preamplifier module includes a differential amplifier submodule and a source follower amplifier submodule. The differential amplifier submodule is connected to the source follower amplifier submodule, and the source follower amplifier submodule is connected to the latch module. Both the differential amplifier submodule and the source follower amplifier submodule include a current control unit. When the clock signal is at one of its levels, the current control unit reduces the total current in the preamplifier module based on the clock signal. The differential amplifier submodule forms negative feedback based on the clock signal and generates a common-mode bias, thus eliminating the need for an additional common-mode generation circuit. Simultaneously, the pre-charging method of the pre-charging unit accelerates the overall transmission time of the preamplifier module. Amplification is achieved through the sampling charge transfer principle. The isolation and high drive capability of the source follower amplifier submodule reduce kickback noise and improve the SR rate.

[0041] The present invention also provides an apparatus, the apparatus comprising: Figure 1 and Figure 2 The circuit shown. In Figure 1 and Figure 2 The circuit shown includes a preamplifier module and a latch module. The preamplifier module is connected to a clock circuit that generates the clock signal. The preamplifier module includes a differential amplifier submodule and a source follower amplifier submodule. The differential amplifier submodule is connected to the source follower amplifier submodule, and the source follower amplifier submodule is connected to the latch module. Both the differential amplifier submodule and the source follower amplifier submodule include a current control unit. When the clock signal is at one of its levels, the current control unit reduces the total current in the preamplifier module based on the clock signal. The differential amplifier submodule forms negative feedback based on the clock signal and generates a common-mode bias, thus eliminating the need for an additional common-mode generation circuit. Simultaneously, the pre-charging method of the pre-charging unit accelerates the overall propagation time of the preamplifier module. Amplification is achieved through the sampling charge transfer principle. The isolation and high drive capability of the source follower amplifier submodule reduce kickback noise and improve the SR rate.

[0042] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of protection of this application is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0043] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.

Claims

1. A current-controllable preamplifier latch comparator circuit, characterized in that, The circuit includes a preamplifier module and a latch module. The preamplifier module is connected to a clock circuit that generates a clock signal. The preamplifier module includes a differential amplifier submodule and a source follower amplifier submodule. The differential amplifier submodule is connected to the source follower amplifier submodule, and the source follower amplifier submodule is connected to the latch module. The differential amplifier submodule includes a first current control unit, and the source follower amplifier submodule includes a second current control unit and a third current control unit. When the clock signal is at one of the two levels, the current control unit reduces the total current in the preamplifier module based on the clock signal. The differential amplifier submodule forms negative feedback based on the clock signal and generates a common-mode bias. The differential amplifier submodule further includes PMOS transistors M1, M2, M3, M4, M5, M6, M7, and M8, and a negative feedback unit. The source of PMOS transistor M1 is connected to the power supply, the drain of PMOS transistor M1 is connected to the source of PMOS transistor M2, the drain of PMOS transistor M2 is connected to the drain of NMOS transistor M3, the source of NMOS transistor M3 is grounded, the gate of NMOS transistor M3 is connected to the gate of NMOS transistor M4, the first current control unit, and the source follower amplifier submodule, the source of NMOS transistor M4 is grounded, the drain of NMOS transistor M4 is connected to the negative feedback unit, and the first current control unit is connected to the negative feedback unit. The negative feedback unit is connected to the drain of PMOS transistor M7 and the drain of PMOS transistor M8. The gates of PMOS transistors M1 and M2 are both connected to the gates of PMOS transistors M7 and M8. The source of PMOS transistor M7 is connected to the drain of PMOS transistor M5. The drain of PMOS transistor M7 is connected to the gate of PMOS transistor M5 and the source follower amplifier submodule. The source of PMOS transistor M8 is connected to the drain of PMOS transistor M6 and the source follower amplifier submodule. The drain of PMOS transistor M8 is connected to the gate of PMOS transistor M6. The sources of PMOS transistors M5 and M6 are both connected to the power supply and the source follower amplifier submodule. The negative feedback unit includes NMOS transistors M9 and M10, switch K1, and switch K2. The drain of NMOS transistor M4 is connected to the source of NMOS transistor M9, the source of NMOS transistor M10, and the first current control unit. The gate of NMOS transistor M9 is connected to the input terminal Vip and one end of switch K1. The other end of switch K1 is connected to the drain of NMOS transistor M9 and the drain of PMOS transistor M7. The gate of NMOS transistor M10 is connected to the input terminal Vin and one end of switch K2. The other end of switch K2 is connected to the drain of NMOS transistor M10 and the drain of PMOS transistor M8.

2. The current-controllable preamplifier latch comparator circuit according to claim 1, characterized in that, The source follower amplification submodule includes capacitors C1, C2, C3, and C4, switches K3 and K4, NMOS transistors M11, M12, M13, M14, M15, and M16, a first pre-charge unit, and a second pre-charge unit. One end of the differential amplification submodule is connected to the gate of NMOS transistor M11, the second current control unit, the gate of NMOS transistor M14, and the third current control unit. The other end of the differential amplification submodule is connected to the source of PMOS transistor M13 and the first pre-charge unit. The first precharge unit is connected to the source of the PMOS transistor M16 and the second precharge unit. The drain of the NMOS transistor M11 is connected to the second current control unit and the source of the NMOS transistor M12. The gate of the NMOS transistor M12 is connected to one end of the switch K3 and one end of the capacitor C1. The other end of the switch K3 and the other end of the capacitor C1 are both connected to the differential amplifier submodule. The first precharge unit is also connected to the gate of the PMOS transistor M13, the source of the NMOS transistor M12, the output terminal Von, and one end of the capacitor C3. The other end of the capacitor C3 is grounded. The drain of the NMOS transistor M14 is connected to the third current control unit and the source of the NMOS transistor M15. The gate of the NMOS transistor M15 is connected to one end of the switch K4 and one end of the capacitor C2. The other end of the switch K4 and the other end of the capacitor C2 are both connected to the differential amplifier submodule. The second precharge unit is also connected to the gate of the PMOS transistor M16, the source of the NMOS transistor M15, the output terminal Vop, and one end of the capacitor C4. The other end of the capacitor C4 is grounded.

3. The current-controllable preamplifier latch comparator circuit according to claim 2, characterized in that, The first pre-charge unit is a PMOS transistor Ma, the source of which is connected to the source of PMOS transistor M13, the gate of which is connected to the gate of PMOS transistor M13, and the drain of which is connected to the output terminal Von. The second pre-charge unit is a PMOS transistor Mb, the source of which is connected to the source of PMOS transistor M16, the gate of which is connected to the gate of PMOS transistor M16, and the drain of which is connected to the output terminal Vop.

4. The current-controllable preamplifier latch comparator circuit according to claim 2, characterized in that, The current control units have the same structure, including a switch K0 and an NMOS transistor M0. The gate of the NMOS transistor M0 is connected to the gate of the NMOS transistor M3. The source of the NMOS transistor M0 is grounded, and the drain of the NMOS transistor M0 is connected to the switch K0. The total current in the preamplifier module is controlled by the switch K0.

5. The current-controllable preamplifier latch comparator circuit according to claim 4, characterized in that, The switches K0, K1, K2, K3, and K4 are all connected to the clock circuit. When the clock signal is low, switch K0 is closed, and switches K1, K2, K3, and K4 are open. When the clock signal is high, switch K0 is open, and switches K1, K2, K3 and K4 are closed.

6. The current-controllable preamplifier latch comparator circuit according to claim 1, characterized in that, The latch module includes two inverters connected in parallel, and the input of one inverter is connected to the output of the other inverter.

7. The current-controllable preamplifier latch comparator circuit according to claim 1, characterized in that, The circuit also includes an isolating switch, the preamplifier module is connected to one end of the isolating switch, and the latch module is connected to the other end of the isolating switch.

8. An electronic device, characterized in that, The electronic device includes a current-controllable preamplifier latch comparator circuit as described in any one of claims 1 to 7.

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