An ideal diode circuit

Abstract

The embodiment of the application provides an ideal diode circuit, which realizes the function of allowing current to flow in one direction only by using a first transistor sub-circuit, a first current direction selection sub-circuit and a second current direction selection sub-circuit; the first transistor sub-circuit is protected by using a first protection sub-circuit, the first current direction selection sub-circuit is protected by using a second protection sub-circuit, and the second current direction selection sub-circuit is protected by using a third protection sub-circuit, so that the safety performance of the circuit is improved; in addition, the conduction loss of the transistor is lower than that of the diode, so that the ideal diode circuit characteristics can be realized while the conduction voltage drop is reduced.

Description

Technical Field

[0001] This application relates to the field of diode technology, and in particular to an ideal diode circuit. Background Technology

[0002] Diodes are widely used electronic components, characterized by allowing current to flow in only one direction. However, when a diode is conducting, it generates a forward voltage drop, typically ranging from 0.6V to 0.8V, which is relatively large. Therefore, designing an ideal diode circuit that reduces the forward voltage drop while still achieving the diode's function is a problem that urgently needs to be solved. Summary of the Invention

[0003] The purpose of this application is to provide an ideal diode circuit to achieve the function of an ideal diode. The specific technical solution is as follows:

[0004] This application provides an ideal diode circuit, the circuit comprising:

[0005] A first transistor subcircuit, a first protection subcircuit, a first current direction selection subcircuit, a second current direction selection subcircuit, a second protection subcircuit, and a third protection subcircuit; the first protection subcircuit is used to protect the first transistor subcircuit; the second protection subcircuit is used to protect the first current direction selection subcircuit; and the third protection subcircuit is used to protect the second current direction selection subcircuit.

[0006] The first transistor sub-circuit is connected to the first protection sub-circuit, the first current direction selection sub-circuit, and the second current direction selection sub-circuit, respectively, and the first current direction selection sub-circuit is connected to the second current direction selection sub-circuit.

[0007] The first current direction selection sub-circuit is connected to the second protection sub-circuit;

[0008] The second current direction selection sub-circuit is connected to the third protection sub-circuit.

[0009] In one possible implementation, the first transistor sub-circuit includes a PMOS transistor, the first protection sub-circuit includes a first resistor, and the first current direction selection sub-circuit includes a first transistor; the second current direction selection sub-circuit includes a second transistor, the second protection sub-circuit includes a second resistor, and the third protection sub-circuit includes a third resistor; both the first transistor and the second transistor are P-type transistors.

[0010] The drain of the PMOS transistor is connected to the first terminal and the emitter of the first transistor, the source of the PMOS transistor is connected to one end of the first resistor, the second terminal of the first resistor, and the emitter of the second transistor, and the gate of the PMOS transistor is connected to the collector of the second transistor and the other end of the first resistor; the first terminal is one end of the power supply line, and the second terminal is the other end of the power supply line.

[0011] The base of the first transistor is connected to the collector of the first transistor, the base of the second transistor, and one end of the second resistor, respectively.

[0012] The collector of the second transistor is connected to one end of the third resistor;

[0013] The other end of the second resistor is grounded; the other end of the third resistor is grounded.

[0014] In one possible implementation, the first transistor sub-circuit includes a PMOS transistor, the first protection sub-circuit includes a first resistor, and the first current direction selection sub-circuit includes a first diode; the second current direction selection sub-circuit includes a second transistor, the second protection sub-circuit includes a second resistor, and the third protection sub-circuit includes a third resistor; the second transistor is a P-type transistor.

[0015] The drain of the PMOS transistor is connected to the first terminal and the positive terminal of the first diode, the source of the PMOS transistor is connected to one end of the first resistor, the second terminal of the first resistor, and the emitter of the second transistor, and the gate of the PMOS transistor is connected to the collector of the second transistor and the other end of the first resistor; the first terminal is one end of the power line, and the second terminal is the other end of the power line.

[0016] The cathode of the first diode is connected to the base of the second transistor and one end of the second resistor, respectively;

[0017] The collector of the second transistor is connected to one end of the third resistor;

[0018] The other end of the second resistor is grounded; the other end of the third resistor is grounded.

[0019] In one possible implementation, the circuit further includes a fourth protection sub-circuit; the fourth protection sub-circuit is used to protect the first transistor sub-circuit.

[0020] In one possible implementation, the first transistor sub-circuit includes a PMOS transistor, the first protection sub-circuit includes a first resistor, and the first current direction selection sub-circuit includes a first transistor; the second current direction selection sub-circuit includes a second transistor, the second protection sub-circuit includes a second resistor, and the third protection sub-circuit includes a third resistor; the fourth protection sub-circuit includes a fourth resistor and a third transistor; the first transistor and the second transistor are both P-type transistors; and the third transistor is an N-type transistor.

[0021] The drain of the PMOS transistor is connected to the first terminal and the emitter of the first transistor, the source of the PMOS transistor is connected to one end of the first resistor, the second terminal of the first resistor, and the emitter of the second transistor, and the gate of the PMOS transistor is connected to the other end of the first resistor and one end of the fourth resistor; the first terminal is one end of the power supply line, and the second terminal is the other end of the power supply line.

[0022] The other end of the fourth resistor is connected to the collector of the third transistor;

[0023] The base of the third transistor is connected to the collector of the first transistor and one end of the second resistor, respectively; the emitter of the third transistor is grounded.

[0024] The base of the first transistor is connected to the base of the second transistor;

[0025] The collector of the second transistor is connected to the base of the second transistor and one end of the third resistor, respectively;

[0026] The other end of the second resistor is grounded; the other end of the third resistor is grounded.

[0027] In one possible implementation, the first transistor sub-circuit includes a PMOS transistor, the first protection sub-circuit includes a first resistor, and the first current direction selection sub-circuit includes a first transistor; the second current direction selection sub-circuit includes a second diode, the second protection sub-circuit includes a second resistor, and the third protection sub-circuit includes a third resistor; the fourth protection sub-circuit includes a fourth resistor and a third transistor; the first transistor is a P-type transistor; and the third transistor is an N-type transistor.

[0028] The drain of the PMOS transistor is connected to the first terminal and the emitter of the first transistor, the source of the PMOS transistor is connected to one end of the first resistor, the second terminal and the anode of the second diode, and the gate of the PMOS transistor is connected to the other end of the first resistor and one end of the fourth resistor; the first terminal is one end of the power line and the second terminal is the other end of the power line.

[0029] The other end of the fourth resistor is connected to the collector of the third transistor;

[0030] The base of the third transistor is connected to the collector of the first transistor and one end of the second resistor, respectively; the emitter of the third transistor is grounded.

[0031] The base of the first transistor is connected to the negative terminal of the second diode;

[0032] The cathode of the second diode is connected to one end of the third resistor;

[0033] The other end of the second resistor is grounded; the other end of the third resistor is grounded.

[0034] In one possible implementation, the resistance value of the first resistor and the resistance value of the third resistor satisfy the following:

[0035]

[0036] Where R1 is the resistance of the first resistor, R3 is the resistance of the third resistor, and V C(max) The maximum voltage at point C is V. BR This is the reverse breakdown voltage of the PMOS transistor.

[0037] In one possible implementation, the resistance value of the first resistor and the resistance value of the fourth resistor satisfy the following:

[0038]

[0039] Where R1 is the resistance of the first resistor, R4 is the resistance of the fourth resistor, and V C(max) The maximum voltage at point C is V. BR This is the reverse breakdown voltage of the PMOS transistor.

[0040] In one possible implementation, the reverse breakdown voltage of the first transistor satisfies:

[0041] V BR(CEO) >V CA(max) -V F

[0042] Among them, V CA(max) V is the maximum voltage difference between point C and point A. BR(CEO) V is the reverse breakdown voltage of the first transistor; F The on-state voltage drop of the second current direction selection sub-circuit.

[0043] This application also provides an electronic device, which includes the ideal diode circuit described in any of the above embodiments.

[0044] Beneficial effects of the embodiments in this application:

[0045] The ideal diode circuit provided in this application embodiment utilizes a first transistor sub-circuit, a first current direction selection sub-circuit, and a second current direction selection sub-circuit to realize the function of an ideal diode that only allows current to flow in one direction. A first protection sub-circuit protects the first transistor sub-circuit, a second protection sub-circuit protects the first current direction selection sub-circuit, and a third protection sub-circuit protects the second current direction selection sub-circuit, thereby increasing the circuit's safety performance. Moreover, the conduction loss of the transistor is lower than that of the diode, so while realizing the characteristics of an ideal diode circuit, the on-state voltage drop can also be reduced.

[0046] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0048] Figure 1 This is a first schematic diagram of an ideal diode circuit in an embodiment of this application;

[0049] Figure 2 This is a second schematic diagram of an ideal diode circuit in an embodiment of this application;

[0050] Figure 3 This is a third schematic diagram of an ideal diode circuit in the embodiments of this application;

[0051] Figure 4 This is a fourth schematic diagram of an ideal diode circuit in the embodiments of this application;

[0052] Figure 5 This is a fifth schematic diagram of an ideal diode circuit in the embodiments of this application;

[0053] Figure 6 This is a sixth schematic diagram of an ideal diode circuit in the embodiments of this application. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0055] This application provides an ideal diode circuit, which includes:

[0056] A first transistor subcircuit, a first protection subcircuit, a first current direction selection subcircuit, a second current direction selection subcircuit, a second protection subcircuit, and a third protection subcircuit; the first protection subcircuit is used to protect the first transistor subcircuit; the second protection subcircuit is used to protect the first current direction selection subcircuit; and the third protection subcircuit is used to protect the second current direction selection subcircuit.

[0057] The first transistor sub-circuit is connected to the first protection sub-circuit, the first current direction selection sub-circuit, and the second current direction selection sub-circuit, respectively, and the first current direction selection sub-circuit is connected to the second current direction selection sub-circuit.

[0058] The first current direction selection sub-circuit mentioned above is connected to the second protection sub-circuit mentioned above;

[0059] The aforementioned second current direction selection sub-circuit is connected to the aforementioned third protection sub-circuit.

[0060] The first transistor sub-circuit can be a PMOS transistor circuit, see [link / reference]. Figure 1 , Figure 1 This is a first schematic diagram of an ideal diode circuit provided in an embodiment of this application. The first transistor sub-circuit may include a PMOS transistor. The PMOS transistor is characterized by the following behavior: when the gate voltage is lower than the source voltage and |Vgs|>|Vgs(th)| (i.e., when Vgs<Vgs(th)), the PMOS transistor is turned on. Here, Vgs is the voltage between the gate and source of the PMOS transistor, and Vgs(th) is the threshold voltage of the PMOS transistor. Therefore, the PMOS transistor can be turned on and off by controlling its gate, thereby achieving the characteristics of an ideal diode circuit.

[0061] The first and second current direction selection subcircuits can be designed based on power switching transistors, such as diodes or transistors. These subcircuits are used to select the direction of current in the circuit. Combined with the first transistor subcircuit, they ensure that current flows in only one direction in the ideal diode circuit, thus achieving the function of an ideal diode.

[0062] The first protection sub-circuit protects the first transistor sub-circuit, the second protection sub-circuit protects the first current direction selection sub-circuit, and the third protection sub-circuit protects the second current direction selection sub-circuit, which increases the safety performance of the circuit. The function of an ideal diode is achieved by using a small number of basic components, without the need for complex and dedicated control chips, which makes the circuit structure simple and the cost low.

[0063] Moreover, because the conduction loss of a transistor is lower than that of a diode, it can reduce the on-state voltage drop and loss while achieving the characteristics of an ideal diode circuit, thus making it applicable to scenarios with high requirements for power efficiency, heat dissipation, or voltage accuracy.

[0064] In one possible implementation, see Figure 2 The first transistor sub-circuit includes a PMOS transistor N1, the first protection sub-circuit includes a first resistor R1, and the first current direction selection sub-circuit includes a first transistor Q1; the second current direction selection sub-circuit includes a second transistor Q2, the second protection sub-circuit includes a second resistor R2, and the third protection sub-circuit includes a third resistor R3; both the first transistor Q1 and the second transistor Q2 are P-type transistors.

[0065] The drain of the PMOS transistor N1 is connected to the first terminal and the emitter of the first transistor Q1, the source of the PMOS transistor is connected to one end and the second terminal of the first resistor R1 and the emitter of the second transistor Q2, and the gate of the PMOS transistor is connected to the collector of the second transistor Q2 and the other end of the first resistor R1; the first terminal is one end of the power supply line and the second terminal is the other end of the power supply line.

[0066] The base of the first transistor Q1 is connected to the collector of the first transistor Q1, the base of the second transistor Q2, and one end of the second resistor R2, respectively.

[0067] The collector of the second transistor Q2 is connected to one end of the third resistor R3.

[0068] The other end of the second resistor R2 is grounded; the other end of the third resistor R3 is grounded.

[0069] GND1 and GND2 are ground wires.

[0070] PMOS transistor N1 is connected in series on the power supply line. When the gate voltage is lower than the source voltage and |Vgs| > |Vgs(th)|, PMOS transistor N1 is turned on. When PMOS transistor N1 is turned on, because the on-resistance of PMOS transistor N1 is sufficiently small, the voltage drop across PMOS transistor N1 is lower than the on-state voltage of its parasitic diode. Therefore, while ensuring that PMOS transistor N1 has sufficient current carrying capacity, it can also reduce the on-state voltage drop and losses.

[0071] The voltage at point B, i.e., the collector voltage of Q1, is V. B =V A -V F , where V F This is the positive voltage drop of Q1.

[0072] Because resistor R3 is grounded, and R1 is connected in parallel between the gate and source of PMOS transistor N1, if the on-resistance of N1 is infinitesimally small, then the voltage at point D is:

[0073]

[0074] The voltage between the source and gate of PMOS transistor N1 is:

[0075]

[0076] Where V is V A With V C The difference.

[0077] When V C <V A At that time, as long as the voltage V between the source and gate of PMOS transistor N1 is... GS When the voltage exceeds the threshold voltage of N1 but is less than the maximum source-gate voltage of N1, PMOS transistor N1 conducts. This means the circuit is forward-biased and exhibits the forward characteristics of an ideal diode. In other words, by utilizing the voltage divider relationship between R1 and R3, PMOS transistor N1 is ensured to operate within a safe range. Furthermore, R1 shunts current when the PMOS transistor experiences an uncontrolled large transient current, thus protecting the PMOS transistor.

[0078] When V C >V A When transistor Q2 is turned on, V D ≈V C When the voltage difference between the source and gate of PMOS transistor N1 is very small, PMOS transistor N1 is cut off, and the circuit exhibits a high-impedance state. In other words, the circuit is cut off at this time and can exhibit the reverse characteristics of an ideal diode.

[0079] Furthermore, taking the on-state voltage drop of transistor Q2 as an example of 0.6V, then V B =VC -0.6, transistor Q1 needs to withstand a reverse voltage of V. C -0.6-V A As long as the reverse voltage that transistor Q1 withstands is lower than its maximum reverse voltage, the circuit is safe.

[0080] In one possible implementation, see Figure 3 The first transistor sub-circuit mentioned above includes a PMOS transistor N1, wherein the diode in the dashed box in the figure is the parasitic diode of the PMOS transistor N1; the first protection sub-circuit includes a first resistor R1; the first current direction selection sub-circuit includes a first diode Q1; the second current direction selection sub-circuit includes a second transistor Q2; the second protection sub-circuit includes a second resistor R2; the third protection sub-circuit includes a third resistor R3; the second transistor is a P-type transistor.

[0081] The drain of the PMOS transistor N1 is connected to the first terminal and the anode of the first diode Q1, the source of the PMOS transistor N1 is connected to one end and the second end of the first resistor R1 and the emitter of the second transistor Q2, and the gate of the PMOS transistor NQ is connected to the collector of the second transistor Q2 and the other end of the first resistor R1; the first terminal is one end of the power supply line and the second terminal is the other end of the power supply line.

[0082] The cathode of the first diode Q1 is connected to the base of the second transistor Q2 and one end of the second resistor R2, respectively.

[0083] The collector of the second transistor Q2 is connected to one end of the third resistor R3.

[0084] The other end of the second resistor R2 is grounded; the other end of the third resistor R3 is grounded.

[0085] PMOS transistor N1 is connected in series on the power supply line. When the gate voltage is lower than the source voltage and |Vgs| > |Vgs(th)|, PMOS transistor N1 is turned on. When PMOS transistor N1 is turned on, as long as the on-resistance of PMOS transistor N1 is small enough, the voltage drop across PMOS transistor N1 is lower than the on-state voltage of its parasitic diode. This ensures that PMOS transistor N1 has sufficient current carrying capacity while reducing on-state voltage drop and losses.

[0086] The voltage at point B, i.e., the negative terminal voltage V of Q1. B =V A -V F , where V F This is the positive voltage drop of Q1.

[0087] Because resistor R3 is grounded, and R1 is connected in parallel between the gate and source of PMOS transistor N1, if the on-resistance of N1 is infinitesimally small, then the voltage at point D is:

[0088]

[0089] The voltage between the source and gate of PMOS transistor N1 is:

[0090]

[0091] When V C <V A As long as the voltage V between the source and gate of PMOS transistor N1 GS When the voltage exceeds the threshold voltage of N1 but is less than the maximum source-gate voltage of N1, PMOS transistor N1 conducts. This means that the circuit is forward-biased at this time, exhibiting the forward characteristics of an ideal diode. In other words, by utilizing the voltage divider relationship between R1 and R3, PMOS transistor N1 is ensured to operate within a safe range. Furthermore, R1 can protect the PMOS transistor from uncontrolled large transient currents.

[0092] When V C >V A When transistor Q2 is turned on, V D ≈V C The voltage difference between the source and gate of PMOS transistor N1 is very small, so PMOS transistor N1 is cut off, and the circuit exhibits a high-resistance state. That is, the circuit is cut off at this time, exhibiting the reverse characteristics of an ideal diode. Furthermore, if the forward voltage drop of transistor Q2 is 0.6V, then V... B =V C -0.6, diode Q1 needs to withstand a reverse voltage of V. C -0.6-V A As long as the reverse voltage across diode Q1 is lower than its reverse breakdown voltage, the circuit is safe. Furthermore, since the reverse breakdown voltage of a typical diode is generally above 40V, even if V... C- V A The circuit is safe even at voltages above 10V. Therefore, this circuit can be used in high-voltage circuits exceeding 20V.

[0093] In one possible implementation, such as Figure 4 As shown, the circuit also includes a fourth protection sub-circuit; the fourth protection sub-circuit is used to protect the first transistor sub-circuit.

[0094] To further improve the availability of the first transistor sub-circuit, a fourth protection sub-circuit is also introduced in this embodiment to further protect the first transistor sub-circuit.

[0095] In one possible implementation, see Figure 5 The aforementioned PMOS transistor N1 sub-circuit includes a PMOS transistor N1; the aforementioned first protection sub-circuit includes a first resistor R1; the aforementioned first current direction selection sub-circuit includes a first transistor Q1; the aforementioned second current direction selection sub-circuit includes a second transistor Q2; the aforementioned second protection sub-circuit includes a second resistor R2; the aforementioned third protection sub-circuit includes a third resistor R3; the aforementioned fourth protection sub-circuit includes a fourth resistor R4 and a third transistor Q3; the aforementioned first transistor and the aforementioned second transistor are both P-type transistors; the aforementioned third transistor is an N-type transistor.

[0096] The drain of the PMOS transistor N1 is connected to the first terminal and the emitter of the first transistor Q1, the source of the PMOS transistor N1 is connected to one end and the second terminal of the first resistor R1 and the emitter of the second transistor Q2, and the gate of the PMOS transistor N1 is connected to the other end of the first resistor R1 and one end of the fourth resistor R4; the first terminal is one end of the power supply line and the second terminal is the other end of the power supply line.

[0097] The other end of the fourth resistor R4 is connected to the collector of the third transistor Q3.

[0098] The base of the third transistor Q3 is connected to the collector of the first transistor Q1 and one end of the second resistor R2; the emitter of the third transistor Q3 is grounded.

[0099] The base of the first transistor Q1 is connected to the base of the second transistor Q2.

[0100] The collector of the second transistor Q2 is connected to the base of the second transistor Q2 and one end of the third resistor R3, respectively.

[0101] The other end of the second resistor R2 is grounded; the other end of the third resistor R3 is grounded.

[0102] GND3 is the ground wire.

[0103] When V C <V A At that time, as long as the voltage V between the source and gate of PMOS transistor N1 is... GS When the voltage exceeds the threshold voltage of N1 but is less than the maximum source-gate voltage of N1, PMOS transistor N1 conducts. In other words, the circuit is forward-biased at this time, exhibiting the forward characteristics of an ideal diode. Moreover, by utilizing the voltage divider relationship between R1 and R4, PMOS transistor N1 is ensured to operate within a safe range. Furthermore, R1 also ensures that the PMOS transistor is protected from burning out when subjected to uncontrolled large transient currents.

[0104] When VC >V A When, transistor Q2 is turned on, V D ≈V C Because V C >V A When transistor Q1 is cut off, transistor Q3 is subsequently cut off. The voltage difference between the source and gate of PMOS transistor N1 is very small, so PMOS transistor N1 is also cut off, and the circuit exhibits a high-impedance state. In other words, the circuit is cut off at this time and can exhibit the reverse characteristics of an ideal diode.

[0105] Furthermore, if the on-state voltage drop of transistor Q2 is 0.6V, then V D =V C -0.6, transistor Q1 needs to withstand a reverse voltage of V. C -0.6-V A As long as the reverse voltage that transistor Q1 withstands is lower than its maximum reverse voltage, the circuit is safe.

[0106] In one possible implementation, see Figure 6 The aforementioned PMOS transistor N1 sub-circuit includes a PMOS transistor N1; the aforementioned first protection sub-circuit includes a first resistor R1; the aforementioned first current direction selection sub-circuit includes a first transistor Q1; the aforementioned second current direction selection sub-circuit includes a second diode Q1; the aforementioned second protection sub-circuit includes a second resistor R2; the aforementioned third protection sub-circuit includes a third resistor R3; the aforementioned fourth protection sub-circuit includes a fourth resistor R4 and a third transistor Q3; the aforementioned first transistor is a P-type transistor; the aforementioned third transistor is an N-type transistor.

[0107] The drain of the PMOS transistor N1 is connected to the first terminal and the emitter of the first transistor Q1, the source of the PMOS transistor N1 is connected to one end of the first resistor R1, the second terminal of the first resistor R1, and the anode of the second diode Q1, and the gate of the PMOS transistor N1 is connected to the other end of the first resistor R1 and one end of the fourth resistor R4; the first terminal is one end of the power supply line, and the second terminal is the other end of the power supply line.

[0108] The other end of the fourth resistor R4 is connected to the collector of the third transistor Q3.

[0109] The base of the third transistor Q3 is connected to the collector of the first transistor Q1 and one end of the second resistor R2; the emitter of the third transistor Q3 is grounded.

[0110] The base of the first transistor Q1 is connected to the cathode of the second diode Q1.

[0111] The cathode of the second diode Q1 is connected to one end of the third resistor R3.

[0112] The other end of the second resistor R2 is grounded; the other end of the third resistor R3 is grounded.

[0113] When V C <V A At that time, as long as the voltage V between the source and gate of PMOS transistor N1 is... GS When the voltage exceeds the threshold voltage of N1 but is less than the maximum source-gate voltage of N1, PMOS transistor N1 conducts. In other words, the circuit is forward-biased at this time, exhibiting the forward characteristics of an ideal diode. Moreover, by utilizing the voltage divider relationship between R1 and R4, PMOS transistor N1 is ensured to operate within a safe range. Furthermore, R1 also ensures that the PMOS transistor is protected from burning out when subjected to uncontrolled large transient currents.

[0114] When V C >V A When, diode Q1 is turned on, V D =V C -V F , where V F This is the forward voltage drop of Q1. Because V C >V A When transistor Q1 is cut off, transistor Q3 is subsequently cut off. The voltage difference between the source and gate of PMOS transistor N1 is very small, so PMOS transistor N1 is also cut off, and the circuit exhibits a high-impedance state. In other words, the circuit is cut off at this time and can exhibit the reverse characteristics of an ideal diode.

[0115] Furthermore, if the forward voltage drop of diode Q1 is 0.6V, then V D =V C -0.6, transistor Q1 needs to withstand a reverse voltage of V. C -0.6-V A As long as the reverse voltage that transistor Q1 withstands is lower than its maximum reverse voltage, the circuit is safe.

[0116] based on Figure 2 and Figure 3 In one possible implementation of the embodiment shown, the resistance value of the first resistor R1 and the resistance value of the third resistor R3 satisfy the following:

[0117]

[0118] Where R1 is the resistance of the first resistor, R3 is the resistance of the third resistor, and V C(max) The maximum voltage at point C is V. BR This is the reverse breakdown voltage of the PMOS transistor.

[0119] When V C >V AWhen transistor Q2 is turned on, V D ≈V C When the voltage difference between the source and gate of PMOS transistor N1 is very small, PMOS transistor N1 is turned off. The reverse voltage between the source and gate of PMOS transistor N1 must be less than the reverse breakdown voltage of PMOS transistor.

[0120] Because transistor Q2 is turned on, the reverse voltage across the source and gate of PMOS transistor N1 is:

[0121]

[0122] Among them, V C The voltage at point C is to prevent the PMOS transistor from breaking down.

[0123]

[0124] Therefore, as long as The circuit exhibits the reverse characteristics of an ideal diode while also preventing damage to the PMOS transistor.

[0125] based on Figure 5 and Figure 6 In one possible implementation of the illustrated embodiment, the resistance value of the first resistor and the resistance value of the fourth resistor satisfy the following:

[0126]

[0127] Where R1 is the resistance of the first resistor, R4 is the resistance of the fourth resistor, and V C(max) The maximum voltage at point C is V. BR This is the reverse breakdown voltage of the PMOS transistor.

[0128] When V C >V A When transistor Q2 is turned on, V D ≈V C When the voltage difference between the source and gate of PMOS transistor N1 is very small, PMOS transistor N1 is turned off. The reverse voltage between the source and gate of PMOS transistor N1 must be less than the reverse breakdown voltage of PMOS transistor.

[0129] Because transistor Q2 is turned on, the reverse voltage across the source and gate of PMOS transistor N1 is:

[0130]

[0131] Among them, V C The voltage at point C is to prevent the PMOS transistor from breaking down.

[0132]

[0133] Therefore, as long as The circuit exhibits the reverse characteristics of an ideal diode while also preventing damage to the PMOS transistor.

[0134] based on Figure 2 , Figure 5 and Figure 6 In one possible implementation of the illustrated embodiment, the reverse breakdown voltage of the first transistor satisfies:

[0135] V BR(CEO) >V CA(max) -V F

[0136] Among them, V CA(max) V is the maximum voltage difference between point C and point A. BR(CEO) V is the reverse breakdown voltage of the first transistor mentioned above; F The on-state voltage drop of the second current direction selection sub-circuit.

[0137] When V C >V A When transistor Q2 or diode D1 is turned on, V D ≈V C Because V C >V A When transistor Q1 is cut off, the voltage difference between the source and gate of PMOS transistor N1 is very small, so PMOS transistor N1 is also cut off, and the circuit exhibits a high-impedance state. In other words, the circuit is cut off at this time and can exhibit the reverse characteristics of an ideal diode.

[0138] The reverse voltage between the source and gate of PMOS transistor N1 must be less than the reverse breakdown voltage of the PMOS transistor.

[0139] Transistor Q1 needs to withstand a reverse voltage, which is: V C -V F -V A Among them, V C -V A The voltage difference between point C and point A;

[0140] To prevent transistor Q1 from being damaged:

[0141] V BR(CEO) >V CA(max) -V F

[0142] As long as V BR(CEO) >V C(max) -V F -V A(nax)The circuit exhibits the reverse characteristics of an ideal diode while also preventing damage to transistor Q1.

[0143] This application provides an electronic device, which includes the circuit described in any of the above embodiments.

[0144] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0145] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0146] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. An ideal diode circuit, characterized in that, The circuit includes: First transistor subcircuit, first protection subcircuit, first current direction selection subcircuit, second current direction selection subcircuit, second protection subcircuit, third protection subcircuit; The circuit also includes a fourth protection sub-circuit; The first transistor sub-circuit includes a PMOS transistor; the first protection sub-circuit includes a first resistor; the first current direction selection sub-circuit includes a first transistor; the second current direction selection sub-circuit includes a second transistor or a second diode; the second protection sub-circuit includes a second resistor; the third protection sub-circuit includes a third resistor; the fourth protection sub-circuit includes a fourth resistor and a third transistor; the first transistor and the second transistor are both P-type transistors; the third transistor is an N-type transistor. The drain of the PMOS transistor is connected to the first terminal and the emitter of the first transistor, respectively. The source of the PMOS transistor is connected to one end of the first resistor, the second terminal, and the emitter of the second transistor or the positive terminal of the second diode, respectively. The gate of the PMOS transistor is connected to the other end of the first resistor and one end of the fourth resistor, respectively. The first terminal is one end of the power supply line, and the second terminal is the other end of the power supply line. The other end of the fourth resistor is connected to the collector of the third transistor; The base of the third transistor is connected to the collector of the first transistor and one end of the second resistor, respectively; the emitter of the third transistor is grounded. The base of the first transistor is connected to the base of the second transistor or the cathode of the second diode; The collector of the second transistor is connected to the base of the second transistor and one end of the third resistor; or the cathode of the second diode is connected to one end of the third resistor. The other end of the second resistor is grounded; the other end of the third resistor is grounded. The resistance values ​​of the first resistor and the fourth resistor satisfy the following: ; Where R1 is the resistance of the first resistor, and R4 is the resistance of the fourth resistor. The maximum voltage at point C. This is the reverse breakdown voltage of the PMOS transistor.

2. The circuit according to claim 1, characterized in that, The reverse breakdown voltage of the first transistor satisfies: ; in, The maximum voltage difference between point C and point A. This is the reverse breakdown voltage of the first transistor; The on-state voltage drop of the second current direction selection sub-circuit.

3. An electronic device, characterized in that, The electronic device includes the circuit according to any one of claims 1-2.

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