Method for manufacturing a magnetic random access memory and magnetic random access memory
By introducing a carbon-containing dielectric layer during the MRAM manufacturing process, the Arc phenomenon in the MTJ etching process was solved, improving device performance and yield, and enabling high-precision and high-sensitivity MRAM manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG HIKSTOR TECHOGY CO LTD
- Filing Date
- 2021-11-23
- Publication Date
- 2026-07-21
AI Technical Summary
In the prior art, magnetic random access memory (MRAM) exhibits a high Arc phenomenon during MTJ etching, leading to device performance degradation and insufficient yield, which is difficult to alleviate effectively.
A carbon-containing dielectric layer is introduced during the etching process of the MTJ film to create an atmosphere conducive to charge conduction and release, ensuring that the charge is released rapidly during the etching process. Charge accumulation is controlled through multiple etching and deposition steps, reducing Arc risk.
It effectively alleviates the Arc phenomenon during the MTJ etching process, improves device performance and yield, reduces device damage and short circuit risk, and ensures high-precision and high-sensitivity MRAM manufacturing.
Smart Images
Figure CN116171098B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory, and more specifically, to a method for manufacturing a magnetic random access memory and the magnetic random access memory itself. Background Technology
[0002] With the rapid development of electronic technology, non-volatile memory has become a key research focus. Non-volatile memory, characterized by high density, fast read / write speeds, and ultra-long lifespan, has broad market application prospects. Magnetic random access memory (MRAM), as a representative of the next generation of non-volatile memory, is currently the most promising candidate for mass production.
[0003] In the manufacturing process of magnetic random access memory (MRAM), the MTJ etching process is crucial to the mass production of MRAM. Numerous etching defects, such as arc discharge, can cause serious damage and defects to MTJ products. These problems range from affecting morphological uniformity to causing breakdowns and short circuits, hindering further improvements in MRAM device performance and yield. These are significant challenges that MTJ etching must overcome and real-world problems that must be solved. The Arc phenomenon during MTJ etching is primarily caused by inadequate charge release during the etching process.
[0004] In the existing structural design, MTJ etching can mitigate the arc discharge phenomenon by reducing the etching rate and extending the etching pause time, but it still carries a high risk of arcing.
[0005] Therefore, there is an urgent need for a better way to alleviate the Arc problem.
[0006] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention
[0007] The main objective of this application is to provide a method for manufacturing a magnetic random access memory (RAM) and a magnetic RAM itself, in order to solve the problem of the Arc problem that is difficult to alleviate in the prior art.
[0008] To achieve the above objectives, according to one aspect of this application, a method for fabricating a magnetic random access memory (MRMemory) is provided, comprising: providing a substrate, the substrate including a plurality of bottom electrodes spaced apart and an insulating dielectric layer located between any two adjacent bottom electrodes, the exposed surfaces of the bottom electrodes and the insulating dielectric layer being on a predetermined plane; sequentially forming a plurality of MTJ film layers on the exposed surfaces of the substrate; etching away at least a portion of each of the MTJ film layers and a C-containing dielectric layer to form a plurality of spaced MTJ bits, wherein the C-containing dielectric layer is a material layer formed on the surface of at least one of the MTJ film layers during the formation of the MTJ bits.
[0009] Furthermore, the plurality of the aforementioned MTJ film layers sequentially include at least a reference layer, a tunneling layer, and a free layer in a direction away from the aforementioned substrate. Etching away at least a portion of each of the aforementioned MTJ film layers and the C-containing dielectric layer includes: etching away at least a portion of the aforementioned MTJ film layer to form the aforementioned C-containing dielectric layer on the formed exposed surface; and at least etching away the aforementioned C-containing dielectric layer to form a plurality of spaced MTJ bits.
[0010] Further, etching away at least one portion of the aforementioned MTJ film layer to form the aforementioned C-containing dielectric layer on the formed exposed surface includes: etching away portions of each of the aforementioned MTJ film layers, exposing portions of the predetermined plane of the substrate where no aforementioned MTJ film layer is disposed; forming a first C-containing dielectric layer at least on the exposed predetermined plane and on the exposed surface of each of the aforementioned MTJ film layers; and etching away at least the aforementioned C-containing dielectric layer to form a plurality of spaced MTJ bits, including: etching away the aforementioned first C-containing dielectric layer and a portion of the aforementioned insulating dielectric layer to form a plurality of spaced MTJ bits.
[0011] Further, etching away at least one portion of the aforementioned MTJ film layer to form a C-containing dielectric layer on the formed exposed surface includes: etching away a portion of the free layer, exposing a portion of the surface of the tunneling layer; forming a second C-containing dielectric layer at least on the exposed surface of the tunneling layer and the exposed surface of the free layer; etching away at least the C-containing dielectric layer to form a plurality of spaced MTJ bits, including: etching away the second C-containing dielectric layer and a portion of the tunneling layer, exposing a portion of the surface of the reference layer; forming a third C-containing dielectric layer at least on the exposed surface of the reference layer and the exposed surfaces of the free layer and the tunneling layer; etching away the third C-containing dielectric layer, a portion of the reference layer, and a portion of the insulating dielectric layer to form a plurality of spaced MTJ bits.
[0012] Furthermore, before etching away at least one portion of the aforementioned MTJ film layer and forming the aforementioned C-containing dielectric layer on the formed exposed surface, etching away at least portions of each of the aforementioned MTJ film layers and the C-containing dielectric layer to form a plurality of spaced MTJ bits, further comprising: forming a plurality of spaced mask portions on the exposed aforementioned MTJ film layers, the mask portions being used to protect portions of each of the aforementioned MTJ film layers from being removed, the aforementioned C-containing dielectric layer also being formed on the exposed surface of the aforementioned mask portions.
[0013] Furthermore, after forming a plurality of spaced mask portions on the exposed MTJ film layers, etching away at least each of the MTJ film layers and the C-containing dielectric layer to form a plurality of spaced MTJ bits, the method further includes: forming a fourth C-containing dielectric layer on the exposed surface of the mask portions and the exposed surface of the MTJ film layers; etching away portions of each of the MTJ film layers and the fourth C-containing dielectric layer to form a plurality of spaced MTJ bits.
[0014] Furthermore, the ratio of the thickness of the removed insulating dielectric layer to the total thickness of the insulating dielectric layer is greater than 0.2.
[0015] Furthermore, the substrate also includes a plurality of metal interconnects, which are located one-to-one on the surface of the bottom electrode away from the MTJ film layer. The critical dimension of the metal interconnect is smaller than the critical dimension of the corresponding bottom electrode, and the minimum distance between the projection of the metal interconnect on the corresponding bottom electrode and the boundary of the bottom electrode is greater than a predetermined distance, which is greater than 0.
[0016] Furthermore, in the aforementioned C-containing dielectric layer, the weight ratio of C is greater than or equal to 20%.
[0017] Furthermore, the dielectric constant of the aforementioned C-containing dielectric layer is between 2 and 7.
[0018] Furthermore, the thickness of the aforementioned C-containing dielectric layer is between 30 and 100 nm.
[0019] According to another aspect of this application, a magnetic random access memory is provided, which is manufactured using any of the above-described manufacturing methods.
[0020] Applying the technical solution of this application, firstly, a substrate is provided comprising a plurality of spaced-apart bottom electrodes and an insulating dielectric layer located between any two adjacent bottom electrodes, wherein the exposed surfaces of the bottom electrodes and the insulating dielectric layer are on the same plane, i.e., on a predetermined plane; then, a plurality of MTJ films are formed on the exposed surfaces of the substrate; finally, portions of each MTJ film and a C-containing dielectric layer are removed to form a plurality of MTJ bits, and, during the formation of the MTJ bits, a C-containing dielectric layer is formed on the surface of at least one of the MTJ films. In this method, during the etching process to form the MTJ bits, the addition of a C-containing dielectric layer creates an atmosphere conducive to charge conduction and release. As the MTJ films are gradually etched apart, the charge is always in a state of rapid release until it is completely disconnected, thus mitigating the Arc phenomenon during the MTJ etching process. Attached Figure Description
[0021] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0022] Figure 1 This illustration shows a schematic diagram of the structure after multiple MTJ film layers are sequentially formed on a predetermined plane on the exposed surface of a substrate, according to a typical embodiment of this application.
[0023] Figure 2 It is shown as in Figure 1 A schematic diagram of the structure after a C-containing dielectric layer is formed on the exposed surface;
[0024] Figure 3 It shows the removal Figure 2 A schematic diagram of the structure formed after the C dielectric layer and the insulating dielectric layer are partially included;
[0025] Figure 4 This illustration shows a schematic diagram of the structure of a substrate with a high-density small BV structure after multiple MTJ film layers are sequentially formed on a predetermined plane on the exposed surface of the substrate in one embodiment of this application.
[0026] Figure 5 It is shown as in Figure 4 A schematic diagram of the structure after a C-containing dielectric layer is formed on the exposed surface;
[0027] Figure 6 It shows the removal Figure 5 A schematic diagram of the structure formed after the C dielectric layer and the insulating dielectric layer are partially included;
[0028] Figure 7This illustration shows a schematic diagram of the effect of forming a fourth C-containing dielectric layer on the exposed surface of the mask portion and the exposed surface of the free layer in one embodiment of this application;
[0029] Figure 8 It shows the removal Figure 7 A schematic diagram of the structure after the middle free layer and the C-containing dielectric layer;
[0030] Figure 9 It shows in Figure 8 A schematic diagram illustrating the effect of forming a C-containing dielectric layer on an exposed surface;
[0031] Figure 10 It shows the removal Figure 9 A schematic diagram of the structure after the C dielectric layer and the tunneling layer are shown in part.
[0032] Figure 11 It shows in Figure 10 A schematic diagram illustrating the effect of forming a C-containing dielectric layer on an exposed surface;
[0033] Figure 12 It shows the removal Figure 10 The diagram shows the structure after the C dielectric layer, reference layer, and insulating dielectric layer are included.
[0034] The above figures include the following reference numerals:
[0035] 110. Bottom electrode; 111. Insulating dielectric layer; 112. Reference layer; 113. Tunneling layer; 114. Free layer; 115. Hard mask section; 116. C-containing dielectric layer; 117. Redeposited material; 118. Metal interconnect section; 1151. Metal mask layer; 1152. Oxide mask layer. Detailed Implementation
[0036] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0037] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0038] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.
[0039] As described in the background section, there is a high risk of arcing during the MTJ etching process in the prior art. In order to solve the above technical problems, this application proposes a fabrication method and a magnetic random access memory.
[0040] In a typical embodiment of this application, a method for fabricating a magnetic random access memory is provided. The method includes: providing a substrate, the substrate comprising a plurality of spaced-apart bottom electrodes 110 and an insulating dielectric layer 111 located between any two adjacent bottom electrodes 110, such as... Figure 1 As shown, the exposed surfaces of the bottom electrode 110 and the insulating dielectric layer 111 are on a predetermined plane; a plurality of MTJ films are sequentially formed on the exposed surface of the substrate; at least a portion of each of the MTJ films and the C-containing dielectric layer 116 are etched away to form a plurality of spaced MTJ bits, as shown. Figure 2 and Figure 3 As shown, the C-containing dielectric layer 116 is a material layer formed on the surface of at least one of the MTJ films during the formation of the MTJ bits.
[0041] In the above fabrication method, firstly, a substrate is provided comprising a plurality of spaced-apart bottom electrodes and an insulating dielectric layer located between any two adjacent bottom electrodes, wherein the exposed surfaces of the bottom electrodes and the insulating dielectric layer are on the same plane, i.e., on a predetermined plane; then, a plurality of MTJ films are formed on the exposed surfaces of the substrate; finally, portions of each MTJ film and a C-containing dielectric layer are removed to form a plurality of MTJ bits, and, during the formation of the MTJ bits, a C-containing dielectric layer is formed on the surface of at least one of the MTJ films. In this method, the addition of a C-containing dielectric layer during the etching process to form the MTJ bits creates an atmosphere conducive to charge conduction and release. As the MTJ films are gradually etched apart, the charge is always in a state of rapid release until it is completely disconnected, thus mitigating the Arc phenomenon during the MTJ etching process.
[0042] In one specific embodiment of this application, the process of forming the substrate includes: firstly, forming multiple spaced bottom electrodes on the substrate, and forming a discontinuous structure through photolithography and etching processes, wherein the BECD size can be 150-250 nm. Then, an insulating dielectric layer is formed on the exposed surfaces of the bottom electrodes and the substrate using PECVD, specifically including but not limited to SiO2, SiON, SiN, and SiCN, with a thickness of 20-100 nm and a temperature of 200-300 °C; subsequently, the insulating dielectric layer on a predetermined plane is removed using CMP to form the substrate.
[0043] In one specific embodiment of this application, the aforementioned C-containing dielectric layer is formed using a CVD deposition method. Specific materials include, but are not limited to, SiCN, SiC, and SiOC. The silicon source used for CVD deposition includes, but is not limited to, SiH4, K5, and TSA. The reaction temperature can be 150–200°C, and the thickness can be 30–100 nm. When forming the aforementioned MTJ bits, the etching amount of the insulating dielectric layer can account for more than 30% of the total thickness.
[0044] The method for forming the C-containing dielectric layer described in this application is not limited to CVD, but can also be PECVD, ALD, etc. Those skilled in the art can select an appropriate formation method based on the specific circumstances.
[0045] The method for etching away the C-containing dielectric layer in this application includes forming a redeposited material 117, which is mainly concentrated around the periphery of each film layer of the MTJ. Specifically, the etching process primarily employs low-energy, small-angle bombardment. This method allows the already formed redeposited material 117 to be positioned appropriately, while reducing energy also decreases the amount of redeposited material and cleans the MTJ sidewalls.
[0046] In one embodiment of this application, the plurality of MTJ films, arranged sequentially from a direction away from the substrate, include at least a reference layer 112, a tunneling layer 113, and a free layer 114. The fabrication method, involving etching away at least a portion of each of the MTJ films and the C-containing dielectric layer 116, includes: etching away at least a portion of the MTJ films to form the C-containing dielectric layer 116 on the formed exposed surface; and at least etching away the C-containing dielectric layer 116 to form a plurality of spaced MTJ bits, such as... Figure 3 , Figure 8 , Figure 10 and Figure 12 As shown. In this embodiment, after etching away at least one portion of the MTJ film, the aforementioned C-containing dielectric layer 116 is formed on the formed bare surface, so that electrons released by etching and electrons to be released during the etching process can be released quickly, thereby better mitigating the Arc phenomenon during the MTJ etching process.
[0047] In one embodiment of this application, the above-described fabrication method, involving etching away at least one portion of the aforementioned MTJ film layer to form the C-containing dielectric layer 116 on the exposed surface, includes: etching away portions of each of the aforementioned MTJ film layers, thereby exposing portions of the substrate on which the predetermined planes are not provided with the aforementioned MTJ film layers, such as... Figure 1 As shown; a first C-containing dielectric layer 116 is formed at least on the exposed predetermined plane and on the exposed surface of each of the above-mentioned MTJ films, as shown. Figure 2 As shown. At least the C-containing dielectric layer 116 is etched away to form a plurality of spaced MTJ bits, including: etching away the first C-containing dielectric layer 116 and a portion of the insulating dielectric layer 111 to form a plurality of spaced MTJ bits, as shown. Figure 3 As shown, etching removes the C-containing dielectric layer and part of the insulating dielectric layer, completely disconnecting the MTJ pillar and thus forming multiple spaced MTJ bits.
[0048] In the above embodiment, after removing portions of each MTJ film layer during MTJ etching, a C-containing dielectric layer 116 is formed on the exposed surface. Firstly, this method can precisely control the etching to stop on a predetermined plane using endpoint determination, thus reducing fabrication difficulty and improving efficiency. Secondly, when the equipment is sensitive to the Arc phenomenon or discharge current, even slight charge accumulation can damage the equipment's electronic components. This method, by etching each MTJ film layer and then forming the C-containing dielectric layer, allows for the conduction and release of minute-level accumulated charges, meeting the high precision and high sensitivity requirements of the equipment, and thus can be applied to the fabrication of high-sensitivity MRAM. Thirdly, because this method involves etching each MTJ film layer and then forming the C-containing dielectric layer, electrons released during previous etching and those released during subsequent etching processes can be quickly released through the C-containing dielectric layer, thereby better mitigating severe Arc phenomena.
[0049] In one specific embodiment of this application, the MTJ functional layer etching is divided into two steps. The first step, ME main etching, is performed using the IBE method. The etching uses plasma of dissociated elements such as Ar, Kr, or Xe for physical bombardment. At the same time, OES (Optical Emission Spectrum) is used to determine the endpoint of the first step, and the etching endpoint stops at the interface between the bottom electrode and the insulating dielectric layer. The second step, dielectric etching, is performed using IBE or RIE for low-energy etching. IBE includes, but is not limited to, physical bombardment of plasma of elements such as Ar, Kr, or Xe. RIE uses reactive gases including, but not limited to, CH3OH+Ar, CO / NH3+Ar, C2H5OH+Ar. The etching depth is controlled within the range of 30% to 100% of the total thickness of the insulating dielectric layer.
[0050] In another embodiment of this application, in the above-described fabrication method, etching away at least one portion of the MTJ film layer to form a C-containing dielectric layer on the exposed surface includes: etching away a portion of the free layer 114, exposing a portion of the surface of the tunneling layer 113, forming a C-containing dielectric layer. Figure 8 The structure shown; at least on the exposed surface of the tunneling layer 113 and the exposed surface of the free layer 114, a second C-containing dielectric layer 116 is formed, as shown. Figure 9 As shown. At least the C-containing dielectric layer 116 is etched away to form a plurality of spaced MTJ bits, including: etching away the second C-containing dielectric layer 116 and a portion of the tunneling layer 113, exposing the surface of the reference layer 112, as shown. Figure 10 As shown; a third C-containing dielectric layer 116 is formed at least on the exposed surface of the reference layer 112 and on the exposed surfaces of the free layer 114 and the tunneling layer 113, as shown. Figure 11 As shown; etching removes the third C-containing dielectric layer 116, a portion of the reference layer 112, and a portion of the insulating dielectric layer 111, as shown. Figure 12 As shown, multiple spaced MTJ bits are formed. In this embodiment, after etching each MTJ film layer, a C-containing dielectric layer is formed on the exposed surface. This allows for better release of electrons formed during etching or those generated during subsequent etching processes, thereby better mitigating the Arc phenomenon.
[0051] Of course, in practical applications, the MTJ film layer is not limited to the above-mentioned scheme and can also include other magnetic material layers. The specific structure can be a single-layer barrier structure, a double-layer barrier structure, or other structures. The connection between the upper and lower electrodes of the MTJ includes, but is not limited to, metal structures such as TM / TV / TE / MTJ / BE / BV / BM, TM / TV / TE / MTJ / BV / BM, TM / TV / MTJ / BE / BV / BM, and TM / TV / MTJ / BV / BM. Those skilled in the art can form suitable multiple MTJ films according to the actual situation. During subsequent etching, a C-containing dielectric layer can be formed after etching each MTJ film layer to better mitigate the Arc phenomenon.
[0052] In one embodiment of this application, in the above-described fabrication method, before forming the C-containing dielectric layer on the formed exposed surface after etching away at least one of the MTJ film layers, at least each of the MTJ film layers and the C-containing dielectric layer is etched away to form a plurality of spaced MTJ bits. The method further includes forming a plurality of spaced hard mask portions 115 on the exposed MTJ film layers, such as... Figure 1As shown, the hard mask portion 115 is used to protect portions of each of the aforementioned MTJ film layers from being removed, and the C-containing dielectric layer 116 is also formed on the exposed surface of the mask portion. In this embodiment, the C-containing dielectric layer 116 is formed on the exposed surface of the mask portion, so that during the etching of the free layer 114, the released electrons can be conducted and released through the C-containing dielectric layer 116, thereby better mitigating the Arc phenomenon.
[0053] The aforementioned mask portion can be formed from photoresist or other materials suitable for use as a mask portion. In one specific embodiment, the mask portion is a hard mask portion, which can be formed into a double-layer structure of metal and oxide, wherein the lower layer is a metal mask material and the upper layer is an oxide mask material, with a total height of 100-200 nm. By covering the dielectric film, the mask portion can also form a protective layer for the free layer, thereby further reducing the damage of etching to the magnetic layer and increasing device reliability.
[0054] The dielectric layer covered by the hard mask interface described above can significantly reduce the connectivity of conductive materials to the MgO insulating dielectric layer, thereby preventing the adhesion of redeposited material generated by the bottom electrode to the free layer and thus improving device performance.
[0055] In one specific embodiment of this application, an MTJ functional layer and a double-layer hard mask (HM) layer are formed on the substrate, such as... Figure 4 As shown, the above-mentioned double-layer hard mask has a lower layer of metal mask layer 1151 (Oxide Hard Mask: M-HM), the material of which includes, but is not limited to, Ta, TiN, Ta / Ru / Ta, etc., and an upper layer of oxide mask layer 1152 (Metal Hard Mask: M-HM O-HM), the material of which includes, but is not limited to, SiO2, SiN, SiC, SiON, SiCN, etc., wherein the thickness of M-HM is approximately 20-40 nm, and the thickness of O-HM is approximately 200 nm-300 nm. HM etching is performed using CFx-based plasma, including, but not limited to, CF4, C4F8, C4F6, SF6, etc., and the HM CD size is controlled within the range of 40-70 nm, and the final remaining thickness of HM is controlled within the range of 40-60 nm. The aforementioned redeposition can be further avoided by reshaping the HM Profile: before the MTJ etching process, an insulating dielectric layer, including but not limited to SiO2, SiON, SiN, and SiCN, is first deposited around the HM Pattern. This insulating dielectric layer can have a thickness of 10–100 nm. This method allows a large amount of insulating redeposited material generated during the etching process to adhere around the MgO insulating dielectric layer, thereby avoiding the adhesion of conductive dielectrics and the conduction phenomenon of the MgO tunneling layer, thus reducing the occurrence of short circuits.
[0056] In one embodiment of this application, after forming a plurality of spaced mask portions on the exposed MTJ film layer, at least each of the MTJ film layer and the C-containing dielectric layer are etched away to form a plurality of spaced MTJ bits. The method further includes forming a fourth C-containing dielectric layer 116 on the exposed surface of the mask portions and on the exposed surface of the MTJ film layer. Figure 7 As shown; etching removes portions of each of the aforementioned MTJ films and the aforementioned fourth C-containing dielectric layer 116, forming a plurality of spaced MTJ bits, as shown. Figures 8 to 11 As shown or as Figure 2 and Figure 3 As shown.
[0057] In order to ensure that the shape and size of the formed MTJ bits are the predetermined shape and size, in one embodiment of this application, the ratio of the thickness of the removed insulating dielectric layer to the total thickness of the insulating dielectric layer is greater than 0.2.
[0058] In another embodiment of this application, the substrate further includes a plurality of metal interconnects 118 (BV), such as Figure 4 As shown, the material of the metal interconnect 118 includes, but is not limited to, Cu, Ta, TaN, W, etc. The metal interconnects 118 are located one-to-one on the surface of the bottom electrode 110 away from the MTJ film layer. The critical dimension of each metal interconnect is smaller than the critical dimension of the corresponding bottom electrode 110, and the minimum distance between the projection of the metal interconnect 118 onto the corresponding bottom electrode 110 and the boundary of the bottom electrode 110 is greater than a predetermined distance. This predetermined distance being greater than 0 is beneficial for forming a high-density MRAM.
[0059] To better form a discharge channel and thus better release electrons to alleviate the Arc phenomenon, in one embodiment of this application, the aforementioned C-containing dielectric layer 116, as follows: Figure 1 As shown, the weight ratio of C is greater than or equal to 20%.
[0060] In order to improve conductivity and thus form a discharge channel, thereby better releasing electrons and better mitigating the Arc phenomenon, in one embodiment of this application, the dielectric constant of the C-containing dielectric layer 116 is between 2 and 7.
[0061] In one embodiment of this application, the thickness of the C-containing dielectric layer 116 is between 30 and 100 nm. Figure 1 As shown, this not only forms a good conductive channel, but also ensures that there are no residues caused by an excessively thick C-containing dielectric layer 116, thus ensuring that the MTJ bits have good performance.
[0062] In another typical embodiment of this application, a magnetic random access memory is provided, which is prepared by any of the above-described manufacturing methods.
[0063] Because the magnetic random access memory is fabricated using the above-mentioned method, the Arc phenomenon during the fabrication process can be well mitigated. This effectively alleviates the problem of poor device performance caused by the Arc phenomenon, ensuring minimal damage to the device and reducing the likelihood of short circuits, thus resulting in good performance.
[0064] To enable those skilled in the art to better understand the technical solution of this application, the technical solution of this application will be described in detail below with reference to specific embodiments and comparative examples.
[0065] Example 1
[0066] The method for fabricating the magnetic random access memory in this embodiment includes the following steps:
[0067] Provides a high-density substrate with small BV, such as Figure 4 As shown, the substrate includes a plurality of bottom electrodes 110 spaced apart and an insulating dielectric layer 111 located between any two adjacent bottom electrodes 110, with the exposed surfaces of the bottom electrodes 110 and the insulating dielectric layer 111 on a predetermined plane.
[0068] An MTJ film is deposited on a predetermined plane, consisting of a reference layer 112, a tunneling layer 113, a free layer 114, and a hard mask portion 115 from bottom to top. The mask portion is composed of a metal mask layer 1151 and an oxide mask layer 1152, and the total height of the hard mask portion is 100–200 nm. An HM pattern is formed after exposure and development.
[0069] A protective film is applied to the hard mask using methods such as CVD, ALD, or PECVD. The film material is an insulating dielectric material, including but not limited to SiOX, SiN, SiCO, SiC, and SiCN. The protective dielectric layer is tightly adhered to the hard mask. Specifically, the hard mask can be formed using CFx-based plasma etching, where CFx includes but is not limited to CF4, C4F8, C4F6, and SF6. The size of the hard mask is controlled within the range of 40–70 nm, and the final remaining thickness of the hard mask is controlled within the range of 40–60 nm.
[0070] Next, MTJ etching is performed, which is done in two steps.
[0071] The first step, main etching, employs IBE etching. This involves physical bombardment with plasma containing dissociated elements such as Ar, Kr, or Xe, and the etching termination position is controlled at the interface between the MTJ bottom electrode 110 and the insulating dielectric layer 111 using OSE endpoint determination. Then, an ALD or PECVD method is used to deposit a C-containing dielectric layer 116 with a thickness of 30–50 nm at the interface between the insulating dielectric layer 111 and the bottom electrode 110. Figure 5 As shown, the deposited Si source precursors include, but are not limited to, K5, TSA, SiH4, etc., and the synthesized thin film materials include, but are not limited to, SiCN, SiC, SiOC, etc. The C content in the carbon-containing dielectric layer accounts for more than 20% of the total molecular weight. The film layer has a low dielectric constant k, with a value between 2.0 and 7.0, and the deposition temperature is 200 to 300℃.
[0072] The second step, dielectric etching, employs low-energy etching using either IBE or RIE. IBE includes, but is not limited to, plasma physical bombardment with elements such as Ar, Kr, or Xe. RIE uses reactive gases including, but not limited to, CH3OH+Ar, CO / NH3+Ar, and C2H5OH+Ar. It primarily etches the C-containing dielectric layer 116 and the insulating dielectric layer 111. Etching stops when the insulating dielectric layer 111 has been etched to a height of 30%–60%, forming MTJ bits. Figure 6 As shown. The secondary etching uses low energy and a small-angle bombardment, primarily to position the already formed redeposited material 117 in a suitable location. Reducing energy also helps to decrease the amount of redeposited material 117 and clean the MTJ sidewalls. An etching depth of 30%–60% of the total insulating dielectric layer height further eliminates the short-circuit risk caused by the redeposited material.
[0073] Finally, a 10–50 nm protective film is deposited using ALD or PECVD to provide real-time protection for the MTJ sites. The protective film includes, but is not limited to, SiN, SiCN, SiOC, etc., and the precursors or reactants include, but are not limited to, SiH4, K5, TSA, etc., with the temperature control range being 200–300 °C.
[0074] Example 2
[0075] The method for fabricating the magnetic random access memory in this embodiment includes the following steps:
[0076] Provide a substrate, such as Figure 1 As shown, the substrate includes a plurality of bottom electrodes 110 spaced apart and an insulating dielectric layer 111 located between any two adjacent bottom electrodes 110, with the exposed surfaces of the bottom electrodes 110 and the insulating dielectric layer 111 on a predetermined plane.
[0077] An MTJ film is deposited on a predetermined plane, consisting of a reference layer 112, a tunneling layer 113, a free layer 114, and a hard mask portion 115, from bottom to top. An HM pattern is formed after exposure and development.
[0078] A protective film is applied to the hard mask using methods such as CVD, ALD, or PECVD. The film material is an insulating dielectric material, including but not limited to SiOX, SiN, SiCO, SiC, and SiCN. The protective dielectric layer is tightly adhered to the hard mask. Specifically, the hard mask can be formed using CFx-based plasma etching, where CFx includes but is not limited to CF4, C4F8, C4F6, and SF6. The size of the hard mask is controlled within the range of 40–70 nm, and the final remaining thickness of the hard mask is controlled within the range of 40–60 nm.
[0079] Next, a 15–100 nm carbon-containing insulating dielectric layer is deposited around the HM pattern using ALD or PECVD methods, such as... Figure 7 As shown, the deposited Si source precursors include, but are not limited to, K5, TSA, SiH4, etc., and the synthesized thin film materials include, but are not limited to, SiCN, SiC, SiOC, etc. The C content in the carbon-containing dielectric layer accounts for more than 20% of the total molecular weight. This film layer has a low dielectric constant k, with a value between 2.0 and 7.0, and the deposition temperature is 200 to 300℃. IBE etching is used, and physical bombardment is performed using plasma of dissociated elements such as Ar, Kr, or Xe. The etching termination position is controlled at the interface between the free layer 114 and the reference layer 112 by using OSE endpoint determination or fixing the etching time and etching depth ratio. Figure 8 structure;
[0080] Next, a second carbon-containing dielectric layer is deposited on the reference layer, free layer, and hard mask, such as... Figure 9 As shown, a second IBE etching is then performed, with the endpoint controlled at the interface between the tunneling layer 113 and the reference layer 112, resulting in the following... Figure 10 The structure shown;
[0081] Next, a third carbon-containing dielectric layer is deposited on the reference layer, tunneling layer, free layer, and hard mask, such as... Figure 11 As shown, three IBE etching processes were then performed, with etching stopping when the etching depth of the insulating dielectric layer 111 exceeded 20%, resulting in the following... Figure 12 The MTJ bit structure is shown.
[0082] Finally, a 10–50 nm protective film is deposited using ALD or PECVD to provide real-time protection for the MTJ sites. The protective film includes, but is not limited to, SiN, SiCN, SiOC, etc., and the precursors or reactants include, but are not limited to, SiH4, K5, TSA, etc., with the temperature control range being 200–300 °C.
[0083] The above method involves a total of three thin film depositions, but is not limited to three. The number of protective film depositions can be set to n, where n = 1, 2, 3, 4..., and the value of n depends on the process stability control capability and production capacity control. This method can minimize the damage to MTJ bits.
[0084] As can be seen from the above description, the embodiments of this application achieve the following technical effects:
[0085] 1) In the fabrication method of this application, firstly, a substrate is provided comprising a plurality of bottom electrodes spaced apart and an insulating dielectric layer located between any two adjacent bottom electrodes, wherein the exposed surfaces of the bottom electrodes and the insulating dielectric layer are on the same plane, i.e., on a predetermined plane; then, a plurality of MTJ film layers are formed on the exposed surface of the substrate; finally, portions of each MTJ film layer and a C-containing dielectric layer are removed to form a plurality of MTJ bits, and, during the formation of the MTJ bits, a C-containing dielectric layer is formed on the surface of at least one of the MTJ film layers. In this method, during the etching process to form the MTJ bits, the addition of the C-containing dielectric layer creates an atmosphere conducive to charge conduction and release. As the MTJ film layers are gradually etched apart, the charge is always in a state of rapid release until it is completely disconnected, thus mitigating the Arc phenomenon during the MTJ etching process.
[0086] 2) Since the magnetic random access memory of this application is formed by the above-mentioned manufacturing method, the Arc phenomenon during the formation process can be well mitigated, thereby effectively alleviating the problem of poor device performance caused by the Arc phenomenon and ensuring that the device has good performance.
[0087] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for manufacturing a magnetic random access memory, characterized in that, include: A substrate is provided, the substrate comprising a plurality of bottom electrodes spaced apart and an insulating dielectric layer located between any two adjacent bottom electrodes, the exposed surfaces of the bottom electrodes and the insulating dielectric layer being on a predetermined plane; Multiple MTJ film layers are sequentially formed on the exposed surface of the substrate; Etching removes at least a portion of each of the MTJ film layers and the C-containing dielectric layer to form a plurality of spaced MTJ bits, wherein the C-containing dielectric layer is a material layer formed on the surface of at least one of the MTJ film layers during the formation of the MTJ bits; The etching process for removing the portion of the MTJ film and the etching process for removing the C-containing dielectric layer are performed multiple times. The portion of the MTJ film etched in each etching process is different. After each etching process, the C-containing dielectric layer is formed on the exposed surface. The portion of the MTJ film covered by the C-containing dielectric layer is etched away during the etching process.
2. The manufacturing method according to claim 1, characterized in that, The MTJ film layer, in the direction away from the substrate, includes at least a reference layer, a tunneling layer, and a free layer in sequence.
3. The manufacturing method according to claim 2, characterized in that, Etching away at least one portion of the MTJ film layer to form a C-containing dielectric layer on the formed bare surface includes: Etching removes a portion of the free layer, exposing a portion of the surface of the tunneling layer; A second C-containing dielectric layer is formed at least on the exposed surface of the tunneling layer and on the exposed surface of the free layer. At least the C-containing dielectric layer is etched away to form a plurality of spaced MTJ bits, including: The second C-containing dielectric layer and a portion of the tunneling layer are etched away, exposing a portion of the surface of the reference layer. A third C-containing dielectric layer is formed at least on the exposed surface of the reference layer and on the exposed surfaces of the free layer and the tunneling layer; The third C-containing dielectric layer, a portion of the reference layer, and a portion of the insulating dielectric layer are etched away to form a plurality of spaced MTJ bits.
4. The manufacturing method according to claim 2 or 3, characterized in that, Before forming the C-containing dielectric layer on the formed exposed surface, at least portions of each of the MTJ film layers and the C-containing dielectric layer are etched away to form a plurality of spaced MTJ bits. The process further includes forming a plurality of spaced mask portions on the exposed MTJ film layers, the mask portions serving to protect portions of each of the MTJ film layers from being removed. The C-containing dielectric layer is also formed on the exposed surface of the mask portion.
5. The manufacturing method according to claim 4, characterized in that, After forming a plurality of spaced mask portions on the exposed MTJ film, etching away at least each of the MTJ film and the C-containing dielectric layer to form a plurality of spaced MTJ bits, further comprising: A fourth C-containing dielectric layer is formed on the exposed surface of the mask portion and on the exposed surface of the MTJ film layer; Etching removes portions of each of the MTJ film layers and the fourth C-containing dielectric layer to form a plurality of spaced MTJ bits.
6. The manufacturing method according to claim 4, characterized in that, The ratio of the thickness of the removed insulating dielectric layer to the total thickness of the insulating dielectric layer is greater than 0.
2.
7. The manufacturing method according to any one of claims 1 to 3, characterized in that, The substrate further includes a plurality of metal interconnects, which are located one-to-one on the surface of the bottom electrode away from the MTJ film layer. The critical dimension of the metal interconnect is smaller than the critical dimension of the corresponding bottom electrode, and the minimum distance between the projection of the metal interconnect on the corresponding bottom electrode and the boundary of the bottom electrode is greater than a predetermined distance, which is greater than 0.
8. The manufacturing method according to any one of claims 1 to 3, characterized in that, In the C-containing dielectric layer, the weight ratio of C is greater than or equal to 20%.
9. The manufacturing method according to any one of claims 1 to 3, characterized in that, The dielectric constant of the C-containing dielectric layer is between 2 and 7.
10. The manufacturing method according to any one of claims 1 to 3, characterized in that, The thickness of the C-containing dielectric layer is between 30 and 100 nm.
11. A magnetic random access memory, characterized in that, The magnetic random access memory is manufactured using any one of the methods described in claims 1 to 10.