Method for fabricating a semiconductor structure

Abstract

The present application provides a method for fabricating a semiconductor structure. By using mask opening holes with different ratios in a unit area corresponding to a substrate, the flow rates of reaction gases in each opening are different during the growth of the light-emitting layer, the growth rate of the light-emitting layer is different, and the doping efficiency of each element in the grown light-emitting layer is different. As a result, the component ratios of each element in the grown light-emitting layer are different, and the emission wavelengths of the LEDs are different. The above process is simple, and a semiconductor structure for full-color LEDs can be fabricated on a single substrate, reducing the size of the full-color LEDs.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a method for fabricating a semiconductor structure. Background Art

[0002] A light-emitting diode, abbreviated as LED, emits visible light by the recombination of electrons and holes. Two main application fields of LEDs include lighting and display. Especially in the display field, future development trends include higher picture quality and higher definition (more pixels and smaller pixel sizes). The key technology to achieve high-definition display is to realize ultra-small light-emitting pixels, which requires full-color LED light-emitting units with smaller sizes.

[0003] In the prior art, currently, the size of a full-color LED packaging unit is 1mm * 1mm. Three surface-mounted LED chips of red, green, and blue are packaged onto a PCB board through die bonding and wire bonding processes. The PCB board then leads out the electrodes of the three chips from the back through a conductive via process to form a full-color LED packaging unit. The full-color LED packaging unit is then press-bonded onto a COB flat panel through a COB (chip onboard) packaging process, and a dot matrix LED display screen is formed through row and column wiring on the COB flat panel. The sizes of both the full-color LED packaging unit and the dot matrix LED display screen are relatively large. Summary of the Invention

[0004] The object of the present invention is to provide a method for fabricating a semiconductor structure, which can be used for full-color LEDs and can reduce the size of the full-color LEDs and lower the cost.

[0005] To achieve the above object, the method for fabricating a semiconductor structure provided by the present invention includes:

[0006] Providing a substrate, the surface of the substrate includes a plurality of unit regions, and each unit region includes n sub-unit regions, where n is a positive integer greater than or equal to 2;

[0007] Providing a patterned mask on the substrate, the patterned mask has an opening corresponding to each sub-unit region; at least one of the hole ratios of the n openings corresponding to each unit region is different from the hole ratios of the other n - 1 openings, where the hole ratio of the opening is the ratio of the area of the opening to the area of the sub-unit region corresponding to the opening on the patterned mask;

[0008] Successively forming a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer on the substrate exposed by the opening, and the conductive type of the second-type semiconductor layer is opposite to that of the first-type semiconductor layer.

[0009] Optionally, the manufacturing method further includes: forming a common electrode layer between the substrate and the patterned mask; the first type of semiconductor layer, the light-emitting layer, and the second type of semiconductor layer are sequentially formed on the common electrode layer exposed by the opening.

[0010] Optionally, the hole occupation ratios of the n openings corresponding to the n sub-unit areas of the unit area are all different.

[0011] Optionally, the n sub-unit areas of the unit area are the same, and at least one of the n openings corresponding to the n sub-unit areas has an area different from the areas of the other n - 1 openings.

[0012] Optionally, the arrangement of the 2n openings corresponding to two adjacent unit areas is mirror-symmetrical.

[0013] Optionally, at least one of the n sub-unit areas of the unit area has an area different from the areas of the other n - 1 sub-unit areas, and the n openings corresponding to the n sub-unit areas have the same area.

[0014] Optionally, the arrangement of the 2n sub-unit areas in two adjacent unit areas is mirror-symmetrical.

[0015] Optionally, the shape of the sub-unit area is one of a rectangle, a circle, a triangle, a hexagon, and a trapezoid.

[0016] Optionally, the shape of the opening is one of a rectangle, a circle, a triangle, a hexagon, and a trapezoid.

[0017] Optionally, the patterned mask is a patterned mask layer retained in the semiconductor structure or a reusable shielding mask template.

[0018] Optionally, the light-emitting layer includes a single quantum well layer or a multi-quantum well layer.

[0019] Optionally, the material of the first type of semiconductor layer is a group III nitride, and / or the material of the light-emitting layer is a group III nitride, and / or the material of the second type of semiconductor layer is a group III nitride.

[0020] Optionally, In element is doped in the light-emitting layer, and the hole occupation ratio of the opening is adjusted to adjust the component ratio of In element in the light-emitting layer within the opening.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] By using different ratios of the openings in the mask corresponding to a unit area of the substrate, the flow rates of the reaction gases in each opening are different when growing the light-emitting layer, the growth rates of the light-emitting layer are different, and the doping efficiencies of the elements in the grown light-emitting layer are different. Furthermore, the component ratios of the elements in the grown light-emitting layer are different, and the emission wavelengths of the LEDs are different. The above process is simple and can fabricate a semiconductor structure for full-color LEDs on one substrate, reducing the size of the full-color LEDs and lowering the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a flowchart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention;

[0024] Figures 2 to 6 is Figure 1 the intermediate structure diagram corresponding to the process in

[0025] Figures 7 to 10 is the intermediate structure diagram corresponding to a method for fabricating a semiconductor structure according to a second embodiment of the present invention;

[0026] Figure 11 is a flowchart of a method for fabricating a semiconductor structure according to a third embodiment of the present invention;

[0027] Figures 12 to 15 is Figure 11 the intermediate structure diagram corresponding to the process in

[0028] Figure 16 is the intermediate structure diagram corresponding to a method for fabricating a semiconductor structure according to a fourth embodiment of the present invention;

[0029] Figures 17 to 20 is the intermediate structure diagram corresponding to a method for fabricating a semiconductor structure according to a fifth embodiment of the present invention;

[0030] Figure 21 is the intermediate structure diagram corresponding to a method for fabricating a semiconductor structure according to a sixth embodiment of the present invention.

[0031] For ease of understanding of the present invention, all the reference numerals appearing in the present invention are listed below:

[0032] Substrate 10

[0033] Unit area 11

[0034] Sub-unit area 11a

[0035] Patterned mask 12

[0036] Patterned mask layer 121

[0037] Blocking mask template 122

[0038] Opening 12a

[0039] Area S1 of the sub - unit region

[0040] Area S2 of the opening

[0041] Area S3 corresponding to the sub - unit region on the patterned mask

[0042] Semiconductor layer 13 of the first type

[0043] Light - emitting layer 14

[0044] Semiconductor layer 15 of the second type

[0045] Common electrode layer 16 Detailed implementation manners

[0046] To make the above - mentioned objects, features, and advantages of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0047] Figure 1 is a flowchart of the manufacturing method of the semiconductor structure according to the first embodiment of the present invention; Figures 2 to 6 is Figure 1 the schematic diagram of the intermediate structure corresponding to the process in

[0048] First, referring to Figure 1 step S1 in Figure 2 and as shown in

[0049] a substrate 10 is provided, and the surface of the substrate 10 includes a plurality of unit regions 11. Each unit region 11 includes n sub - unit regions 11a, where n is a positive integer greater than or equal to 2.

[0050] In this embodiment, the semiconductor structure is used for display, and the plurality of unit regions 11 are arranged in an array. Each unit region 11 corresponds to a pixel unit region; each sub - unit region 11a corresponds to a sub - pixel region.

[0051] In other embodiments, the semiconductor structure can also be used for lighting. The plurality of unit regions 11 are arranged in an array. Each unit region 11 corresponds to an illumination unit region; each sub - unit region 11a corresponds to a primary - color light - emitting structure region.

[0052] Figure 2 In the illustrated embodiment, n is preferably 3, corresponding to forming LED light - emitting structures of red, green, and blue primary colors.

[0053] In some embodiments, n can also be 4, corresponding to forming LED light - emitting structures of red, green, blue, and yellow primary colors.

[0054] Figure 2In the illustrated embodiment, the area S1 of each sub-unit region 11a is the same.

[0055] In this embodiment, the shapes of the respective sub-unit regions 11a are the same, and are all rectangles. In other embodiments, the shapes of the respective sub-unit regions 11a may be different, and / or the shape of the sub-unit region 11a may also be one of a circle, a triangle, a hexagon, and a trapezoid. This embodiment does not limit the distribution, shape, and area size of each sub-unit region 11a.

[0056] Next, referring to Figure 1 step S2 in Figure 3 and Figure 4 as shown, Figure 4 is a cross-sectional view along line AA in Figure 3 where a patterned mask 12 is provided on the substrate 10, and the patterned mask 12 has an opening 12a corresponding to each sub-unit region 11a; among the hole ratios of the n openings 12a corresponding to each unit region 11, at least one opening 12a has a hole ratio different from the hole ratios of the other n - 1 openings 12a, where the hole ratio of the opening 12a is the ratio between the area S2 of the opening 12a and the area S3 on the patterned mask 12 corresponding to the sub-unit region 11a corresponding to the opening 12a.

[0057] In this embodiment, the patterned mask 12 is a patterned mask layer 121. The material of the mask layer 121 may include, for example, at least one of silicon dioxide and silicon nitride. The mask layer 121 may be formed by physical vapor deposition or chemical vapor deposition, and the patterning may be achieved by dry etching or wet etching.

[0058] In this embodiment, referring to Figure 2 as shown, the areas S1 of the three sub-unit regions 11a of each unit region 11 are the same, so that the areas S3 on the patterned mask 12 corresponding to each sub-unit region 11a are the same. Referring to Figure 3 as shown, the areas S2 of the three openings 12a corresponding to the three sub-unit regions 11a are different from each other, so as to achieve different hole ratios for each opening 12a.

[0059] In some embodiments, when a unit region 11 includes n sub-unit regions 11a, the areas of the respective sub-unit regions 11a are the same; among the n openings 12a corresponding to the n sub-unit regions 11a, at least one opening 12a may have an area different from the areas of the other n - 1 openings 12a.

[0060] In this embodiment, the shapes of the respective openings 12a are the same, and are all rectangles. In other embodiments, the shapes of the respective openings 12a may be different, and / or the shape of the opening 12a may also be one of a circle, a triangle, a hexagon, and a trapezoid.

[0061] After that, referring to Figure 1 step S3 in Figure 5 and Figure 6 shown in Figure 6 is a cross-sectional view along line BB in Figure 5 On the substrate 10 exposed at each opening 12a, a semiconductor layer 13 of the first type, a light-emitting layer 14, and a semiconductor layer 15 of the second type are sequentially formed. The semiconductor layer 15 of the second type has a conductivity type opposite to that of the semiconductor layer 13 of the first type.

[0062] The material of the semiconductor layer 13 of the first type can be a group III nitride, and specifically can include at least one of GaN and AlGaN.

[0063] It should be noted that in this embodiment, a chemical element is used to represent a certain material, but the molar ratio of each chemical element in the material is not limited. For example, in the GaN material, Ga element and N element are included, but the molar ratio of Ga element and N element is not limited; in the AlGaN material, Al, Ga, and N three elements are included, but the molar ratio of each is not limited.

[0064] The first type can be a P-type, and the P-type doping ions can be at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions.

[0065] The growth process of the group III nitride material can include: atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxy (MBE, Molecular Beam Epitaxy), or plasma-enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or low-pressure chemical vapor deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or metal-organic chemical vapor deposition (MOCVD, Metal-Organic Chemical Vapor Deposition), or a combination thereof.

[0066] The P-type doping ions can be realized by an in-situ doping process.

[0067] The light-emitting layer 14 can include at least one of a single quantum well structure, a multi-quantum well (MQW) structure, a quantum wire structure, and a quantum dot structure. The light-emitting layer 14 can include a well layer and a barrier layer. The bandgap of the well layer is smaller than that of the barrier layer.

[0068] The material of the light-emitting layer 14 can be a GaN-based material, in which In element can be doped, specifically for example InGaN, or Al element can be doped, specifically for example AlGaN. The bandgap of InN is about 0.7 eV, which is smaller than the bandgap of GaN, 3.4 eV. Therefore, the larger the doping amount of In, the longer the emission wavelength of the light-emitting layer 14. The bandgap of AlN is about 6.2 eV, which is larger than the bandgap of GaN, 3.4 eV. Therefore, the larger the doping amount of Al, the shorter the emission wavelength of the light-emitting layer 14.

[0069] The growth process of the GaN-based material containing In or Al can refer to the growth process of the group III nitride material described above.

[0070] The hole occupation ratio of the opening 12a of the mask 12 is different, and the flow rate of the reaction gas in each opening 12a is different when the light-emitting layer 14 is grown. As a result, the incorporation rates of In / Al elements and Ga elements are different, that is, the incorporation efficiency of In / Al elements is different, which makes the component ratio of In / Al elements in the grown light-emitting layer 14 different. Specifically, the smaller the hole occupation ratio of the opening 12a, the faster the growth rate of the base material GaN of the light-emitting layer 14 in the opening 12a. The doping of In element has better selectivity, and the incorporation rate of In element is greater than the incorporation rate of Ga element. Therefore, the smaller the hole occupation ratio of the opening 12a, the higher the component content of In element in InGaN of the light-emitting layer 14. In addition, the smaller the hole occupation ratio of the opening 12a, the thicker the quantum well in the opening will be. Due to the quantum Stark effect, the emission wavelength will increase accordingly. On the contrary, the larger the hole occupation ratio of the opening 12a, the less obvious the difference between the incorporation rate of In element and the incorporation rate of Ga element, that is, the lower the incorporation efficiency of In element, and the lower the component ratio of In element in the grown light-emitting layer 14.

[0071] In another embodiment, when Al element is doped in the base material GaN of the light-emitting layer 14, the smaller the hole occupation ratio of the opening 12a, the faster the growth rate of the base material GaN of the light-emitting layer 14 in the opening 12a. However, the growth of Al element has no selectivity, and the incorporation rate of Al element is less than the incorporation rate of Ga element. Therefore, the smaller the hole occupation ratio of the opening 12a, the lower the component content of Al element in AlGaN of the light-emitting layer 14, and thus the smaller the doping amount of Al, and the longer the emission wavelength of the light-emitting layer 14.

[0072] In addition, the larger the hole occupation ratio of the opening 12a, the smaller the thickness of the grown light-emitting layer 14; the smaller the hole occupation ratio of the opening 12a, the larger the thickness of the grown light-emitting layer 14, and the thickness of the quantum well will also increase accordingly. Due to the quantum Stark effect, the emission wavelength will increase accordingly.

[0073] Figure 6In the illustrated embodiment, the thickness of the mask 12 is greater than the sum of the predetermined maximum thickness of the first type of semiconductor layer 13 and the predetermined maximum thickness of the light-emitting layer 14, which can avoid the overlap of the light-emitting layers 14 of the sub-unit regions 11a of a unit region 11, and thus avoid the problem of color mixing.

[0074] The material of the second type of semiconductor layer 15 can be a group III nitride, and specifically can include at least one of GaN and AlGaN.

[0075] The second type can be N-type, and the N-type doping ions can be at least one of Si ions, Ge ions, Sn ions, Se ions or Te ions.

[0076] The growth process of the N-type group III nitride material can refer to the growth process of the aforementioned P-type group III nitride material.

[0077] In some embodiments, the second type of semiconductor layer 15 can be attached to the patterned mask layer 121, and the second type of semiconductor layer 15 on the mask layer 121 can be removed by dry etching or wet etching, so that the second type of semiconductor layers 15 of the respective sub-unit regions 11a in a unit region 11 are electrically insulated; in some embodiments, the second type of semiconductor layer 15 on the mask layer 12 of a unit region 11 can also not be removed, so that the second type of semiconductor layers 15 of the respective sub-unit regions 11a in a unit region 11 are electrically connected together.

[0078] In some embodiments, by selecting the material of the mask layer 121, it is difficult for the second type of semiconductor layer 15 to be attached to the patterned mask layer 121. In this way, the grown second type of semiconductor layer 15 can electrically insulate the second type of semiconductor layers 15 of the respective sub-unit regions 11a in a unit region 11.

[0079] In this embodiment, the patterned mask layer 121 is retained in the semiconductor structure.

[0080] In some embodiments, the first type of semiconductor layer 13 can be an N-type semiconductor layer, and the second type of semiconductor layer 15 can be a P-type semiconductor layer.

[0081] The first type of semiconductor layer 13, the light-emitting layer 14, and the second type of semiconductor layer 15 of each sub-unit region 11a form an LED structure. The LED structures of each unit region 11 form an LED unit.

[0082] When a voltage is applied to the semiconductor layer 13 of the first type and the semiconductor layer 15 of the second type respectively to provide holes and electrons, the higher the proportion of In element in the light-emitting layer 14, the longer the emission wavelength; the lower the proportion of In element, the shorter the emission wavelength; the higher the proportion of Al element, the shorter the emission wavelength; the lower the proportion of Al element, the longer the emission wavelength.

[0083] In subsequent processes, the first electrode and the second electrode can be further fabricated to form an LED device; wherein, the first electrode electrically leads out the semiconductor layer 13 of the first type, and the second electrode electrically leads out the semiconductor layer 15 of the second type.

[0084] Figures 7 to 10 It is a schematic diagram of an intermediate structure corresponding to the manufacturing method of the semiconductor structure of the second embodiment of the present invention. Figure 9 is along Figure 8 a cross-sectional view taken along the CC line in Figures 7 to 10 As shown, the manufacturing method of the semiconductor structure of the second embodiment is substantially the same as that of the first embodiment, except that: as shown in Figure 7 in step S2, the patterned mask 12 is the blocking mask template 122; correspondingly, as shown in Figures 8 to 10 after step S3, the blocking mask template 122 can be peeled off from the substrate 10 and reused.

[0085] The thickness of the blocking mask template 122 can be greater than the sum of the predetermined maximum thickness of the semiconductor layer 13 of the first type and the predetermined maximum thickness of the light-emitting layer 14.

[0086] The blocking mask template 122 can be located between adjacent sub-unit areas 11a, which can prevent the light-emitting layers 14 of the respective sub-unit areas 11a of one unit area 11 from overlapping and avoid color mixing problems. At the same time, the blocking mask template 122 can also be located between adjacent unit areas 11, which can prevent color mixing problems between adjacent unit areas 11.

[0087] Figure 11 It is a flowchart of the manufacturing method of the semiconductor structure of the third embodiment of the present invention; Figures 12 to 15 is Figure 11 a schematic diagram of an intermediate structure corresponding to the process in Figure 14 is along Figure 13 a cross-sectional view taken along the DD line in

[0088] Referring to Figure 11 as shown, the manufacturing method of the semiconductor structure of the third embodiment is substantially the same as that of the first and second embodiments, except that:

[0089] step S2', referring to Figures 12 to 14As shown, a common electrode layer 16 and a patterned mask 12 are sequentially disposed on a substrate 10. In other words, a common electrode layer 16 is formed between the substrate 10 and the patterned mask 12. The material of the common electrode layer 16 and its formation method may refer to the material of the first type of semiconductor layer 13 and its formation method.

[0090] Step S3', referring to Figure 15 As shown, a first type of semiconductor layer 13, a light-emitting layer 14, and a second type of semiconductor layer 15 are sequentially formed on the common electrode layer 15 exposed by the opening 12a.

[0091] The common electrode layer 16 is used to electrically connect the first type of semiconductor layer 13 of each sub-unit region 11a in a unit region 11, and / or the first type of semiconductor layer 13 of each unit region 11.

[0092] Figure 16 It is a schematic diagram of an intermediate structure corresponding to the manufacturing method of the semiconductor structure according to the fourth embodiment of the present invention.

[0093] Referring to Figure 16 As shown, the manufacturing method of the semiconductor structure of the fourth embodiment is substantially the same as the manufacturing methods of the semiconductor structures of the first, second, and third embodiments, except that: the arrangement of 2n openings 12a corresponding to two adjacent unit regions 11 is mirror-symmetric.

[0094] Relative to Figure 3 the arrangement of the openings 12a therein, the advantage of the mirror-symmetric arrangement of the present embodiment is that: the openings 12a with similar hole ratios are adjacent, which can stabilize the flow rate of the reaction gas, making the incorporation efficiency of In / Al elements stable and the component ratio of In / Al elements in the grown light-emitting layer 14 stable.

[0095] Figures 17 to 20 It is a schematic diagram of an intermediate structure corresponding to the manufacturing method of the semiconductor structure according to the fifth embodiment of the present invention, Figure 19 is a cross-sectional view along the Figure 18 EE line therein. Referring to Figures 17 to 20 As shown, the manufacturing method of the semiconductor structure of the fourth embodiment is substantially the same as the manufacturing methods of the semiconductor structures of the first, second, and third embodiments, except that:

[0096] In step S1, referring to Figure 17 as shown, in a unit region 11, the areas S1 of each sub-unit region 11a are different;

[0097] In step S2, referring to Figure 18 and Figure 19As shown, in the patterned mask 12, the areas S2 of the openings 12a corresponding to the respective sub-unit regions 11a are the same; since the areas S1 of the respective sub-unit regions 11a of each unit region 11 are different, the areas S3 of the respective sub-unit regions 11a corresponding on the patterned mask 12 are different, thereby achieving different hole ratios of the respective openings 12a.

[0098] Referring to Figure 20 As shown, the hole ratios of the openings 12a of the mask 12 are different, and the component ratios of In / Al elements in the grown light-emitting layer 14 in step S3 are different, and the emission wavelengths are different.

[0099] Figure 21 It is a schematic diagram of an intermediate structure corresponding to the manufacturing method of the semiconductor structure according to the sixth embodiment of the present invention.

[0100] Referring to Figure 21 As shown, the manufacturing method of the semiconductor structure of the sixth embodiment is substantially the same as that of the semiconductor structure of the fifth embodiment, except that: the arrangement of the 2n sub-unit regions 11a of two adjacent unit regions 11 is mirror-symmetrical.

[0101] Relative to Figure 18 the arrangement of the n sub-unit regions 11a in [reference], the advantage of the mirror-symmetrical arrangement of this embodiment is that the openings 12a with similar hole ratios are adjacent, which can stabilize the flow rate of the reaction gas, make the incorporation efficiency of In / Al elements stable, and make the component ratio of In / Al elements in the grown light-emitting layer 14 stable.

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, comprising: providing a substrate (10), the surface of the substrate (10) including a plurality of unit regions (11), each of the unit regions (11) including n sub-unit regions (11a), where n is a positive integer greater than or equal to 2; providing a patterned mask (12) on the substrate (10), the patterned mask (12) having an opening (12a) corresponding to each of the sub-unit regions (11a); at least one of the aperture ratios of the n openings (12a) corresponding to each unit region (11) is different from the aperture ratios of the other n - 1 openings (12a), wherein the aperture ratio of the opening (12a) is the ratio between the area of the opening (12a) and the area of the sub-unit region (11a) corresponding to the opening (12a) on the patterned mask (12); sequentially forming a first-type semiconductor layer (13), a light-emitting layer (14), and a second-type semiconductor layer (15) on the substrate (10) exposed by each of the openings (12a), the second-type semiconductor layer (15) having a conductivity type opposite to that of the first-type semiconductor layer (13); doping the light-emitting layer (14) with In element or Al element, and adjusting the aperture ratio of the opening (12a) to adjust the component ratio of In element or Al element in the light-emitting layer (14) within the opening (12a).

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, further comprising: forming a common electrode layer (16) between the substrate (10) and the patterned mask (12); the first-type semiconductor layer (13), the light-emitting layer (14), and the second-type semiconductor layer (15) are sequentially formed on the common electrode layer (16) exposed by the opening (12a).

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, the n sub-unit regions (11a) of the unit region (11) have the same area, and at least one of the n openings (12a) corresponding to the n sub-unit regions (11a) has an area different from the areas of the other n - 1 openings (12a).

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, the arrangement of the 2n openings (12a) corresponding to two adjacent unit regions (11) is mirror-symmetric.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, at least one of the n sub-unit regions (11a) of the unit region (11) has an area different from the areas of the other n - 1 sub-unit regions (11a), and the n openings (12a) corresponding to the n sub-unit regions (11a) have the same area.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The arrangement of the 2n sub-unit regions (11a) in two adjacent unit regions (11) is mirror-symmetric.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein, the shape of the sub-unit region (11a) is one of a rectangle, a circle, a triangle, a hexagon, and a trapezoid.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein, the shape of the opening (12a) is one of a rectangle, a circle, a triangle, a hexagon, and a trapezoid.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein, the patterned mask (12) is a patterned mask layer (121) retained in the semiconductor structure or a reusable blocking mask template (122).

10. The method for manufacturing a semiconductor structure according to claim 1, wherein, the light-emitting layer (14) includes a single quantum well layer or a multi-quantum well layer.

11. The method for manufacturing a semiconductor structure according to claim 1, wherein, the material of the first type of semiconductor layer (13) is a group III nitride, and / or the material of the light-emitting layer (14) is a group III nitride, and / or the material of the second type of semiconductor layer (15) is a group III nitride.

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