Tiled chip layout and method of forming semiconductor structures

Abstract

The application provides a method for forming a spliced chip layout and a semiconductor structure, and is applied to the technical field of semiconductors. In the spliced chip layout provided by the application, line-width-gradually-changing splicing patterns are added on two splicing regions (repeated exposure regions) between two adjacent non-splicing regions, then, in a multiple-exposure process of positive etching or reverse etching determined according to the polarity of the spliced chip layout, the line-width-gradually-changing splicing patterns are used to change the area of the overlapping region after exposure, so as to offset the problem that the critical dimension of the pattern after development of the uniform-size splicing pattern in the conventional process is suddenly changed at the edge of the splicing region, and then the smooth interconnection photolithography splicing process is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a spliced ​​chip layout and semiconductor structure. Background Technology

[0002] In semiconductor integrated circuit manufacturing, chip size is often limited by the field of view of a single exposure in a lithography machine, which also restricts further improvements in chip performance. However, with the rapid development of applications such as artificial intelligence and automotive chips in recent years, higher demands have been placed on the high performance and high integration of chips, leading to an increase in the required chip size.

[0003] Currently, one method to increase chip size is to increase the single exposure size of the lithography machine, for example, by using a lithography machine with a larger field of view. Another method is to build upon the existing lithography machine by stitching together adjacent exposure fields to achieve interconnection, thereby breaking through the limitation of the single exposure size. That is, when the chip size exceeds the maximum photomask size of 26mm × 33mm (the maximum single exposure size of the lithography machine), it cannot be obtained through conventional single-step lithography processes. In this case, it is necessary to achieve this through multiple regional lithography stitching processes. Compared to using a large field-of-view lithography machine, the solution of using the existing lithography machine for stitching lithography saves on procurement costs and has advantages in maintaining the high precision of the lithography machine.

[0004] However, for conventional uniform critical dimension linear patterns, overlapping exposures cause the light intensity to superimpose in the overlapping areas. As the photosensitive material or photoacid in the photoresist diffuses, the critical dimension CD of the pattern inevitably increases significantly after development, especially at the edges of the overlapping areas, where the critical dimension CD exhibits a sudden increase. For electrical interconnects, as long as the overlapping areas and adjacent spacing are sufficiently large, the metal lines will be in a conductive state, and changes in the CD of the metal lines will only cause local changes in resistance, without affecting the realization of the electrical interconnect itself. But for other forms of interconnects, such as optical waveguides, abrupt changes in the critical dimension will lead to significant signal loss, which is unacceptable for the process. Summary of the Invention

[0005] The purpose of this invention is to provide a new chip layout and a method for forming a semiconductor structure using the chip layout, so as to solve the problem in the prior art that the critical dimensions of the pattern after development are increased and distorted due to the diffusion of photosensitive substances or photoacids in the photoresist during the photolithography splicing process of large-size chips.

[0006] To address the aforementioned technical problems, this invention provides a chip layout comprising:

[0007] Multiple non-seamless areas;

[0008] Multiple splicing areas are set between two adjacent non-splicing areas;

[0009] A splicing graphic is disposed on each splicing area, and one end of the splicing graphic is connected to a line graphic in the non-splicing area at the boundary between the splicing area and the adjacent non-splicing area.

[0010] Furthermore, the non-stitched area can be a single-exposure area, and the stitched area can be a repeated-exposure area between the single-exposure areas.

[0011] Furthermore, the sum of the lengths of the multiple stitching regions set between two adjacent non-stitching regions can be greater than the interval between the exposure positions corresponding to the two adjacent non-stitching regions.

[0012] Furthermore, the spliced ​​graphic includes line graphics with gradually changing line widths. The line width of the spliced ​​graphic at the junction is the same as the line width of the line graphics in the non-spliced ​​area connected to it, and the line width of the spliced ​​graphic gradually increases or decreases from the junction in a direction away from the line graphics in the non-spliced ​​area connected to it.

[0013] Furthermore, when the polarity of the splicing chip layout is clear, the splicing pattern is a first trapezoidal line pattern formed by the line width gradually decreasing from the boundary along the direction away from the line patterns in the non-splicing areas connected to it; and when the polarity of the splicing chip layout is dark, the splicing pattern is a second trapezoidal line pattern formed by the line width gradually increasing from the boundary along the direction away from the line patterns in the non-splicing areas connected to it.

[0014] Furthermore, the line width of the line obtained after the first line graphic is gradually reduced can be no less than the preset mask rule value.

[0015] Furthermore, the line width of the line obtained by gradually increasing the size of the second line graphic can be more than twice the line width of the line graphic in the non-joined area connected to it.

[0016] Furthermore, the included angle of the spliced ​​graphic can be less than 1 urad, wherein the included angle is the ratio of the line width to the length of the line graphic.

[0017] Furthermore, the plurality of non-splicing regions and the plurality of splicing regions are located on the same chip layout or on different chip layouts; when the plurality of non-splicing regions are located on the same chip layout, the plurality of non-splicing regions are located at both ends of the chip layout, and when the plurality of non-splicing regions are located on different chip layouts, each chip layout includes at least one non-splicing region and one splicing region.

[0018] Furthermore, based on the chip layout described above, the present invention also provides a method for forming a semiconductor structure, which may specifically include the following steps:

[0019] A semiconductor substrate is provided, on the surface of which a patterned dielectric layer and a photoresist layer are sequentially formed;

[0020] Based on the aforementioned spliced ​​chip layout, a photolithography splicing process including multiple regional exposures is performed to form an actual layout of the spliced ​​chip corresponding to the aforementioned spliced ​​chip layout on the photoresist layer.

[0021] Using the photoresist layer on which the actual layout is formed as a mask, the pattern medium layer and the semiconductor substrate are etched to smoothly and interconnectively transfer the pattern on the spliced ​​chip layout onto the semiconductor substrate.

[0022] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0023] In the splicing chip layout provided by this invention, splicing patterns (repeated exposure areas) with varying linewidths are added to two splicing areas located between two adjacent non-splicing areas. Then, during multiple exposures of positive or negative etching determined by the polarity of the splicing chip layout, the area of ​​the overlapping area after exposure is changed by using the splicing patterns with varying linewidths. This offsets the problem that the critical dimensions of the pattern change abruptly at the edge of the splicing area after the development of uniformly sized splicing patterns in conventional processes, thereby achieving a smooth interconnect photolithography splicing process.

[0024] Furthermore, in the chip layout provided by this invention, different gradient patterns are set for chip layouts with different polarities, thereby enabling the application of photolithography splicing technology to form smooth interconnected patterns for different diffusion effects (inward or outward diffusion) of photosensitive materials or photoacids, thus expanding the application of photolithography splicing technology. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of spliced ​​chip layouts when the polarity of the chip layout is clear, provided in one embodiment of the present invention.

[0026] Figure 2 for Figure 1 The corresponding chip layout is shown in the structural diagram after the photolithography splicing process.

[0027] Figure 3 This is a schematic diagram of the structure of spliced ​​chip layouts when the polarity of the chip layout is dark, provided in one embodiment of the present invention.

[0028] Figure 4for Figure 3 The corresponding chip layout is shown in the structural diagram after the photolithography splicing process.

[0029] Figure 5 According to one embodiment of the present invention, based on Figure 1 or Figure 3 The diagram shows a process flow diagram of the semiconductor structure formation method of the spliced ​​chip layout. Detailed Implementation

[0030] To address the aforementioned problems, this invention provides a novel chip layout and a method for forming a semiconductor structure using the chip layout, thereby resolving the issue in the prior art where the diffusion of photosensitive substances or photoacids in the photoresist during the photolithography splicing process of large-size chips leads to increased distortion in the critical dimensions of the pattern after development.

[0031] The following is in conjunction with the appendix Figures 1-5 The present invention provides a novel spliced ​​chip layout and a method for forming a semiconductor structure using the spliced ​​chip layout, and will be further described in detail with specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Many specific details are set forth in the following description to provide a thorough understanding of the present invention; however, the present invention may be practiced in other ways different from those described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.

[0032] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0033] The splicing chip layout provided by this invention will be introduced first below.

[0034] It should be noted that in practical applications, during the exposure and development of photoresist layers using chip layouts, the type of photoresist layer (positive or negative) and the polarity of the chip layout (clear or dark) can be used to determine which patterns on the chip layout correspond to the photoresist and whether to expose or remove that portion of the photoresist.

[0035] Based on this, in the process of proposing a splicing chip layout for forming a semiconductor structure of a large-size chip, the inventors of this invention can specifically set splicing patterns with different gradient sizes (linewidths) according to the polarity of the chip layout, thereby achieving smooth interconnection patterns using photolithography splicing technology for different photosensitive materials or photoacids (inward or outward diffusion). For example, in an embodiment of this invention, the photoresist is positive resist. When the polarity of the chip layout is clear, the light-transmitting areas (blank areas) in the chip layout represent the areas to be removed from the photoresist, while the opaque areas (shaded areas) represent the areas to be retained. When the polarity of the chip layout is dark, the light-transmitting and opaque parts of the pattern are exactly the opposite of the clear polarity. Figure 1 This is a schematic diagram of the structure of spliced ​​chip layouts when the polarity of the chip layout is clear, provided in one embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of the corresponding chip layout after photolithography splicing process; Figure 3 This is a schematic diagram of the structure of spliced ​​chip layouts when the polarity of the chip layout is dark, provided in one embodiment of the present invention; Figure 4 for Figure 3 The corresponding chip layout is shown in the structural diagram after the photolithography splicing process.

[0036] For details, please refer to the following: Figure 1 and Figure 2 ,like Figure 1 As shown, when the polarity of the splicing chip layout is clear, the splicing chip layout provided by this invention may specifically include:

[0037] Multiple non-separate regions; for example, such as Figure 1 The first non-splicing region A1 and the second non-splicing region A2 in the image.

[0038] Multiple splicing regions are positioned between two adjacent non-splicing regions; for example, such as... Figure 1 The first splicing area B1 and the second splicing area B2 are located between the first non-splicing area A1 and the second non-splicing area A2.

[0039] A spliced ​​graphic is disposed on each of the splicing areas, and one end of the spliced ​​graphic is connected to a line graphic in the non-splicing area at the boundary between the splicing area and the adjacent non-splicing area; for example, such as Figure 1Graphic 11 is located in the first splicing area B1 and graphic 12 is located in the second splicing area B2.

[0040] Wherein, the non-stitched areas, such as A1 and A2, are single-exposure areas, and the stitched areas, such as B1 and B2, are repeated-exposure areas between the single-exposure areas A1 and A2. Furthermore, the size of a single stitched area B1 or B2 located between two adjacent non-stitched areas A1 and A2 should be smaller than the interval between the adjacent non-stitched areas A1 and A2, while the sum of the lengths of multiple stitched areas B1 and B2 located between two adjacent non-stitched areas A1 and A2 needs to be greater than the interval between the exposure positions corresponding to the two adjacent non-stitched areas A1 and A2.

[0041] The spliced ​​graphics 11 and 12 are line graphics with gradually changing line widths. Specifically, the spliced ​​graphics 11 or 12 are trapezoidal first line graphics formed by gradually decreasing line widths from the boundary between A1 and B1 or A2 and B2, away from the line graphics in the non-spliced ​​areas A1 or A2. That is, the line width of the spliced ​​graphics 11 or 12 at the boundary is the same as the line width of the line graphics in the non-spliced ​​areas A1 or A2 connected to it, while the line width of the spliced ​​graphics 11 or 12 gradually decreases from the boundary away from it. The line width a1 of the line obtained after the gradual decrease of the first line graphics 11 or 12 is not less than a preset mask rule value. Preferably, the line width a1 is equal to the preset mask rule value, and the ratio of the line width a1 to the length b1 of the first line graphics 11 or 12 (the angle between the graphics) is less than 1 μad.

[0042] In this embodiment, each of the non-splicing regions may contain at least one linear graphic, such as... Figure 1 The rectangular patterns in A1 and A2 shown; and in order to form a smooth interconnected pattern composed of linear patterns in multiple non-splicing regions on the photoresist and semiconductor substrate after multiple partitioned exposures, the inventors of this invention propose adding a splicing pattern with a gradually changing linewidth, such as a first line pattern 11 or 12, to two splicing regions located between two adjacent non-splicing regions. Since the first line patterns 11 and 12 will overlap during multiple partitioned exposures, forming a pattern as shown in the diagram. Figure 2 The hexagonal overlay pattern shown is located in the blank area (within the two dashed lines of the overlay area AB). Therefore, the exposure dose of this overlay pattern (corresponding to the area to be removed in the photoresist) is twice that of other areas. This will cause the photosensitive material or photoacid in the area where the overlay pattern is located to diffuse outwards along the concentration gradient from high to low. However, during the development of the first line patterns 11 and 12, the closer to the center line of the overlay pattern, such as... Figure 2 The larger the overlapping area of ​​the pattern along the center line A'B', the greater the concentration gradient of the exposure dose. This will cause the diffusion of photosensitive material or photoacid to immediately increase the line width of the superimposed pattern. As the overlapping area moves away from the center line, the overlapping area gradually decreases, and the concentration gradient of the exposure dose also decreases. Furthermore, as it moves further away from the edge of the line, the diffusion effect of the photosensitive material or photoacid gradually weakens, and its influence on the line width change of the line pattern also decreases. This results in the first line patterns 11 and 12 after development forming a concave line pattern, such as... Figure 2 The diagram shown on the right.

[0043] For details, please refer to the following: Figure 3 and Figure 4 ,like Figure 3 As shown, when the polarity of the splicing chip layout is dark, the splicing chip layout provided by this invention may specifically include:

[0044] Multiple non-separate regions; for example, such as Figure 3 The first non-splicing region C1 and the second non-splicing region C2 in the image.

[0045] Multiple splicing regions are positioned between two adjacent non-splicing regions; for example, such as... Figure 3 The first splicing area D1 and the second splicing area D2 are located between the first non-splicing area C1 and the second non-splicing area C2.

[0046] A spliced ​​graphic is disposed on each of the splicing areas, and one end of the spliced ​​graphic is connected to a line graphic in the non-splicing area at the boundary between the splicing area and the adjacent non-splicing area; for example, such as Figure 3 Graphic 21 is located in the first splicing area D1 and graphic 22 is located in the second splicing area D2.

[0047] Wherein, the non-stitched areas, such as C1 and C2, are single-exposure areas, and the stitched areas, such as D1 and D2, are repeated-exposure areas between the single-exposure areas C1 and C2. Furthermore, the size of a single stitched area D1 or D2 located between two adjacent non-stitched areas C1 and C2 should be smaller than the interval between the adjacent non-stitched areas C1 and C2, while the sum of the lengths of multiple stitched areas D1 and D2 located between two adjacent non-stitched areas C1 and C2 should be greater than the interval between the exposure positions corresponding to the two adjacent non-stitched areas C1 and C2.

[0048] The spliced ​​graphics 21 and 22 are line graphics with gradually changing line widths. Specifically, the spliced ​​graphics 21 and 22 are trapezoidal second line graphics that start from the boundary between C1 and D1 or C2 and D2 and gradually increase in width away from the line graphics in the non-spliced ​​areas C1 or C2. The line width c1 of the gradually increasing second line graphic 21 or 22 is more than twice the line width of the line graphics in the connected non-spliced ​​areas, specifically 2 times, 2.1 times, 3 times, 3.12 times, 4 times, etc. As a preferred example, N is 3, and the ratio of the line width c2 to the length d2 of the second line graphic 21 or 22 (the angle between the graphics) is less than 1 μad.

[0049] In this embodiment, during the multiple exposure processes of the chip layout, the second line patterns 22 and 22 will overlap, thus forming a pattern as shown. Figure 4 The sharp corners shown in the shadow area are eliminated by the exposure of their relative positions, forming a hexagonal superimposed shape (specifically located within the two dashed lines of the overlapping area CD). This is because... Figure 3 and Figure 4 The blank areas in the image are the exposure and development areas. Therefore, the exposure dose in the blank areas on both sides of the overlay pattern will diffuse inwards towards the lines of the overlay pattern, thereby compressing the sharp corners of the overlay pattern in the shadow area inwards into smooth arcs. That is, it causes the second line patterns 21 and 22 after development to form convex line patterns, such as... Figure 4 As shown.

[0050] Understandable Figure 1 and Figure 3 The chip layout shown is an example of forming one non-splitting area, multiple splicing areas, and splicing graphics on different chip layouts. In other embodiments, the chip layout provided by the present invention, which adds splicing graphics with varying line widths to two splicing areas between two adjacent non-splitting areas, can also be located on the same chip layout. The present invention will not describe this in detail.

[0051] Furthermore, the present invention specifically provides a method for forming on the original splicing chip layout. Figure 1 or Figure 3 The aforementioned chip layout containing the spliced ​​pattern may specifically include the following steps:

[0052] Step S1: Provide an original splicing chip layout and determine different functional areas on the original splicing chip layout to form multiple non-splicing areas and multiple splicing areas, such as a first non-splicing area, a first splicing area, a second non-splicing area, and a second splicing area.

[0053] Step S2: Confirm the line width of the line graphics in the non-splicing area and the maximum allowable angle of the graphic angle that can be formed in the splicing area.

[0054] Step S3: According to the splicing requirements, a splicing pattern with gradually changing line width is formed on each splicing area. The line width of the splicing pattern at the junction is the same as the line width of the line pattern in the non-splicing area connected to it, while the line width of the splicing pattern gradually increases or decreases from the line width at the junction in the direction away from the line pattern in the non-splicing area connected to it.

[0055] Wherein, the maximum angle of the spliced ​​pattern is the maximum angle allowed for the chip after splicing, and the maximum angle allowed for the chip after splicing is greater than or equal to the tilt angle formed by the reduction of the line width of the spliced ​​pattern on the photomask (spliced ​​chip layout) and greater than or equal to the tilt angles on both sides of the lines formed after actual splicing on the silicon wafer (semiconductor substrate).

[0056] In this embodiment, when the polarity of the splicing chip layout is clear, the splicing pattern is a trapezoidal first line pattern whose line width starts from the boundary and gradually decreases along the direction away from the line patterns in the non-splicing areas connected to it. The line width of the line obtained after the gradual decrease of the first line pattern should be designed to be the minimum feature size allowed by the design rule, i.e., the mask rule value. When the polarity of the splicing chip layout is dark, the splicing pattern is a trapezoidal second line pattern whose line width starts from the boundary and gradually increases along the direction away from the line patterns in the non-splicing areas connected to it. The line width of the line obtained after the gradual increase of the second line pattern is 3 times the line width of the line patterns in the non-splicing areas connected to it.

[0057] Furthermore, the angle between the first and second line figures must be smaller than the maximum allowed angle, i.e., 1 urad.

[0058] Furthermore, based on the above Figure 1 and Figure 3 In addition to the aforementioned chip layout, the present invention also provides a method for forming a semiconductor structure using the chip layout.

[0059] For details, please refer to the following: Figure 5 , Figure 5 The utilization provided in one embodiment of the present invention Figure 1 or Figure 3 The diagram shows a flow chart illustrating the method for forming the semiconductor structure of the spliced ​​chip board. (See attached diagram.) Figure 5 As shown, the forming method includes the following steps:

[0060] Step S501: A semiconductor substrate is provided, and a patterned dielectric layer and a photoresist layer are sequentially formed on the surface of the semiconductor substrate;

[0061] Step S502, based on the above Figure 1 or Figure 3 The aforementioned chip layout undergoes a photolithography splicing process involving multiple regional exposures to form an actual chip layout corresponding to the aforementioned chip layout on a photoresist layer.

[0062] Step S503: Using the photoresist layer on which the actual layout is formed as a mask, the pattern medium layer and the semiconductor substrate are etched to smoothly and interconnectively transfer the pattern on the spliced ​​chip layout onto the semiconductor substrate.

[0063] The actual layout size of the splicing chip is greater than 26mm × 33mm.

[0064] In this embodiment, the photolithography splicing process involves exposing each exposure area of ​​the spliced ​​chip layout one by one, thereby transferring the patterns of each exposure area in the spliced ​​chip layout sequentially onto the target wafer. The patterns of adjacent exposure areas are then spliced ​​together in corresponding areas on the semiconductor substrate, thus forming the actual layout of the spliced ​​chip with seams. Figure 2 or Figure 4 As shown.

[0065] It should be noted that in step S501, a photoresist layer may be formed only on the surface of the semiconductor substrate, or an etching intermediate layer and a photolithographic anti-reflection layer may be deposited before the photoresist layer is formed, and then the designed spliced ​​chip layout is used for photolithography and etching processes to transfer the non-spliced ​​pattern and spliced ​​pattern sequentially onto the photoresist layer, the pattern medium layer, and the semiconductor substrate; after that, the photoresist layer and other possible auxiliary layers on the pattern medium layer are removed.

[0066] In summary, in the chip layout provided by this invention, a layered linewidth splicing pattern (repeated exposure area) is added to two splicing areas located between two adjacent non-splicing areas. Then, during multiple exposures of positive or negative etching determined by the polarity of the chip layout, the layered linewidth splicing pattern is used to change the area of ​​the overlapping area after exposure. This offsets the problem of abrupt changes in the critical dimensions of the pattern at the edge of the splicing area after development of uniformly sized splicing patterns in conventional processes, thereby achieving a smooth interconnect photolithography splicing process.

[0067] Furthermore, in the chip layout provided by this invention, different gradient patterns are set for chip layouts with different polarities, thereby enabling the application of photolithography splicing technology to form smooth interconnected patterns for different diffusion effects (inward or outward diffusion) of photosensitive materials or photoacids, thus expanding the application of photolithography splicing technology.

[0068] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0069] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0070] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A chip layout, characterized in that, include: Multiple non-seamless areas; Multiple splicing areas are set between two adjacent non-splicing areas; A splicing graphic is disposed on each of the splicing areas, and one end of the splicing graphic is connected to a line graphic in the non-splicing area at the boundary between the splicing area it is located in and the adjacent non-splicing area. The spliced ​​graphic includes line graphics with gradually changing line widths. The line width of the spliced ​​graphic at the junction is the same as the line width of the line graphics in the non-spliced ​​area connected to it, and the line width of the spliced ​​graphic gradually increases or decreases from the junction in a direction away from the line graphics in the non-spliced ​​area connected to it. When the polarity of the splicing chip layout is clear, the splicing pattern is a first trapezoidal line pattern formed by the line width gradually decreasing from the boundary and moving away from the line patterns in the non-splicing areas connected to it; and when the polarity of the splicing chip layout is dark, the splicing pattern is a second trapezoidal line pattern formed by the line width gradually increasing from the boundary and moving away from the line patterns in the non-splicing areas connected to it. The line width of the line obtained after the first line graphic is gradually reduced is not less than the preset mask rule value; The line width of the line obtained by gradually increasing the size of the second line pattern is more than twice the line width of the line pattern in the non-splicing area connected to it, and the splicing chip layout is used to realize the photolithography splicing process for smooth interconnection.

2. The chip layout as described in claim 1, characterized in that, The non-stitched area is a single-exposure area, and the stitched area is a repeated-exposure area between the single-exposure areas.

3. The chip layout as described in claim 2, characterized in that, The sum of the lengths of the multiple stitching regions set between two adjacent non-stitching regions is greater than the interval between the exposure positions corresponding to the two adjacent non-stitching regions.

4. The chip layout as described in claim 1, characterized in that, The plurality of non-splicing regions and the plurality of splicing regions are located on the same chip layout or on different chip layouts; when the plurality of non-splicing regions are located on the same chip layout, the plurality of non-splicing regions are located at both ends of the chip layout, and when the plurality of non-splicing regions are located on different chip layouts, each chip layout contains at least one non-splicing region and one splicing region.

5. A method for forming a semiconductor structure, characterized in that, Includes the following steps: A semiconductor substrate is provided, on the surface of which a patterned dielectric layer and a photoresist layer are sequentially formed; Based on the splicing chip layout according to any one of claims 1-4, a photolithography splicing process including multiple regional exposures is performed to form an actual layout of the splicing chip corresponding to the splicing chip layout on the photoresist layer; Using the photoresist layer on which the actual layout is formed as a mask, the pattern medium layer and the semiconductor substrate are etched to smoothly and interconnectively transfer the pattern on the spliced ​​chip layout onto the semiconductor substrate.

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