Storage method of failure data, repair method, and storage device of failure data

Abstract

The application belongs to the technical field of semiconductor automatic test, and specifically provides a failure data storage method, a repair method and a failure data storage device. The failure data storage method comprises the following steps: generating a response signal in response to an excitation signal loaded on a chip under test; the excitation signal is generated by a pattern generator of an automatic test equipment; performing a logical comparison between the response signal and the excitation signal to obtain a comparison result, and performing a first marking on the comparison result; the comparison result comprises failure data and normal data; grouping the comparison result according to a preset rule and performing a second marking on each group according to the first marking; and storing each group and the second marking corresponding to each group. Based on the technical scheme provided in the application, the storage efficiency can be improved, and the storage space can be saved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor automated testing technology, and in particular to a method for storing failure data, a method for repairing failure data, and a device for storing failure data. Background Technology

[0002] With the development of the domestic economy and the gradual expansion of the consumer market, especially the increasing demand for electronic products, the demand for semiconductor silicon wafers is also growing. However, these semiconductor silicon wafers need to be inspected and tested by semiconductor testing plants before they can be packaged and used.

[0003] In the current testing process for semiconductor silicon wafers, the test results (including both failure and normal data) are often stored directly. This results in a massive amount of data to be stored, consuming a large amount of storage space and thus reducing storage efficiency. Summary of the Invention

[0004] In view of this, the present invention provides a method for storing failed data, a method for repairing failed data, and a device for storing failed data, which can improve storage efficiency and save storage space.

[0005] To achieve the above objectives, a first aspect of this application provides a method for storing failure data, comprising: responding to an excitation signal loaded on a chip under test to generate a response signal; the excitation signal being generated by a pattern generator of an automated testing device; logically comparing the response signal and the excitation signal to obtain a comparison result, and marking the comparison result with a first label; the comparison result including failure data and normal data; grouping the comparison result according to a preset rule and marking each group with a second label according to the first label; and storing each group and the second label corresponding to each group.

[0006] As described above, this approach uses a first label to mark the logical comparison results of the response signal and the excitation signal, which can mark failed data and normal data. By grouping the comparison results and then marking the grouped groups, it can mark groups containing failed data and groups containing only normal data. Instead of storing all the marked results directly, the marked groups are stored, which greatly reduces the amount of data that needs to be stored, thereby saving a lot of storage space and improving storage efficiency.

[0007] As one possible implementation of the first aspect, the first marking of the comparison result includes: when the comparison result is invalid data, marking the comparison result as a first invalid mark; when the comparison result is normal data, marking the comparison result as a first normal mark.

[0008] As described above, by marking the comparison results with a first failure mark and a first normal mark, it is possible to quickly locate and retrieve failure data.

[0009] As one possible implementation of the first aspect, grouping the comparison results according to a preset rule includes: sorting the comparison results according to the order in which they were generated; and for the sorted comparison results, truncating them sequentially according to a preset data length to group the comparison results.

[0010] As described above, the data length can be set arbitrarily according to the actual working conditions. When the data volume is large, the data length can be set to be larger, and when the data volume is small, the data length can be set to be smaller. Based on the data length set above, the comparison results can be reasonably grouped, thereby saving storage space.

[0011] As one possible implementation of the first aspect, the second marking of each group based on the first mark includes: marking the group as a second failure mark when the failure data exists in the group; and marking the group as a second normal mark when the failure data does not exist in the group.

[0012] As described above, when there is faulty data in a certain group, the group is marked as a second faulty group. This allows for quick location of the corresponding group when faulty data needs to be obtained, thus enabling rapid and accurate location of the corresponding faulty data.

[0013] As one possible implementation of the first aspect, storing the respective groups and the second markers corresponding to the respective groups includes: storing the data information in each group and the second markers corresponding to the respective groups; wherein the data information includes at least a data address.

[0014] As shown above, the data address in the data information makes it easy to locate the data, and the data content in the data information makes it easy to view the detailed information of the data.

[0015] As one possible implementation of the first aspect, the excitation signal is generated by a pattern generator of an automatic test device, comprising: the pattern generator of the automatic test device generating address signal data, clock signal data, and enable signal data; and modulating the address signal data, clock signal data, and enable signal data to obtain the excitation signal.

[0016] A second aspect of this application provides a method for repairing failed data, wherein the failed data is stored according to the method for storing failed data as described in any of the first aspects above, comprising: obtaining a group corresponding to a second failure mark; obtaining data corresponding to a first failure mark from the group corresponding to the second failure mark; obtaining the data address according to the data corresponding to the first failure mark to locate the failed data; and repairing the failed data at the data address according to the location.

[0017] As described above, by sequentially locating the group and data address using the second failure marker and the first failure marker, the faulty data can be accurately located. When the faulty data is located, it can be repaired, thereby improving the chip's yield rate.

[0018] A third aspect of this application provides a storage device for failure data, comprising: a response module for responding to an excitation signal loaded on a chip under test and generating a response signal; the excitation signal is generated by a pattern generator of an automatic testing device; a logic comparison module for logically comparing the response signal and the excitation signal to obtain a comparison result and assigning a first mark to the comparison result; the comparison result includes failure data and normal data; a grouping module for grouping the comparison result according to a preset rule and assigning a second mark to each group according to the first mark; and a storage module for storing each group and the second mark corresponding to each group.

[0019] Therefore, the storage device for the failure data is the same as the storage method for failure data described in the first aspect above, and its corresponding beneficial effects can be found in the description of the first aspect above.

[0020] A fourth aspect of this application provides a computing device, including: a processor and a memory; the memory storing program instructions thereon, which, when executed by the processor, cause the processor to perform a method for storing invalid data as described in any of the first aspects above.

[0021] The fifth aspect of this application provides a computer-readable storage medium having program instructions stored thereon, characterized in that, when executed by a computer, the program instructions cause the computer to perform the method for storing invalid data described in the first aspect above.

[0022] These and other aspects of this application will become more apparent in the description of the following embodiments(s). Attached Figure Description

[0023] The various technical features of this application and their relationships will be further explained below with reference to the accompanying drawings. The drawings are exemplary; some technical features are not shown to scale, and some drawings may omit technical features commonly used in the art to which this application pertains that are not essential for understanding and implementing this application, or additionally show technical features that are not essential for understanding and implementing this application. In other words, the combination of various technical features shown in the drawings is not intended to limit this application. Furthermore, throughout this application, the same reference numerals refer to the same things. Specific descriptions of the drawings are as follows:

[0024] Figure 1 A schematic diagram of a failure data storage device provided for related technologies;

[0025] Figure 2 A flowchart illustrating a method for storing failure data provided in an embodiment of this application;

[0026] Figure 3 An example diagram illustrating a storage method provided in an embodiment of this application;

[0027] Figure 4 A flowchart illustrating a method for repairing failed data provided in this application embodiment;

[0028] Figure 5 A schematic diagram of a comprehensive structure for storing and repairing test data, provided for an embodiment of this application;

[0029] Figure 6 This is a schematic diagram of the structure of a storage device for failed data provided in an embodiment of this application;

[0030] Figure 7 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0031] Figure 8 This is a schematic diagram of another computing device provided in an embodiment of this application. Detailed Implementation

[0032] The terms "first, second, third, etc." or similar terms such as module A, module B, module C, etc., used in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that a specific order or sequence may be interchanged where permitted so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0033] In the following description, the labels of the steps, such as S110, S120, etc., do not necessarily mean that the steps will be executed in this way. The order of the steps can be interchanged or executed simultaneously if permitted.

[0034] The term "comprising" as used in the specification and claims should not be construed as limiting itself to what follows; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the mentioned feature, integral, step, or component, but does not exclude the presence or addition of one or more other features, integrals, steps, or components, or groups thereof. Thus, the statement "device comprising means A and B" should not be limited to a device consisting solely of components A and B.

[0035] The terms "an embodiment" or "an embodiment" as used in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in at least one embodiment of this application. Therefore, the terms "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics can be combined in any suitable manner, as will be apparent to those skilled in the art from this disclosure.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In case of any inconsistency, the meaning set forth in this specification or derived from the content described herein shall prevail. Furthermore, the terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit the scope of this application.

[0037] Before providing a detailed description of the specific embodiments of this application, the relevant technologies of this application will be described in detail first.

[0038] like Figure 1As shown, the related technology provides a structural schematic diagram of a failure data storage device. In this technology, the failure data storage device includes an Automatic Test Equipment (ATE) 110, a Double Data Rate (DDR) synchronous dynamic random access memory (DDR), a logic comparison module 130, and a memory 140. In this technology, the DDR 120 is the chip under test (DUT). First, the ATE sends test signals to the DUT for performance testing. Then, the data sent by the ATE and the data obtained after testing the DDR are compared and calculated in the logic comparison module 130, and the comparison result is sent to the memory 140 for storage. As a result, the memory 140 stores a large amount of failure data and a large amount of normal data. Therefore, the storage capacity of the memory 140 should not be less than the storage capacity of the DDR, leading to a waste of storage space. Furthermore, as the amount of data stored in the memory 140 increases, it may also affect the storage efficiency of subsequent data.

[0039] Referring to the figures below, a method for storing failure data provided in an embodiment of this application will be described in detail.

[0040] like Figure 2 The diagram shows a flowchart of a method for storing failure data according to an embodiment of this application. The implementation process of this method mainly includes steps S110-S140, which are described in detail below:

[0041] S210: Responds to the excitation signal applied to the chip under test and generates a response signal.

[0042] In this embodiment, the chip under test can be any memory, such as, but not limited to, random access memory (RAM), static random-access memory (SRAM), and dynamic random-access memory (DRAM). In the following description of the embodiments of this application, the chip under test is described as double data rate synchronous dynamic random-access memory (DDR).

[0043] The Algorithmic Pattern Generator (ALPG) in the Automated Test Equipment (ATE) generates enable signals, clock signals, address signals, etc. After being modulated accordingly, these signals are output by the ATE as excitation signals and loaded onto the DDR chip under test for testing.

[0044] The DDR chip under test responds to the stimulus signal and generates a response signal. Here, "response" refers to performing relevant tests on the DDR chip based on the stimulus signal, and the generated test data is the response signal.

[0045] S220: Perform a logical comparison between the response signal and the excitation signal to obtain a comparison result, and assign a first mark to the comparison result. The comparison result includes failure data and normal data.

[0046] In this embodiment, the test data generated by the DDR chip under test and the excitation signal output by the automated test equipment (ATE) are logically compared and calculated to determine whether the DDR-generated test data is correct. Incorrect data (failed data) is marked with a first failure flag, and correct data (normal data) is marked with a first normal flag. For example, the first failure flag can be recorded as 1, and the first normal flag as 0. In this way, it can be determined which data is failed data and which data is normal data. It should be understood that the 0 / 1 marking in this embodiment is only an exemplary description, and in other embodiments, the first failure flag and the first normal flag can also be in other forms.

[0047] S230: Group the comparison results according to a preset rule and assign a second label to each group based on the first label.

[0048] One approach is to sort the comparison results according to the order in which they were generated, and then truncate the sorted comparison results according to a preset data length, thereby grouping the comparison results.

[0049] As another implementation method, the comparison results can be grouped according to the test cycle, that is, the comparison results generated in the same test cycle are in the same group.

[0050] As another implementation method, the comparison results can be grouped according to the test task, that is, the comparison results generated in the same test task are grouped together. This grouping method is generally suitable for situations where the amount of comparison result data generated by a test task is small.

[0051] In this embodiment, when there is faulty data in the same group, regardless of the number of faulty data, the group needs to be marked as faulty again. Conversely, when there is no faulty data in the same group, and all data in the group is normal, the group is marked as normal again. In short: when there is data in a group marked with a first fault flag of 1, the group is marked as faulty again. When all data in a group are marked with a first normal flag of 0, the group is marked as normal again. For example, the second fault flag can also be 1, and the second normal flag can also be 0.

[0052] S240: Store each group and the second tag corresponding to each group.

[0053] One implementation method is to store the relevant data in a table; to save storage space, only the data address can be stored. For example... Figure 3 The diagram illustrates one storage method. Each square represents a set of comparison results and its corresponding second marker. For example, a square in the first row and first column storing a 1 indicates that there is invalid data in that set of comparison results. Conversely, a square in the first row and second column storing a 0 indicates that all comparison results in that set are valid. This way, the memory only needs to store this table, saving significant storage space, improving storage efficiency, and providing a clear visual indication of which data sets contain invalid data, facilitating data retrieval and processing.

[0054] Another embodiment of this application provides a method for repairing failed data, such as... Figure 4 The flowchart shown is for this repair method. The implementation process mainly includes steps S410-S440. Each step is described in detail below:

[0055] S410: Obtain the group corresponding to the second mark as the second failure mark.

[0056] In this step, the group corresponding to the second fault mark can be obtained by querying the table stored in step S240 above. For example, Figure 3 The group corresponding to the first row and first column is the group corresponding to the second failure mark.

[0057] S420: Obtain the data corresponding to the first failure mark from the group corresponding to the second failure mark.

[0058] Step S410 has already restricted the data to groups containing only failed data. In this step, the data marked as the first failure flag 1 is found by querying each group.

[0059] S430: Obtain the data address based on the data corresponding to the first failure marker to locate the failure data.

[0060] S440: Repair the faulty data at the data address according to the location.

[0061] In this embodiment, the method for repairing the failed data can be executed by a host computer.

[0062] like Figure 5 The diagram shown is a schematic representation of the integrated structure for storing and repairing test data provided in an embodiment of this application.

[0063] First, the graphics generator ALPG of the automated test equipment ATE generates an excitation signal and loads it onto the DDR chip under test. The DDR responds to the excitation signal and then compares the response result with the excitation signal output by the automated test equipment ATE in a logic comparator. The comparison result is then stored in the memory as described in the above embodiment. Next, the host computer retrieves the relevant data in the memory to obtain the address of the failed data, thereby realizing the repair of the failed data.

[0064] Another embodiment of this application provides a storage device for failed data. This device can be implemented by a software system, a hardware device, or a combination of both. It should be understood that the storage device and the method for storing failed data are based on the same concept. Since the principles by which the method and device solve problems are similar, the implementation of the device and method can refer to each other, and repeated details will not be elaborated further.

[0065] It should be understood that Figure 6 This is merely an illustrative structural diagram of a storage device for failed data; this application does not limit the division of functional modules within such a storage device. Figure 6 As shown, the storage device for failure data can be logically divided into multiple modules, each module having different functions. The function of each module is implemented by a processor in an electronic device reading and executing instructions from the memory. For example, the storage device for failure data includes a response module 610, a logical comparison module 620, a grouping module 630, and a storage module 640.

[0066] In one alternative implementation, the storage device for the failure data is used to perform... Figure 2 The steps S210-S240 shown are described. Specifically, it can be: a response module 610, used to respond to an excitation signal applied to the chip under test and generate a response signal; the excitation signal is generated by the pattern generator of the automatic test equipment. Specifically, the generation process of the excitation signal includes the pattern generator of the automatic test equipment generating address signal data, clock signal data, and enable signal data; and modulating the address signal data, clock signal data, and enable signal data to obtain the excitation signal.

[0067] A logic comparison module 620 is used to logically compare the response signal and the excitation signal to obtain a comparison result, and to assign a first mark to the comparison result; the comparison result includes failure data and normal data. A grouping module 630 is used to group the comparison result according to a preset rule and assign a second mark to each group according to the first mark. A storage module 640 is used to store each group and the second mark corresponding to each group.

[0068] In some embodiments, the logic comparison module 620 is further configured to mark the comparison result as a first failure mark when the comparison result is invalid data, and to mark the comparison result as a first normal mark when the comparison result is normal data.

[0069] In some embodiments, the grouping module 630 is further configured to sort the comparison results according to the order in which the comparison results were generated; and to group the sorted comparison results by sequentially truncating them according to a preset data length.

[0070] In some embodiments, the grouping module 630 is further configured to mark a group as a second failure mark when the failure data exists in the group; and to mark a group as a second normal mark when the failure data does not exist in the group.

[0071] In some embodiments, the storage module 640 is further configured to store the data information in each group and the second tag corresponding to each group; wherein the data information includes at least a data address.

[0072] This application also provides a computing device, including a processor and a memory. The memory stores program instructions, which, when executed by the processor, cause the processor to perform certain actions. Figure 2 The method of the corresponding embodiment, or various optional embodiments thereof.

[0073] Figure 7 This is a schematic structural diagram of a computing device 900 provided in an embodiment of this application. The computing device 900 includes a processor 910 and a memory 920.

[0074] It should be understood that Figure 7 The computing device 900 shown may also include a communication interface 930, which can be used to communicate with other devices.

[0075] The processor 910 can be connected to the memory 920. The memory 920 can be used to store the program code and data. Therefore, the memory 920 can be a storage unit inside the processor 910, an external storage unit independent of the processor 910, or a component that includes both the storage unit inside the processor 910 and the external storage unit independent of the processor 910.

[0076] Optionally, the computing device 900 may also include a bus. The memory 920 and communication interface 930 can be connected to the processor 910 via the bus. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0077] It should be understood that in the embodiments of this application, the processor 910 may be a Central Processing Unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. Alternatively, the processor 910 may employ one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0078] The memory 920 may include read-only memory and random access memory, and provides instructions and data to the processor 910. A portion of the processor 910 may also include non-volatile random access memory. For example, the processor 910 may also store device type information.

[0079] When the computing device 900 is running, the processor 910 executes the computer execution instructions in the memory 920 to perform the operation steps of the above method.

[0080] It should be understood that the computing device 900 according to the embodiments of this application can correspond to the corresponding subject in executing the methods according to the various embodiments of this application, and the above and other operations and / or functions of each module in the computing device 900 are respectively for implementing the corresponding processes of the methods of this embodiment. For the sake of brevity, they will not be described in detail here.

[0081] This application also provides another computing device, such as... Figure 8 The diagram shown is a schematic structural representation of another computing device 1000 provided in this embodiment, including a processor 1010 and an interface circuit 1020. The processor 1010 accesses a memory through the interface circuit 1020. The memory stores program instructions, which, when executed by the processor, cause the processor to perform certain actions. Figure 2 The method of the corresponding embodiment. Additionally, the computing device may also include a communication interface, a bus, etc., as detailed in the following examples. Figure 7 The descriptions in the illustrated embodiments will not be repeated. For example, the interface circuit 1020 can be a CAN bus or a LIN bus.

[0082] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0083] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0084] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0085] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0086] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0087] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0088] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, performs a method for storing failed data or a method for repairing failed data, the method including at least one of the solutions described in the above embodiments.

[0089] The computer storage medium in this application embodiment can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0090] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0091] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including, but not limited to, wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0092] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0093] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this application, all of which fall within the scope of protection of this application.

Claims

1. A method for storing failed data, characterized in that, include: It responds to the excitation signal applied to the chip under test and generates a response signal; The excitation signal is generated by the graphic generator of the automatic testing equipment; The response signal and the excitation signal are logically compared to obtain a comparison result, and the comparison result is marked with a first label; the comparison result includes failure data and normal data. The comparison results are grouped according to a preset rule, and each group is labeled with a second label based on the first label. Store each group and the second tag corresponding to each group; Storing each group and the corresponding second tag includes: The data information in each group and the second tag corresponding to each group are stored; wherein, the data information includes only the data address; The step of grouping the comparison results according to preset rules includes: The comparison results are sorted according to the order in which they were generated. The sorted comparison results are then truncated according to a preset data length to group the comparison results.

2. The method according to claim 1, characterized in that, The first labeling of the comparison result includes: When the comparison result is invalid data, the comparison result is marked as a first invalidation mark; When the comparison result is normal data, the comparison result is marked as the first normal label.

3. The method according to claim 1, characterized in that, The step of marking each group with a second label based on the first label includes: When the failed data is present in a group, the group is marked as a second failure tag; If the failed data is not present in a group, the group is marked as the second normal group.

4. The method according to claim 1, characterized in that, The excitation signal is generated by the pattern generator of the automatic testing equipment, including: The automatic testing equipment's graphics generator generates address signal data, clock signal data, and enable signal data; The address signal data, clock signal data, and enable signal data are modulated to obtain the excitation signal.

5. A storage device for expired data, characterized in that, include: The response module is used to respond to the excitation signal applied to the chip under test and generate a response signal; The excitation signal is generated by the graphic generator of the automatic testing equipment; A logic comparison module is used to perform a logical comparison between the response signal and the excitation signal, obtain a comparison result, and assign a first mark to the comparison result; The comparison results include failure data and normal data; The grouping module is used to group the comparison results according to a preset rule and to assign a second label to each group based on the first label. A storage module is used to store each group and the second tag corresponding to each group; The storage module is specifically used to: store the data information in each group and the second tag corresponding to each group; wherein, the data information includes only the data address; In the grouping module, the comparison results are grouped according to preset rules, specifically for: The comparison results are sorted according to the order in which they were generated. The sorted comparison results are then truncated according to a preset data length to group the comparison results.

6. A computing device, characterized in that, include: Processor, and memory; The memory stores program instructions thereon, which, when executed by the processor, cause the processor to perform a method for storing invalid data as described in any one of claims 1-4.

7. A computer-readable storage medium having program instructions stored thereon, characterized in that, When the program instructions are executed by a computer, the computer performs a method for storing invalid data as described in any one of claims 1-4.

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