A method and apparatus for enhancing stability of digital pre-distortion

Abstract

A method and device for enhancing the stability of digital pre-distortion, by increasing the random lock number indication, controlling the random lock number start and end point range to be greater than the LMS calculation coefficient logic processing time, and the lock number start point being random each time, thus breaking the equal interval sampling problem and being able to cover the entire service data in a long period of time, so that the LMS training coefficient can theoretically cover all the input data in a long period of time, fundamentally solving the coefficient instability problem caused by the inevitable engineering implementation method. If the method is used in actual products, the logic design difficulty can be greatly reduced, and it is convenient for large-scale normal logic link development, and brings advantages for ASIC chip reduction of area power consumption.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more specifically, to a method and apparatus for enhancing digital predistortion stability. Background Technology

[0002] Nonlinearity introduced by active devices is common in wireless communication systems. Digital predistortion is a very effective solution, enabling predistortion before the input to the nonlinear device. Currently, common system architectures fall into two categories: open-loop and closed-loop systems. Closed-loop systems are the most prevalent, primarily represented by algorithms such as Least Mean Square (LMS) and Least Squares (LS). While the Least Squares (LS) algorithm suffers from computational complexity, LMS is the preferred choice for real-time applications due to its ease of implementation and remarkable robustness. However, LMS is susceptible to poor input conditioning or insufficient stimulation, leading to unstable training structures.

[0003] In engineering implementation, many measures have been taken to address the stability issue of the LMS algorithm. For example, the Leakge method is applied to the coefficients to improve stability under high-precision requirements; and the iteration step size is adjusted to improve the convergence stability of LMS. These measures play a leading role in adjusting the stability of the LMS algorithm coefficients, and their effectiveness can be derived through mathematical formula analysis. However, the problems we face in actual engineering cannot be analyzed using mathematical formulas; they are unavoidable issues in the actual logic development process, such as... Figure 1 As shown, the data stream is interrupted regularly, which is equivalent to sampling at equal intervals. The LMS algorithm requires, according to its mathematical formula, that all training samples be used to train coefficients within a certain time period or long period. If data is missed, special abnormal data may cause abnormal coefficient convergence, which may lead to the burnout of active devices.

[0004] In the logical implementation of the LMS algorithm coefficient calculation steps, it is necessary to first lock a data segment of effective length for the data required for calculation. This locked data is then used for LMS coefficient iteration. Logical iteration calculation of coefficients requires a fixed sampling time. However, during this sampling time, the signal data stream is still flowing. Therefore, when the previous coefficient calculation is completed and the next locking is performed, the new locking result is not continuous with the previously locked data. A segment of data is lost and not used for LMS training. In the long run, the data processed in each locking iteration is actually a continuous sampling of business data at equal intervals. According to LMS theory, insufficient sample training poses a risk of LMS divergence.

[0005] Therefore, how to provide a method to enhance the stability of digital predistortion is an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned problems, the present invention provides a method and apparatus for enhancing the stability of digital predistortion.

[0007] A first aspect of the present invention provides a method for enhancing digital predistortion stability, the method comprising:

[0008] Implement digital predistortion structure using the LMS algorithm;

[0009] A random indication signal is generated based on the current signal time using a random sequence generator;

[0010] The number of locks is determined based on the random indication signal for the digital predistortion modeling signal and the error signal, and the lock depth is equal to the longest memory depth of the digital predistortion modeling signal.

[0011] The latched data is used to calculate the LMS solution coefficients using the LMS algorithm.

[0012] Repeat the above process, iterating until the LMS solution coefficients converge.

[0013] Optionally, the method by which the random sequence generator generates a random indication signal based on the current signal time is as follows:

[0014] The relationship between the random sequence generator indicating time t and the current signal time tn is:

[0015]

[0016] Where N is the longest memory depth of the digital predistortion modeling signal.

[0017] Optionally, the method for calculating the LMS solution coefficients using the LMS algorithm on the latched data is as follows:

[0018] The LMS solution coefficients are calculated using the following formula.

[0019]

[0020] Where x(n) is the ideal transmit signal of digital predistortion, f(x(n)) is the digital predistortion modeling signal, fb(n) is the signal that the PA loop returns to the feedback, y(n) is the predistortion output signal, w(n) is the predistortion coefficient, and the error signal e(n) is the difference between the transmit signal x(n) and the feedback signal fb(n).

[0021] Optionally, the step of locking the number of the digital predistortion modeling signal and the error signal according to the random indication signal specifically includes:

[0022] 15 consecutive data points are locked onto the digital predistortion modeling signal;

[0023] Lock one data point for the error signal.

[0024] Optionally, after each iteration of calculating the LMS solution coefficients, a flag indicator is output;

[0025] The flag indicates that the random sequence generator is used to re-trigger the random sequence generator to generate a random indication signal.

[0026] Optionally, the random sequence generator generates a random indication signal according to a set time delay value.

[0027] Optionally, the random sequence generator consists of a pseudo-random sequence generator and an XOR gate.

[0028] A second aspect of the present invention provides an apparatus for enhancing digital predistortion stability, the apparatus comprising:

[0029] The structural implementation unit uses the LMS algorithm to implement the digital predistortion structure;

[0030] The random generation unit is used to generate a random indication signal based on the current signal time using a random sequence generator.

[0031] The random locking unit is used to lock the digital predistortion modeling signal and the error signal according to the random indication signal, and the locking depth is equal to the longest memory depth of the digital predistortion modeling signal;

[0032] The coefficient calculation unit is used to perform LMS solution coefficient calculation on the latched data using the LMS algorithm.

[0033] The iterative control unit is used to repeat the above process and iterate until the LMS solution coefficients converge.

[0034] A third aspect of the present invention provides an electronic device, characterized in that it comprises:

[0035] One or more processors; memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications being configured to perform the method as described in the first aspect.

[0036] A fourth aspect of the present invention provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores program code that can be invoked by a processor to execute the method described in the first aspect.

[0037] In summary, this invention provides a method, apparatus, electronic device, and storage medium to enhance the stability of digital predistortion. By adding a random lock number indicator, controlling the start and end range of the random lock number to be greater than the logic processing time for LMS coefficient calculation, and ensuring that the lock number start is random each time, the problem of equal-interval sampling is overcome, and the entire business data can be covered over a long period. This allows all input data to be theoretically completely covered during LMS coefficient training, fundamentally solving the coefficient instability problem caused by unavoidable engineering implementation methods. If this method is adopted in actual products, it can significantly reduce the difficulty of logic design and facilitate the development of large-scale, routine logic links, providing advantages for ASIC chip development in terms of reduced area and power consumption. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the existing lock count behavior without random lock count;

[0040] Figure 2 This is a flowchart of a method for enhancing digital predistortion stability according to an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of the structure of a random sequence generator according to an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of the lock number control logic according to an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of the locking behavior under the indication of the indication signal in an embodiment of the present invention.

[0044] Figure 6 This is a schematic diagram of the result after applying DPD predistortion correction to the LMS algorithm with random lock number in an embodiment of the present invention;

[0045] Figure 7 This is a schematic diagram of the random lock number indication result value of the LMS algorithm with random lock number used in an embodiment of the present invention;

[0046] Figure 8 This is a functional block diagram of a device for enhancing digital predistortion stability according to an embodiment of the present invention;

[0047] Figure 9This is a structural block diagram of an electronic device for performing a method for enhancing digital predistortion stability according to an embodiment of the present invention.

[0048] Figure 10 This is a structural block diagram of a computer-readable storage medium for storing or carrying program code implementing a method for enhancing digital predistortion stability according to an embodiment of the present invention.

[0049] Figure label:

[0050] Structure implementation unit 110; random generation unit 120; random number locking unit 130; coefficient calculation unit 140; iterative control unit 150; electronic device 300; processor 310; memory 320; computer-readable storage medium 400; program code 410. Detailed Implementation

[0051] Nonlinearity introduced by active devices is common in wireless communication systems. Digital predistortion is a very effective solution, enabling predistortion before the input to the nonlinear device. Currently, common system architectures fall into two categories: open-loop and closed-loop systems. Closed-loop systems are the most prevalent, primarily represented by algorithms such as Least Mean Square (LMS) and Least Squares (LS). While the Least Squares (LS) algorithm suffers from computational complexity, LMS is the preferred choice for real-time applications due to its ease of implementation and remarkable robustness. However, LMS is susceptible to poor input conditioning or insufficient stimulation, leading to unstable training structures.

[0052] In engineering implementation, many measures have been taken to address the stability issue of the LMS algorithm. For example, the Leakge method is applied to the coefficients to improve stability under high-precision requirements; and the iteration step size is adjusted to improve the convergence stability of LMS. These measures play a leading role in adjusting the stability of the LMS algorithm coefficients, and their effectiveness can be derived through mathematical formula analysis. However, the problems we face in actual engineering cannot be analyzed using mathematical formulas; they are unavoidable issues in the actual logic development process, such as... Figure 1 As shown, the data stream is interrupted regularly, which is equivalent to sampling at equal intervals. The LMS algorithm requires, according to its mathematical formula, that all training samples be used to train coefficients within a certain time period or long period. If data is missed, special abnormal data may cause abnormal coefficient convergence, which may lead to the burnout of active devices.

[0053] In the logical implementation of the LMS algorithm coefficient calculation steps, it is necessary to first lock a data segment of effective length for the data required for calculation. This locked data is then used for LMS coefficient iteration. Logical iteration calculation of coefficients requires a fixed sampling time. However, during this sampling time, the signal data stream is still flowing. Therefore, when the previous coefficient calculation is completed and the next locking is performed, the new locking result is not continuous with the previously locked data. A segment of data is lost and not used for LMS training. In the long run, the data processed in each locking iteration is actually a continuous sampling of business data at equal intervals. According to LMS theory, insufficient sample training poses a risk of LMS divergence.

[0054] Therefore, how to provide a method to enhance the stability of digital predistortion is an urgent problem to be solved.

[0055] In view of this, the present invention provides a method to enhance the stability of digital predistortion, which is used to overcome the unavoidable problem of training data with equally spaced periodic sampling in actual logic engineering implementation, thus leading to abnormal coefficient calculation results in the LMS algorithm. By adding a random lock number indicator, all input data can theoretically be completely covered in the long term during LMS coefficient training, which fundamentally solves the coefficient instability problem caused by unavoidable engineering implementation methods.

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0058] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0059] In the description of this invention, it should be noted that the terms "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In addition, the terms "first," "second," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0060] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0061] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0062] This invention addresses the contradictions encountered in the practical engineering application of theoretical mathematical formulas. Because the logic implementation of the LMS algorithm is a data stream processing, and due to the fixed logic processing delay, the actual data to be calculated is the signal after being extracted at fixed intervals. This makes it impossible to train pre-distortion coefficients on all signal data, which in turn affects the performance of the LMS algorithm coefficients.

[0063] Furthermore, during long-term testing in actual engineering projects (generally starting from hours), the inventors discovered that the LMS algorithm also exhibits periodic divergence. Theoretical analysis revealed that when the 10ms periodic data of the communication system is an integer multiple of the LMS convergence period, the LMS convergence equilibrium is disrupted. To completely resolve these issues and improve the long-term stability of the LMS algorithm, a random locking mechanism was introduced to disrupt the data period used for coefficient calculation.

[0064] Therefore, to address the issue of unavoidable logical delays in implementation causing data sampling and thus affecting the stability of the LMS algorithm, please refer to [link / reference needed]. Figure 2 The present invention provides a method for enhancing digital predistortion stability, the method comprising:

[0065] Step S101: Implement the digital predistortion structure using the LMS algorithm.

[0066] For specific application scenarios, LMS is used to implement the digital predistortion structure at fixed points.

[0067] In this embodiment, the specific digital predistortion structure is as follows:

[0068]

[0069] In the above formula, x(n) is the ideal transmit signal of digital predistortion, f(x(n)) is the digital predistortion modeling signal, fb(n) is the signal of PA loop back to feedback, y(n) is the predistortion output signal, w(n) is the predistortion coefficient, and the error signal e(n) is the difference between the transmit signal x(n) and the feedback signal fb(n).

[0070] Step S102: Generate a random indication signal based on the current signal time using a random sequence generator.

[0071] The method by which the random sequence generator generates a random indication signal based on the current signal time is as follows:

[0072] The random sequence generator indicates the time t and the current signal time t. n The relationship is

[0073]

[0074] Where N is the longest memory depth of the digital predistortion modeling signal.

[0075] Specifically, such as Figure 3 As shown, the random sequence generator consists of a pseudo-random sequence generator and an XOR gate. During operation, the pseudo-random sequence generator continuously performs shifts, and an XOR gate is added to each shift. This is equivalent to the value in the register changing with each shift. This continuous shifting and changing generates pseudo-random numbers.

[0076] Taking a 32-bit shift register as an example, the XOR gate polynomial is designed as [101000011], corresponding to x 8 +x 6 +x+1. The shift register moves constantly, outputting x according to a polynomial. 8 +x 6 The value of +x+1 is modulo 7. The reason for this modulo operation is that in actual development projects, the longest memory depth processed by digital predistortion is 15 beats, i.e., N=15. The random indicator signal output time must be within (N-1) / 2 before the current time's endpoint, corresponding to a group delay of 7 beats. The high pulse of the modulo output is the random indicator signal, used in subsequent number locking steps, such as... Figure 3 As shown.

[0077] Step S103: Lock the digital predistortion modeling signal and the error signal according to the random indication signal, and the locking depth is equal to the longest memory depth of the digital predistortion modeling signal.

[0078] To ensure that the number of random starting point locks can cover all data in the long run, the lock depth is equal to the longest memory depth N of the digital predistortion modeling signal.

[0079] Specific lock counting methods include:

[0080] Lock 15 data points continuously for the digital predistortion modeling signal f(x(n));

[0081] Lock one data point for the error signal x(n).

[0082] Step S104: Calculate the LMS solution coefficients using the LMS algorithm on the latched data.

[0083] The LMS solution coefficients can be calculated based on the latched data. Based on the digital predistortion structure described above, the latched data is then calculated using the following formula and iterated over.

[0084] w(n+1)=w(n)+μ·e(n·f * (x(n))

[0085] w(n) is the predistortion coefficient.

[0086] After each iteration of calculating the LMS solution coefficients, step S105 is executed to determine whether the LMS solution coefficients have converged. If they have not converged, the process returns to step S102 to proceed to the next iteration.

[0087] In a preferred embodiment of the present invention, after each iteration of calculating the LMS solution coefficients, a flag indicator is output; the flag indicator is used to re-trigger the random sequence generator to generate a random indicator signal, which is used to trigger the start of the next iteration.

[0088] In another embodiment of the present invention, during iteration, the random sequence generator may generate a random indication signal according to a set time delay value. The specific time delay value corresponds to the time of each iteration.

[0089] Based on the above description, the iterative execution logic in the method for enhancing digital predistortion stability according to embodiments of the present invention is as follows:

[0090] (1) Configure the initial value of the shift sequence trigger so that the shift register works in a loop;

[0091] (2) Data streams f(x(n)) and e(n) flow in continuously, waiting for the lock signal indication in (1);

[0092] (3) When the lock count indicator signal in (1) is pulled high, the lock count delay value [0~6] is output. The logic continuously locks 15 data f(x(n)) according to the specific delay time value, and simultaneously locks 1 data e(n).

[0093] (4) Use the lock number result value in (3) to input the following formula for coefficient iteration. Coefficient iteration requires a certain logical delay.

[0094] w(n+1)=w(n)+μ·e(n·f * (x(n))

[0095] (5) After completing step (4), repeat steps (2) to (4).

[0096] The following specific example illustrates the random lock number in the method for enhancing digital predistortion stability according to an embodiment of the present invention:

[0097] The test signal in this case is NR100M, the downlink frequency is 2.6G, the carrier frequency is 2.6GHz, and the transceiver chip is Baize 20.

[0098] The implementation method includes S1: building a fixed-point LMS algorithm implementation link to implement DPD (Digital Predistortion) engineering, and building an external loopback simulation link; S2: transmitting 10ms cell service data, conducting effective testing, enabling the random number locking unit, setting the memory depth to 15, and setting the random sequence generator to remainder 7; S3: observing the output pattern and range of the random number locking, and observing the long-term stability of the solution coefficients and the performance of digital predistortion correction.

[0099] The mathematical formula for the DPD predistortion link built in S1 is: where the baseband signal x(n) is the NR100M signal, f(x(n)) is the DPD modeling signal, y(n) is the digital predistortion signal, w(n) is the predistortion coefficient, and fb(n) is the data entering the Baize 20ORX channel after the system loops back through the PA and is connected to an external attenuator.

[0100]

[0101] During execution, the random sequence generator is enabled and triggered after each iteration, and the output signal indicates that the iteration continues until the LMS solution coefficients converge. By observing the random lock number indicator value, as well as the solution performance and coefficient convergence trend, the effectiveness of the method for enhancing digital predistortion stability provided by this invention is demonstrated.

[0102] The result of locking the number using a random sequence generator is as follows: Figure 5As shown in the diagram, since the starting point for the lock count is no longer fixed, and the length of the lock count data is greater than the logic processing latency, it is guaranteed that the random starting point lock count data can cover all data in the long run. The result distribution generated by the random lock count generator is a Gaussian white noise distribution.

[0103] Figure 6 The display shows the performance after digital predistortion correction, as well as the changes in the compensation coefficients over time. It is clear that introducing random locks effectively guarantees the performance of the LMS algorithm and the long-term stability of the coefficients. Figure 7 Show corresponding Figure 6 The output indicator shows the random lock count at certain times, and you can see that the starting value of the random lock count is different at different times.

[0104] In summary, this invention provides a method to enhance the stability of digital predistortion. By adding a random lock number indicator, controlling the range of the random lock number's start and end points to be greater than the logic processing time for LMS coefficient calculation, and ensuring that the lock number's start point is random each time, the problem of equal-interval sampling is overcome, and the entire business data can be covered over a long period. This allows all input data to be theoretically completely covered during LMS coefficient training, fundamentally solving the coefficient instability problem caused by unavoidable engineering implementation methods. If this method is adopted in actual products, it can significantly reduce the difficulty of logic design and facilitate the development of large-scale, routine logic links, bringing advantages to ASIC chip development by reducing area and power consumption.

[0105] like Figure 5 As shown, the present invention provides an apparatus for enhancing digital predistortion stability, the apparatus comprising:

[0106] Structural implementation unit 110 uses the LMS algorithm to implement the digital predistortion structure;

[0107] The random generation unit 120 is used to generate a random indication signal based on the current signal time using a random sequence generator;

[0108] The random locking unit 130 is used to lock the digital predistortion modeling signal and the error signal according to the random indication signal, and the locking depth is equal to the longest memory depth of the digital predistortion modeling signal;

[0109] The coefficient calculation unit 140 is used to perform LMS solution coefficient calculation on the latched data using the LMS algorithm.

[0110] The iterative control unit 150 is used to repeat the above process and continue iterating until the LMS solution coefficients converge.

[0111] The apparatus for enhancing digital predistortion stability provided in this embodiment of the invention is used to implement the above-described method for enhancing digital predistortion stability. Therefore, the specific implementation method is the same as the above-described method and will not be repeated here.

[0112] like Figure 6 The diagram shows a structural block diagram of an electronic device 300 provided in an embodiment of the present invention. This electronic device 300 can be a smartphone, tablet computer, e-reader, or other electronic device capable of running applications. The electronic device 300 in this application may include one or more of the following components: a processor 310, a memory 320, and one or more applications, wherein the one or more applications can be stored in the memory 320 and configured to be executed by one or more processors 310, and the one or more applications are configured to perform the methods described in the foregoing method embodiments.

[0113] Processor 310 may include one or more processing cores. Processor 310 connects to various parts within the electronic device 300 using various interfaces and lines, and performs various functions and processes data of the electronic device 300 by running or executing instructions, programs, code sets, or instruction sets stored in memory 320, and by calling data stored in memory 320. Optionally, processor 310 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). Processor 310 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the displayed content; and the modem handles wireless communication. It is understood that the modem may also not be integrated into processor 310 and may be implemented separately using a communication chip.

[0114] The memory 320 may include random access memory (RAM) or read-only memory (ROM). The memory 320 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 320 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as touch functionality, sound playback functionality, image playback functionality, etc.), and instructions for implementing the various method embodiments described below. The data storage area may also store data created by the terminal during use (such as phonebook data, audio and video data, chat log data, etc.).

[0115] like Figure 7 The diagram shows a structural block diagram of a computer-readable storage medium 400 provided in an embodiment of the present invention. The computer-readable medium stores program code 410, which can be called by a processor to execute the methods described in the above method embodiments.

[0116] The computer-readable storage medium 400 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium 400 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 400 has storage space for program code 410 that performs any of the method steps described above. This program code 410 can be read from or written to one or more computer program products. The program code 410 may, for example, be compressed in a suitable form.

[0117] In summary, this invention provides a method, apparatus, electronic device, and storage medium to enhance the stability of digital predistortion. By adding a random lock number indicator, controlling the start and end range of the random lock number to be greater than the logic processing time for LMS coefficient calculation, and ensuring that the lock number start is random each time, the problem of equal-interval sampling is overcome, and the entire business data can be covered over a long period. This allows all input data to be theoretically completely covered during LMS coefficient training, fundamentally solving the coefficient instability problem caused by unavoidable engineering implementation methods. If this method is adopted in actual products, it can significantly reduce the difficulty of logic design and facilitate the development of large-scale, routine logic links, providing advantages for ASIC chip development in terms of reduced area and power consumption.

[0118] In the embodiments disclosed in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0119] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0120] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A method for enhancing the stability of digital predistortion, characterized in that, The method includes: Implement digital predistortion structure using the LMS algorithm; A random indication signal is generated based on the current signal time using a random sequence generator; The number of locks is determined based on the random indication signal for the digital predistortion modeling signal and the error signal, and the lock depth is equal to the longest memory depth of the digital predistortion modeling signal. The latched data is used to calculate the LMS solution coefficients using the LMS algorithm. Repeat the above process, iterating until the LMS solution coefficients converge; After each iteration of calculating the LMS solution coefficients, a flag indicator is output; the flag indicator is used to re-trigger the random sequence generator to generate a random indicator signal. The method by which the random sequence generator generates a random indication signal based on the current signal time is as follows: The relationship between the random sequence generator indicating time t and the current signal time tn is: ; Where N is the longest memory depth of the digital predistortion modeling signal; The step of locking the digital predistortion modeling signal and the error signal according to the random indication signal specifically includes: The number of consecutive locks is determined by the specific time delay value of the random indication signal; 15 data points are continuously locked for the digital predistortion modeling signal; and 1 data point is locked for the error signal.

2. The method for enhancing digital predistortion stability according to claim 1, characterized in that, The method for calculating the LMS solution coefficients using the LMS algorithm on the latched data is as follows: The LMS solution coefficients are calculated using the following formula. in, It is an ideal transmitted signal with digital predistortion. It is a digital predistortion modeling signal. It is the signal that the PA loop returns to the feedback. It is a predistorted output signal. It is the predistortion coefficient. This is the transpose matrix of the predistortion coefficients, w(n+1) is the predistortion coefficient at the next time step, and the error signal. It is a transmitted signal With feedback signal The difference, where μ represents the step size factor. It is the conjugate of the digital predistortion modeling signal.

3. The method for enhancing digital predistortion stability according to claim 2, characterized in that, The random sequence generator generates a random indication signal according to a set time delay value.

4. The method for enhancing digital predistortion stability according to claim 3, characterized in that, The random sequence generator consists of a pseudo-random sequence generator and an XOR gate.

5. A device for enhancing the stability of digital predistortion, characterized in that, The device includes: The structural implementation unit uses the LMS algorithm to implement the digital predistortion structure; The random generation unit is used to generate a random indication signal based on the current signal time using a random sequence generator. The random locking unit is used to lock the digital predistortion modeling signal and the error signal according to the random indication signal, and the locking depth is equal to the longest memory depth of the digital predistortion modeling signal; The coefficient calculation unit is used to perform LMS solution coefficient calculation on the latched data using the LMS algorithm. An iterative control unit is used to repeat the above process and iterate until the LMS solution coefficients converge. After each iteration, the LMS solution coefficients are calculated, and a flag indicator is output. The flag indicator is used to re-trigger the random sequence generator to generate a random indicator signal. The method by which the random sequence generator generates a random indication signal based on the current signal time is as follows: The relationship between the random sequence generator indicating time t and the current signal time tn is: ; Where N is the longest memory depth of the digital predistortion modeling signal; The random number lock unit is specifically used for: The number of consecutive locks is determined by the specific time delay value of the random indication signal; 15 data points are continuously locked for the digital predistortion modeling signal; and 1 data point is locked for the error signal.

6. An electronic device, characterized in that, include: One or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications being configured to perform the method as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program code that can be invoked by a processor to execute the method as described in any one of claims 1-4.

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