Method, device and computer equipment for machine recognition of RTL code module connection relationships
By using machine recognition to identify the connection relationships between RTL code modules, and processing the RTL code with Verilog syntax rules and identifiers, concise connection relationship tables or diagrams are generated. This solves the problem of time-consuming and laborious manual coding by backend engineers, and improves the efficiency and accuracy of chip development.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2023-03-02
- Publication Date
- 2026-07-31
AI Technical Summary
In chip development, backend engineers often lack specialized software to view the connection relationships of RTL code modules, leading to time-consuming, laborious, and error-prone manual coding, especially in complex circuits with numerous and intricate connections.
Using machine recognition methods, Verilog syntax rules and special identifiers are used to preprocess, classify and match RTL code, generating tables or charts of connection relationships, simplifying them into a format that non-front-end engineers can view.
Quickly generate tables or charts showing connection relationships, reducing the workload of front-end engineers, improving accuracy and efficiency, and reducing human error.
Smart Images
Figure CN116187230B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and in particular to a machine identification method, apparatus, computer device, and storage medium for RTL code module connection relationships. Background Technology
[0002] In integrated circuit design, the register-transfer level (RTL) is an abstraction level used to describe the operation of synchronous digital circuits. At the RTL level, an IC consists of a set of registers and the logical operations between them. This is because most circuits can be viewed as having registers storing binary data, logical operations between registers performing data processing, and the data processing flow controlled by a sequential state machine. These processes and controls can be described using a hardware description language.
[0003] In chip development, front-end engineers typically use specialized software like Verdi and Vivado to view signal connections in their RTL code. However, back-end engineers, who also need to view the connections between modules, generally don't have this software. Manually writing the connection relationships for each module by front-end engineers is time-consuming and labor-intensive. Furthermore, a typical project involves thousands of interconnected wires, some of which are interconnected, creating a complex and intricate network that leads to a high error rate. Summary of the Invention
[0004] Therefore, it is necessary to provide a machine identification method, apparatus, computer device, and storage medium for RTL code module connection relationships to address the aforementioned technical problems.
[0005] A machine identification method for RTL code module connection relationships, the method comprising:
[0006] Machine recognition request to obtain the connection relationship of RTL code modules;
[0007] The code is preprocessed according to the machine recognition request, and the code specifications are unified through special identifiers;
[0008] Read the standardized code line by line and categorize it according to Verilog syntax rules;
[0009] Based on the content identified through classification, perform category matching and input the data into a dictionary;
[0010] The results of category matching are classified and the processed structure is output in a formatted format.
[0011] In one embodiment, the step of preprocessing the code according to the machine recognition request and unifying the code specifications through special identifiers further includes:
[0012] By identifying and judging identifiers, comment text and macro definitions can be detected;
[0013] Type groups are split to unify data type definitions.
[0014] In one embodiment, the step of reading the canonicalized code line by line and classifying it according to Verilog syntax rules further includes:
[0015] Enter the content after " / / " into the remarks array until the end of the line;
[0016] Enter the content after " / *" into the remarks array until "* / " is read;
[0017] The content after "parameter" is entered into the parameter array until ";" is read, and the array is monitored to see if it contains "[", "]" and ":". The data is then read as the bit width.
[0018] According to Verilog syntax rules, they are classified into IO classes, connection classes, parameter classes, and module classes.
[0019] In one embodiment, the step of performing category matching and entering the dictionary based on the content identified by the classification further includes:
[0020] The content identified by classification is categorized, processed, and entered into a dictionary, which includes the module name, parameters, I / O items, wire register items, submodule items, and the connecting wires contained in each module.
[0021] Read the code of each module, record the corresponding dictionary, and find the project parameters of each module by traversing the table.
[0022] A machine identification device for RTL code module connection relationships, the device comprising:
[0023] The acquisition module is used to acquire machine recognition requests for the connection relationships of RTL code modules;
[0024] The preprocessing module is used to preprocess the code according to the machine recognition request and to unify the code specifications through special identifiers;
[0025] A classification module is used to read the standardized code line by line and classify it according to Verilog syntax rules;
[0026] The matching and input module is used to perform category matching and input into a dictionary based on the content identified by the classification.
[0027] The result output module is used to classify the results based on the category matching and output the processed structure in a formatted manner.
[0028] In one embodiment, the preprocessing module is further configured to:
[0029] By identifying and judging identifiers, comment text and macro definitions can be detected;
[0030] Type groups are split to unify data type definitions.
[0031] In one embodiment, the classification module is further configured to:
[0032] Enter the content after " / / " into the remarks array until the end of the line;
[0033] Enter the content after " / *" into the remarks array until "* / " is read;
[0034] The content after "parameter" is entered into the parameter array until ";" is read, and the array is monitored to see if it contains "[", "]" and ":". The data is then read as the bit width.
[0035] According to Verilog syntax rules, they are classified into IO classes, connection classes, parameter classes, and module classes.
[0036] In one embodiment, the matching and input module is further configured to:
[0037] The content identified by classification is categorized, processed, and entered into a dictionary, which includes the module name, parameters, I / O items, wire register items, submodule items, and the connecting wires contained in each module.
[0038] Read the code of each module, record the corresponding dictionary, and find the project parameters of each module by traversing the table.
[0039] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.
[0040] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.
[0041] The aforementioned machine recognition method, apparatus, computer equipment, and storage medium for RTL code module connection relationships obtain machine recognition requests for RTL code module connection relationships; preprocess the code according to the machine recognition requests, unifying code specifications through special identifiers; read the standardized code line by line and classify it according to Verilog syntax rules; perform category matching based on the identified content and input it into a dictionary; perform classification processing based on the category matching results and output the processed structure in a formatted format. This invention, through machine recognition, completes the identification and organization of RTL hierarchical relationships and signal connection relationships between modules, and presents them in a common format, generating tables or charts of connection relationships in seconds for viewing by non-front-end personnel. Attached Figure Description
[0042] Figure 1 This is a flowchart illustrating a machine recognition method for the connection relationship of RTL code modules in one embodiment;
[0043] Figure 2 This is a schematic diagram of the code preprocessing process in one embodiment;
[0044] Figure 3 This is a flowchart illustrating a machine recognition method for RTL code module connection relationships in another embodiment;
[0045] Figure 4 This is a flowchart illustrating the machine recognition method for the connection relationship of RTL code modules in another embodiment;
[0046] Figure 5 This is a schematic diagram illustrating category matching and dictionary entry in one embodiment;
[0047] Figure 6 This is a schematic diagram illustrating the generation of a signal connection table for each module in one embodiment;
[0048] Figure 7 This is a schematic diagram illustrating the hierarchical relationship between modules in one embodiment;
[0049] Figure 8 This is a structural block diagram of a machine recognition device showing the connection relationship of RTL code modules in one embodiment.
[0050] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0052] Currently, in chip development, front-end engineers typically use specialized software like Verdi and Vivado to view signal connections in the RTL code they write. However, back-end engineers, who also need to view the connections between modules, generally don't have this software. Manually writing the connection relationships for each module by front-end engineers is time-consuming and labor-intensive. Furthermore, projects often involve thousands of interconnected wires, creating a complex and intricate network that leads to a high error rate.
[0053] Based on this, the present invention proposes a machine recognition method for the connection relationship of RTL code modules, which aims to quickly complete the RTL hierarchical relationship and the signal connection relationship of each module, and present them in a universal format.
[0054] In one embodiment, such as Figure 1 As shown, a machine identification method for RTL code module connection relationships is provided, the method including:
[0055] Step 102: Obtain the machine recognition request for the connection relationship of RTL code modules;
[0056] Step 104: Preprocess the code according to the machine recognition request, and unify the code specifications through special identifiers;
[0057] Step 106: Read the standardized code line by line and classify it according to Verilog syntax rules;
[0058] Step 108: Perform category matching based on the identified content and enter it into the dictionary;
[0059] Step 110: Perform classification processing based on the category matching results and format the output of the processing structure.
[0060] This embodiment provides a machine recognition method for the connection relationships of RTL code modules. This method leverages the clear identifiers inherent in RTL code, such as Verilog syntax, which facilitate machine recognition. For example, symbols like "wire", "reg", "input", "#(", ");" can uniquely identify the purpose of the code. This recognition algorithm replaces manual work, generating a table or chart of connection relationships in seconds, and presenting it in common table or graph formats for easy viewing by non-front-end users.
[0061] Specifically, first, the machine recognition request for the connection relationship of RTL code modules is obtained; the code is preprocessed according to the machine recognition request, and the code specification is unified through special identifiers.
[0062] In one embodiment, the step of preprocessing the code according to the machine recognition request and unifying the code specifications through special identifiers further includes: identifying and judging the identifiers to detect comment text and macro definitions; and splitting type groups to unify data type definitions.
[0063] For specific details, please refer to Figure 2 The code preprocessing flow shown illustrates how different engineers' coding habits lead to vastly different code styles. To facilitate unified machine recognition, this module standardizes code style. For example, two wires might be defined as: `wire wire_a` and `wire_b`; the standardized version would be: `wire wire_a`; `wire wire_b`, etc. Comment text is also retrieved and stored in an array. Some variables from macro definitions are written into the actual code. This operation step completes macro definition retrieval, comment text retrieval, type group splitting, and port matching.
[0064] Next, the standardized code is read line by line and categorized according to Verilog syntax rules. The identified categories are then matched against the corresponding dictionary entries. Finally, the categorized results are processed and the processed structure is output in a formatted format.
[0065] Specifically, the code style is first standardized using special identifiers, and category matching is performed for initial identification. Then, a relational dictionary is established based on the categorized data types. Finally, the relationships are traversed and the results are formatted and output.
[0066] In the above embodiment, a machine recognition request for the connection relationship of RTL code modules is obtained; the code is preprocessed according to the machine recognition request, and the code specification is unified through special identifiers; the standardized code is read line by line and classified according to Verilog syntax rules; the classified content is matched and entered into a dictionary; the classification process is performed according to the results of the category matching, and the processed structure is output in a formatted format. The above solution completes the identification and sorting of the RTL hierarchy and the signal connection relationship of each module through machine recognition, and presents it in a common format. A table or chart of connection relationship can be generated in a few seconds for non-front-end personnel to view.
[0067] In one embodiment, such as Figure 3 As shown, a machine recognition method for RTL code module connection relationships is provided. This method further includes the steps of reading the standardized code line by line and classifying it according to Verilog syntax rules:
[0068] Step 302: Enter the content after " / / " into the remarks array until the end of the line;
[0069] Step 304: Enter the content after “ / *” into the remarks array until “* / ” is read;
[0070] Step 306: Enter the content after "parameter" into the parameter array until ";" is read and monitor whether it contains "[", "]" and ":" to read the data as the bit width;
[0071] Step 308: Classify according to Verilog syntax rules, including IO class, connection class, parameter class and module class.
[0072] In this embodiment, the preprocessed code will be standardized and read line by line, for example:
[0073] 1. Enter the content after " / / " into the remarks array until the end of the line;
[0074] 2. Enter the content after " / *" into the remarks array until you read "* / ";
[0075] 3. Enter the content after "parameter" into the parameter array until ";" is read; and monitor whether it contains "[", "]" and ":" to read the data as the bit width;
[0076] 4. ...
[0077] According to Verilog syntax rules, these can be categorized as follows, generally including: IO classes, connection classes, parameter classes, module classes, etc.
[0078] In one embodiment, such as Figure 4 As shown, a machine recognition method for RTL code module connection relationships is provided. This method further includes the steps of category matching and dictionary entry based on the classified content:
[0079] Step 402: Classify and process the content identified by classification and input it into a dictionary, including the module name, parameters, I / O items, wire register items, sub-module items, and the connecting wires contained in each module;
[0080] Step 404: Read the code of each module, record the corresponding dictionary, and find the project parameters of each module by traversal and record them in the table.
[0081] First, category matching is performed and a dictionary is built. Specifically, for example, the content is categorized based on its relevance to the identified information, and the dictionary is entered, containing the module name, parameters, I / O items, wire register items, submodule items, and the I / O and connected wires contained in this module. The dictionary construction diagram is shown below. Figure 5 As shown.
[0082] Then, statistical output is performed. Specifically, for example, the top-level connection relationships of the project are output by reading the code of each module at the top and second-to-last level, recording the corresponding dictionaries, and then finding the end-to-end connections of the wires in the sub-modules through iteration and recording them in a table. The generated style can be as follows: Figure 6 The connection table shown or as follows Figure 7 The hierarchy diagram shown.
[0083] In this embodiment, tables or charts showing the connection relationships can be generated quickly, making them easy for non-front-end developers to view and saving front-end engineers time in writing code.
[0084] It should be understood that, although Figure 1-7 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1-7 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0085] In one embodiment, such as Figure 8 As shown, a machine identification device 800 for RTL code module connection relationships is provided. The device includes:
[0086] Acquisition module 801, the acquisition module is used to acquire machine recognition requests for RTL code module connection relationships;
[0087] Preprocessing module 802, the preprocessing module is used to preprocess the code according to the machine recognition request, and to unify the code specifications through special identifiers;
[0088] Classification module 803, which is used to read the standardized code line by line and classify it according to Verilog syntax rules;
[0089] The matching and input module 804 is used to perform category matching and input into a dictionary based on the content identified by the classification.
[0090] Result output module 805 is used to classify the results of category matching and output the processed structure in a formatted manner.
[0091] In one embodiment, the preprocessing module 802 is further configured to:
[0092] By identifying and judging identifiers, comment text and macro definitions can be detected;
[0093] Type groups are split to unify data type definitions.
[0094] In one embodiment, the classification module 803 is further configured to:
[0095] Enter the content after " / / " into the remarks array until the end of the line;
[0096] Enter the content after " / *" into the remarks array until "* / " is read;
[0097] The content after "parameter" is entered into the parameter array until ";" is read, and the array is monitored to see if it contains "[", "]" and ":". The data is then read as the bit width.
[0098] According to Verilog syntax rules, they are classified into IO classes, connection classes, parameter classes, and module classes.
[0099] In one embodiment, the matching and input 804 module is also used for:
[0100] The content identified by classification is categorized, processed, and entered into a dictionary, which includes the module name, parameters, I / O items, wire register items, submodule items, and the connecting wires contained in each module.
[0101] Read the code of each module, record the corresponding dictionary, and find the project parameters of each module by traversing the table.
[0102] For specific limitations on the machine recognition device for RTL code module connection relationships, please refer to the limitations on the machine recognition method for RTL code module connection relationships mentioned above, which will not be repeated here.
[0103] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 9 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a machine identification method for RTL code module connection relationships.
[0104] Those skilled in the art will understand that Figure 9The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0105] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.
[0106] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.
[0107] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.
[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0109] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A machine identification method for RTL code module connection relationships, the method comprising: Machine recognition request to obtain the connection relationship of RTL code modules; The code is preprocessed according to the machine recognition request, and the code specifications are unified through special identifiers; Read the standardized code line by line and categorize it according to Verilog syntax rules; Based on the content identified through classification, perform category matching and input the data into a dictionary; The results of the category matching are classified and then formatted and output. The step of preprocessing the code according to the machine recognition request and unifying the code specifications through special identifiers further includes: By identifying and judging identifiers, comment text and macro definitions can be detected; Type groups are split to unify data type definitions.
2. The method of claim 1, wherein, The step of reading the standardized code line by line and classifying it according to Verilog syntax rules also includes: Enter the content after " / / " into the remarks array until the end of the line; Enter the content after " / *" into the remarks array until "* / " is read; The content after "parameter" is entered into the parameter array until ";" is read, and the array is monitored to see if it contains "[", "]" and ":". The data is then read as the bit width. According to Verilog syntax rules, they are classified into IO classes, connection classes, parameter classes, and module classes.
3. The machine recognition method for RTL code module connection relationships according to claim 2, characterized in that, The step of matching categories based on the identified content and entering the dictionary also includes: The content identified by classification is categorized, processed, and entered into a dictionary, which includes the module name, parameters, I / O items, wire register items, submodule items, and the connecting wires contained in each module. Read the code of each module, record the corresponding dictionary, and find the project parameters of each module by traversing the table.
4. A machine identification device for RTL code module connection relationships, characterized in that, The device includes: The acquisition module is used to acquire machine recognition requests for the connection relationships of RTL code modules; The preprocessing module is used to preprocess the code according to the machine recognition request and to unify the code specifications through special identifiers; A classification module is used to read the standardized code line by line and classify it according to Verilog syntax rules; The matching and input module is used to perform category matching and input into a dictionary based on the content identified by the classification. The result output module is used to classify the results according to the category matching results and output the processing results in a formatted manner. The preprocessing module is further used for: By identifying and judging identifiers, comment text and macro definitions can be detected; Type groups are split to unify data type definitions.
5. The machine identification device for RTL code module connection relationship according to claim 4, characterized in that, The classification module is also used for: Enter the content after " / / " into the remarks array until the end of the line; Enter the content after " / *" into the remarks array until "* / " is read; The content after "parameter" is entered into the parameter array until ";" is read, and the array is monitored to see if it contains "[", "]" and ":". The data is then read as the bit width. According to Verilog syntax rules, they are classified into IO classes, connection classes, parameter classes, and module classes.
6. The machine identification device for RTL code module connection relationship according to claim 5, characterized in that, The matching and input module is also used for: The content identified by classification is categorized, processed, and entered into a dictionary, which includes the module name, parameters, I / O items, wire register items, submodule items, and the connecting wires contained in each module. Read the code of each module, record the corresponding dictionary, and find the project parameters of each module by traversing the table.
7. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 3.
8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 3.