A Parametric Unit Design Method for User-Defined Derivative Layer Input

Abstract

This invention provides a parametric cell design method for user-defined derived layer input, configuring a custom process information table; the custom process information table includes: process layout hierarchy; layout design rules; derived layers defined based on Boolean expressions; defining Pcell parameter variables to store user-input derived layer names and constraint values ​​between derived layers; traversing the process information table to find the Boolean expression corresponding to the input derived layer; based on the Boolean expression, obtaining the information on the hierarchy of the participating process layout and the layout design rules; generating a parametric sub-cell layout instance for each derived layer; and concatenating the generated parametric sub-cell layout instances of the derived layers to generate the Pcell layout.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a parametric cell design method for user-defined derived layer input. Background Technology

[0002] A parameterized cell (Pcell) generally refers to a final layout instance formed by combining various graphical elements based on predefined layout layers and related design rules, by setting various variable device parameters.

[0003] Traditional Pcell development methods can generally only perform geometric changes at a fixed layout level based on device parameter inputs, and cannot parse dynamic layout level inputs. This results in the need to develop custom Pcells one-to-one for different process platforms and different graphic hierarchy definitions of wafer fabs, reducing the applicability of Pcells and increasing Pcell development costs. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a parametric cell design method for user-defined derived layer input, which solves the problem that the prior art performs corresponding fixed layout layer geometric changes for device parameter input, and cannot parse dynamic layout layer input, resulting in the need to develop dedicated Pcells for different process platforms and different graphic layer structure definitions, which increases the Pcell development cost.

[0005] To achieve the above and other related objectives, the present invention provides a parametric unit design method for user-defined derived layer input, comprising at least:

[0006] Step 1: Configure a custom process information table; the custom process information table includes: process layout hierarchy; layout design rules; and derived layers defined based on Boolean expressions;

[0007] Step 2: Define Pcell parameter variables to store the user-inputted derived layer names and constraint values ​​between derived layers;

[0008] Step 3: Traverse the process information table to find the Boolean expression corresponding to the input derived layer;

[0009] Step 4: Based on the Boolean expression, obtain the information on the hierarchical structure of the process layout and the layout design rules;

[0010] Step 5: Generate a parameterized sub-unit layout instance for each of the derived layers;

[0011] Step 6: Combine the generated parametric sub-cell layout instances of the derived layer to generate the Pcell layout.

[0012] Preferably, the process layout hierarchy defined in step one is a virtual layer derived from Boolean logic operations, used to represent the relationship between process layout hierarchies.

[0013] Preferably, the Pcell parameter variable in step two is the CDF parameter.

[0014] Preferably, the constraint values ​​between the derived layers in step two include positional relationships and graphic dimensions.

[0015] Preferably, in step four, the derived layers are parsed in real time using a callback function based on the Boolean expression to obtain information on the hierarchical structure of the process layout and the layout design rules.

[0016] Preferably, in step six, the parameterized sub-cell layout instances of the derived layers are spliced ​​together based on the constraint values ​​between the derived layers input by the user and the obtained layout design rules to generate the Pcell layout.

[0017] As described above, the parameterized unit design method for user-defined derived layer input of the present invention has the following beneficial effects: The method of the present invention uses the derived layer name input by the user to set a callback function to dynamically parse the Boolean expression corresponding to the derived layer, obtains the layout hierarchy information and corresponding design rules in real time according to the parsing result, generates the parameterized unit instance of the corresponding derived layer, and finally splices these parameterized unit instances of the derived layer according to the device structure to form the final layout structure. Attached Figure Description

[0018] Figure 1 The flowchart shown is a parameterized unit design method for user-defined derived layer input in this invention. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0020] Please see Figure 1 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] This invention provides a parametric unit design method for user-defined derived layer input, such as... Figure 1 As shown, Figure 1 The flowchart shown is a parameterized unit design method for user-defined derived layer input in this invention, which includes at least the following steps:

[0022] Step 1: Configure a custom process information table; the custom process information table includes: process layout hierarchy; layout design rules; and derived layers defined based on Boolean expressions;

[0023] In a further embodiment of the present invention, the Pcell parameter variable in step two is the CDF parameter.

[0024] Furthermore, in step one of this embodiment, the layering of the process layout described is a virtual layer derived from Boolean logic operations, used to represent the relationship between the layers of the process layout.

[0025] The hierarchical definition of the process layout described in this invention refers to the layers representing process information that can be used on the layout, for example:

[0026] ACT = AA:drawing

[0027] NWELL = NW:drawing

[0028] GATE = POLY:drawing

[0029] TGO = TGO:drawing

[0030] ...

[0031] ...

[0032] Derived layer definition: Virtual layers derived from process layout layers using Boolean logic operations (AND, OR, etc.) are used to represent the relationships between process layout layers. For example:

[0033] nw25 = NWELL AND TGO

[0034] nw50 = NWELL AND TGO2

[0035] ...

[0036] ...

[0037] Step 2: Define Pcell parameter variables to store the user-inputted derived layer names and constraint values ​​between derived layers;

[0038] Furthermore, in step two of this embodiment, the constraint values ​​between the derived layers include positional relationships and graphic dimensions.

[0039] Step 3: Traverse the process information table to find the Boolean expression corresponding to the input derived layer;

[0040] With the help of process information tables, users can freely define different process platforms and different layout levels without having to develop corresponding Pcells.

[0041] Step 4: Based on the Boolean expression, obtain the information on the hierarchical structure of the process layout and the layout design rules;

[0042] Furthermore, in step four of this embodiment, based on the Boolean expression, the derived layer is parsed in real time using a callback function to obtain information about the layers of the process layout and the layout design rules.

[0043] Step 5: Generate a parameterized sub-unit layout instance for each of the derived layers; that is, generate multiple parameterized sub-unit layout instances for the derived layers.

[0044] Step 6: Combine the generated parametric sub-cell layout instances of the derived layer to generate the Pcell layout.

[0045] In a further step of this invention, in step six of this embodiment, the parameterized sub-cell layout instances of the derived layers are spliced ​​together based on the constraint values ​​between the derived layers input by the user and the obtained layout design rules to generate the Pcell layout.

[0046] In summary, the method of this invention uses the derived layer name input by the user to dynamically parse the Boolean expression corresponding to the derived layer using a callback function. Based on the parsing result, it obtains layout hierarchy information and corresponding design rules in real time, generates parameterized unit instances of the corresponding derived layers, and finally splices these parameterized unit instances of derived layers according to the device structure to form the final layout structure. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for designing parametric units for user-defined derived layer input, characterized in that, At least including: Step 1: Configure a custom process information table; the custom process information table includes: process layout hierarchy; layout design rules; and derived layers defined based on Boolean expressions; Step 2: Define Pcell parameter variables to store the user-inputted derived layer names and constraint values ​​between derived layers; Step 3: Traverse the process information table to find the Boolean expression corresponding to the input derived layer; Step 4: Based on the Boolean expression, the input derived layer is parsed in real time using a callback function to obtain the information on the hierarchical structure of the process layout and the layout design rules. Step 5: Generate a parameterized sub-unit layout instance for each of the derived layers; Step 6: Combine the generated parametric sub-cell layout instances of the derived layer to generate the Pcell layout.

2. The method of claim 1, wherein: The process layout hierarchy defined in step one is a virtual layer derived from Boolean logic operations, used to represent the relationship between process layout hierarchies.

3. The method of claim 1, wherein: The Pcell parameter variable mentioned in step two is the CDF parameter.

4. The method of claim 1, wherein: The constraint values ​​between the derived layers in step two include positional relationships and graphic dimensions.

5. The parametric unit design method for user-defined derived layer input according to claim 1, characterized in that: In step six, based on the constraint values ​​between the derived layers input by the user and the obtained layout design rules, the parameterized sub-cell layout instances of the derived layers are spliced ​​together to generate the Pcell layout.

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