Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a pixel circuit and a light emitting element, wherein the pixel circuit is used for driving the light emitting element to emit light; the pixel circuit comprises a driving module and a light emitting control module; the driving module is used for generating a driving current; the light emitting control module controls the driving current to be transmitted to the light emitting element in response to a light emitting control signal; a display period of the display panel comprises a first display stage and a second display stage; in the first display stage, an invalid pulse length of the light emitting control signal is T1; in the second display stage, an invalid pulse length of the light emitting control signal is T2; and T1>T2. The technical scheme provided by the application can reduce the brightness difference of the display panel in the refreshing frequency switching process and reduce the flicker problem.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In existing technologies, panels or devices containing electroluminescent devices such as organic light-emitting diodes (OLEDs) and miniature diodes can be driven at different driving frequencies. That is, the display panel can display images at different refresh rates. Specifically, when high-speed driving is required, the refresh rate is increased to drive the pixels; when reducing power consumption or low-speed driving is required, the refresh rate is decreased to drive the pixels.

[0003] When the refresh rate updates the data voltage according to the changing refresh rate, viewers may not perceive the change in brightness naturally. For example, when the refresh rate switches from a high frequency to a low frequency, a change in brightness is likely to occur, resulting in noticeable flickering. Summary of the Invention

[0004] This invention provides a display panel and display device to reduce brightness differences and flicker problems that occur during refresh rate switching of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a display panel, including a pixel circuit and a light-emitting element, wherein the pixel circuit is used to drive the light-emitting element to emit light;

[0006] The pixel circuit includes a driving module and a light-emitting control module; the driving module is used to generate a driving current; the light-emitting control module responds to a light-emitting control signal to control the transmission of the driving current to the light-emitting element;

[0007] The display cycle of the display panel includes a first display stage and a second display stage; in the first display stage, the duration of the invalid pulse of the light emission control signal is T1; in the second display stage, the duration of the invalid pulse of the light emission control signal is T2; wherein, T1 > T2.

[0008] Secondly, embodiments of the present invention provide a display device, the display device including a display panel provided in any embodiment of the present invention.

[0009] In this invention, the pixel circuit includes a driving module and a light-emitting control module. The driving module generates a driving current to drive the light-emitting element, and the light-emitting control module controls the driving current to be transmitted from the driving module to the light-emitting element in response to the light-emitting control signal. The display cycle of the display panel includes a first display stage and a second display stage. Both the first and second display stages are provided with invalid pulses of the light-emitting control signal, and the duration of the invalid pulse of the light-emitting control signal in the first display stage is longer than the duration of the invalid pulse in the second display stage. This makes the light-emitting time of the light-emitting element in the second display stage longer than the light-emitting time in the first display stage. Especially when switching from a high refresh rate to a low refresh rate, this embodiment compensates for the problem of unstable node potential caused by large leakage current in the pixel circuit by lengthening the light-emitting time of the light-emitting element in the second display stage, effectively compensates for the brightness decay, and improves the flicker problem perceived by the human eye when switching refresh rates, thereby improving the display effect of the display panel. Attached Figure Description

[0010] Figure 1 This is a timing diagram for display panel drivers in the prior art;

[0011] Figure 2 A timing diagram for a display panel driver is provided in an embodiment of the present invention;

[0012] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0013] Figure 4 A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0014] Figure 5 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0015] Figure 6 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0016] Figure 7 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0017] Figure 8 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0018] Figure 9 for Figure 2 A brightness diagram illustrating the driving timing of the display panel.

[0019] Figure 10 for Figure 8 A brightness diagram illustrating the driving timing of the display panel.

[0020] Figure 11A schematic diagram illustrating the brightness improvement of a display panel provided in an embodiment of the present invention;

[0021] Figure 12 This is a schematic diagram illustrating flicker reduction of a display panel provided in an embodiment of the present invention;

[0022] Figure 13 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0023] Figure 14 This is a brightness diagram of the display panel driving timing provided in an embodiment of the present invention;

[0024] Figure 15 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0025] Figure 16 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0026] Figure 17 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0027] Figure 18 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0028] Figure 19 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0029] Figure 20 A schematic diagram illustrating the brightness effect without reduction compensation in the last display sub-stage of the display cycle provided in an embodiment of the present invention;

[0030] Figure 21 A schematic diagram illustrating the brightness reduction compensation effect in the last display sub-stage of the display cycle provided in an embodiment of the present invention;

[0031] Figure 22 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0032] Figure 23 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0033] Figure 24 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0034] Figure 25 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0035] Figure 26 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0036] Figure 27 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0037] Figure 28 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0038] Figure 29 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0039] Figure 30 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0040] Figure 31 This is another display panel driving timing diagram provided in an embodiment of the present invention;

[0041] Figure 32 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0042] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0043] When switching refresh rates on a display panel, there are typically several adjustment methods. One method involves reducing the frequency from the base frequency (or fundamental frequency), usually in integer multiples. This integer-multiple reduction is called frame interpolation frequency modulation. In frame interpolation, the display cycle of the base frequency includes valid frames. The display frames after reducing the frequency from the base frequency include valid and invalid frames, with the same duration for both. In other words, the driving frequency is reduced by inserting invalid frames between adjacent valid frames. The reduction factor is changed by varying the number of invalid frames inserted. For example, if the base frequency is 120Hz, inserting one invalid frame reduces the frequency to 60Hz, inserting two invalid frames reduces it to 40Hz, and so on. Switching between two driving frequencies can be between the base frequency and a frequency reduced from that base frequency, or between two frequencies reduced from the same base frequency. Another implementation method is to change the frame drive duration of the base frequency display frames to achieve different base frequencies. For example, the first fundamental frequency is 120Hz, and the second fundamental frequency is 90Hz. The frequency after reducing the first fundamental frequency can be 60Hz, 40Hz, or 30Hz, etc., and the frequency after reducing the second fundamental frequency can be 45Hz, 30Hz, etc. The switching between the two driving frequencies can also be a switching between two fundamental frequencies, or a switching between two frequencies after reducing the frequency based on two different fundamental frequencies.

[0044] For example, such as Figure 1 As shown, Figure 1 This is a timing diagram for display panel driving in the prior art. Figure 1 The timing for switching the display panel refresh rate from a base frequency of 120Hz to 40Hz can be configured such that the display cycle includes one valid frame T1' and two invalid frames T2'. However, when switching from a high-frequency refresh rate to a low-frequency refresh rate, during the valid frame T1', the pixel circuit of the display panel normally refreshes the data signal DATA', allowing the light-emitting element to emit light according to the data signal DATA'. The invalid frame T2' is used to maintain the light emission brightness corresponding to the valid frame. Therefore, the invalid frame T2' is equivalent to extending the light emission time based on the valid frame T1'. The increased light emission time leads to increased brightness of the light-emitting element, especially noticeable at low grayscale levels, causing display differences during frequency switching. The inventors discovered during the development of this invention that the following can be executed... Figure 2 The timing sequence shown is as follows: Figure 2This is a timing diagram for driving a display panel according to an embodiment of the present invention. In this embodiment, during the invalid frame T2', brightness is not only maintained, but the anode of the light-emitting element and the source of the driving transistor are also reset via the SP signal. The first initialization voltage VREF1 is used to reset the anode of the light-emitting element, thereby suppressing the increase in brightness of each light-emitting element during the invalid frame T2'. However, due to the characteristics of the thin-film transistors in the pixel circuit, the leakage current is relatively large, and the existence of the invalid frame T2' will cause the data signal to not be rewritten for a long time, resulting in interference to the potential of some nodes in the pixel circuit and brightness changes. Especially when switching from a high refresh rate to a low refresh rate, the brightness change is large, and at low grayscale, it is easy to cause flickering, resulting in a poor user experience.

[0045] To address the above problems, embodiments of the present invention provide a display panel, such as... Figures 3 to 5 As shown, Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 5 This is another display panel driving timing diagram provided in an embodiment of the present invention. The display panel 1 includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 is used to drive the light-emitting element 20 to emit light.

[0046] The pixel circuit 10 includes a driving module 11 and a light-emitting control module 13; the driving module 11 is used to generate a driving current; the light-emitting control module 13 responds to the light-emitting control signal EMIT to control the transmission of the driving current to the light-emitting element 20;

[0047] The display cycle of the display panel includes a first display stage Ti1 and a second display stage Ti2; in the first display stage Ti1, the duration of the invalid pulse of the light emission control signal EMIT is T1; in the second display stage Ti2, the duration of the invalid pulse of the light emission control signal EMIT is T2; wherein, T1 > T2.

[0048] The display panel 1 generally includes sub-pixels arranged in an array. For example, the sub-pixels can be arranged in rows and columns to form a rectangular array, or they can be arranged in other regular or irregular forms; this embodiment does not impose any special limitations on this. Each sub-pixel is provided with a pixel circuit and a light-emitting element 20. The pixel circuit can drive the light-emitting element 20 to emit light. Specifically, the pixel circuit can include a driving module 11 and a light-emitting control module 13. The driving module 11 can be electrically connected to the light-emitting element 20, thereby providing a driving current to the light-emitting element 20. For example, such as... Figure 4As shown, the first end of the driving module 11 can be connected to the first power signal PVDD, and the second end of the driving module 11 can be connected to the anode of the light-emitting element 20. The cathode of the light-emitting element 20 is connected to the second power signal PVEE. Thus, the driving module 11 can form a path between the first power signal PVDD, the light-emitting element 20, and the second power signal PVEE, enabling the driving module 11 to generate a driving current to the light-emitting element 20. The light-emitting control module 13 is used to control the transmission of the driving current to the light-emitting element 20 in response to a light-emitting control signal, so that the first power signal PVDD, the driving module 11, the light-emitting element 20, and the second power signal PVEE form a path. In this embodiment, the light-emitting control module 13 can control the driving module 11 to connect with the light-emitting element 20 in response to a light-emitting control signal EMIT. Optionally, the light-emitting control module 13 may include a first light-emitting control module 131 and a second light-emitting control module 132. The first light-emitting control module 131 can conduct the first power signal PVDD and the driving module 11 in response to the first light-emitting control signal EMIT1, and the second light-emitting control module 132 can conduct the driving module 11 and the light-emitting element 20 in response to the second light-emitting control signal EMIT2. Optionally, if the first light emission control signal EMIT1 and the second light emission control signal EMIT2 are the same signal, then as follows: Figure 4 As shown, the first light-emitting control module 131 and the second light-emitting control module 132 can simultaneously respond to the light-emitting control signal EMIT. It should be noted that each display stage in the first display stage Ti1 and the second display stage Ti2 requires at least one invalid pulse for the light-emitting control signal EMIT to prevent the light-emitting element 20 from continuously emitting light and reduce brightness shift. It should be noted that this embodiment uses P-type transistors in the light-emitting control module 13 controlled by the light-emitting control signal EMIT as an example. When all transistors in the light-emitting control module 13 are P-type, the invalid pulse of the light-emitting control signal EMIT is at a high level, such as... Figure 5 As shown, when the light emission control module 13 contains an N-type transistor, the invalid pulse of the light emission control signal EMIT is at a low level. In this embodiment, there is no special limitation on whether the invalid pulse of the light emission control signal EMIT is at a high level or a low level.

[0049] A display cycle of the display panel is the time period between the start of the current screen refresh and the start of the next screen refresh, that is, the time period between the start of the current valid frame and the start of the next valid frame. The display cycle may include a first display stage Ti1 and a second display stage Ti2. When using frame interpolation to change the refresh rate, in this embodiment, the first display stage Ti1 can be a valid frame, and the second display stage Ti2 can be an invalid frame. In a valid frame, the invalid pulse duration of the light emission control signal EMIT is T1, and in an invalid frame, the invalid pulse duration of the light emission control signal EMIT is T2. As the name suggests, the invalid pulse is the signal segment when the light emission control signal EMIT controls the light-emitting element not to emit light. In a frame, whether it is a valid frame or an invalid frame, the smaller the invalid pulse duration of the light emission control signal EMIT, the larger the valid pulse duration, and the longer the light emission duration of the light-emitting element, effectively delaying the decay of the brightness of the light-emitting element and avoiding the flickering problem of low grayscale. Specifically, in this embodiment, T1 > T2, which means that the light emission time of the light-emitting element in the first display stage Ti1 is less than its light emission time in the second display stage Ti2. Figure 5 As shown, Figure 5 In the second display stage Ti2, the invalid pulse in the dashed section has the same duration as the invalid pulse in the first display stage Ti1, both being T1. It can be clearly seen that the actual duration T2 of the invalid pulse in the second display stage Ti2 is less than T1. Therefore, the light emission duration of the second display stage Ti2 is greater than that of the first display stage Ti1. This helps to slow down the brightness decay rate of the light-emitting element, improve the problem of large brightness differences during refresh frequency switching, and effectively avoid screen flickering on the display panel.

[0050] In this embodiment of the invention, the pixel circuit includes a driving module and a light-emitting control module. The driving module generates a driving current to drive the light-emitting element, and the light-emitting control module controls the driving current to be transmitted from the driving module to the light-emitting element in response to the light-emitting control signal. The display cycle of the display panel includes a first display stage and a second display stage. Both the first and second display stages are provided with invalid pulses of the light-emitting control signal, and the duration of the invalid pulse of the light-emitting control signal in the first display stage is longer than the duration of the invalid pulse in the second display stage. This makes the light-emitting time of the light-emitting element in the second display stage longer than the light-emitting time in the first display stage. Especially when switching from a high refresh rate to a low refresh rate, this embodiment compensates for the problem of unstable node potential caused by large leakage current in the pixel circuit by lengthening the light-emitting time of the light-emitting element in the second display stage, effectively compensates for the brightness decay, and improves the flicker problem perceived by the human eye when switching refresh rates, thereby improving the display effect of the display panel.

[0051] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0052] It is important to note that Figure 5 The effective pulse duration of the emission control signal EMIT is increased by adjusting the duration from the end of the invalid pulse of the EMIT signal, thereby compensating for the shorter effective pulse duration. Of course, as... Figure 6 As shown, Figure 6 In another display panel driving timing diagram provided in this embodiment of the invention, the effective pulse duration of the light emission control signal EMIT can also be increased by adjusting the start time of the invalid pulse of the light emission control signal EMIT, thereby compensating for the effective pulse duration. This embodiment does not impose any special limitation on the compensation method for the effective pulse of the light emission control signal EMIT.

[0053] Optionally, the display cycle of the display panel includes a first display stage Ti1 and multiple second display stages Ti2; the invalid pulse duration of the light emission control signal EMIT in each second display stage Ti2 is the same. Each first display stage Ti1 or second display stage Ti2 includes an invalid pulse of the light emission control signal EMIT, such as... Figure 5 As shown, in this embodiment, the invalid pulse duration T2 of the light emission control signal EMIT in each second display stage Ti2 can be the same, so the control timing is simple, and T1>T2. The light emission time of the light-emitting element in the second display stage Ti2 is longer than that in the first display stage Ti1. This helps to delay the display brightness decay caused by pixel circuit leakage, improve the problem of large brightness difference during refresh frequency switching, and effectively avoid screen flickering on the display panel.

[0054] Figure 7 Another display panel driving timing diagram provided in this embodiment of the invention includes, optionally, a display cycle of the display panel comprising a first display stage Ti1 and multiple second display stages Ti2; at least two of the second display stages Ti2 have different invalid pulse durations for their light emission control signals EMIT. When multiple second display stages Ti2 exist, the invalid pulse duration T2 of the light emission control signals EMIT for each second display stage Ti2 can be different, but it is necessary to maintain T1 > T2. That is, the light emission time of the light-emitting element in the second display stage Ti2 is greater than its light emission time in the first display stage Ti1. This can also alleviate the attenuation of display brightness, avoid the problem of large brightness changes during frequency switching, and improve the user's viewing experience.

[0055] Continue to refer to Figure 7Optionally, the display cycle of the display panel may include a first display stage Ti1 and N second display stages Ti2; N is an integer greater than or equal to 2; the first second display stage Ti2 is adjacent to the first display stage Ti1; in the i-th second display stage Ti2, the invalid pulse duration of the light emission control signal is T21; in the (i+1)-th second display stage Ti2, the invalid pulse duration of the light emission control signal is T22; where T21 > T22; 1 ≤ i ≤ N-1; i is an integer. When there are multiple second display stages Ti2, the invalid pulse duration T2 of the light emission control signal EMIT of each second display stage Ti2 may be different. In this embodiment, N second display stages Ti2 can be set, where N is an integer with a minimum value of 2. The first second display stage Ti2 is adjacent to the first display stage Ti1, and the Nth second display stage Ti2 is farthest from the first display stage Ti1. In N second display stages Ti2, the invalid pulse duration of the light emission control signal EMIT in the i-th second display stage Ti2 is set to T21, and the invalid pulse duration of the light emission control signal EMIT in the (i+1)-th second display stage Ti2 is set to T22. Given that T21 > T22, this means that the light emission duration of the light-emitting element in the i-th second display stage Ti2 is less than that in the (i+1)-th second display stage Ti2. In other words, in the N second display stages Ti2, the light emission duration of the light-emitting element gradually increases. This is because as the holding time increases, the brightness decay of the light-emitting element gradually strengthens. Therefore, as the number of second display stages Ti2 increases, the brightness decay gradually intensifies. In this embodiment, combined with the brightness decay law, different light emission times are compensated (increased) for different second display stages Ti2. The brightness change problem and flicker problem during frequency switching can be significantly improved, the brightness change is more stable, and the display panel's screen display effect is further improved.

[0056] Based on the above embodiments, this embodiment can verify the brightness improvement effect of the light-emitting element. Before verification, it is necessary to clarify the concept of display sub-stages. When using frame interpolation, the refresh rate can be reduced by integer multiples. For example, when the base frequency is 120Hz, it can only be switched to 60Hz, 40Hz, and 30Hz, etc. Each valid frame and invalid frame can be divided into multiple display sub-stages (pulses), such as... Figure 8 As shown, Figure 8This is another display panel driving timing diagram provided in an embodiment of the present invention. Each display sub-stage has the same duration, and each display sub-stage can be configured with an invalid pulse for the emission control signal EMIT. Optionally, assuming a refresh rate of 40Hz, including one valid frame and two invalid frames, the valid frame serves as the first display stage Ti1, and the invalid frames serve as the second display stage Ti2. Each valid frame and each invalid frame can include three display sub-stages. For example, the width of the invalid pulse for the emission control signal EMIT in each display sub-stage within each frame is the same. Specifically, it can be seen that the first display... In stage Ti1, the duration of the invalid pulse of the light emission control signal EMIT is T1. If it is evenly divided into three invalid pulses of the light emission control signal EMIT, the width of each invalid pulse is Ht1. In the second display stage Ti2, the duration of the invalid pulse of each light emission control signal EMIT is T2. If it is evenly divided into three invalid pulses of the light emission control signal EMIT, the width of each invalid pulse is Ht2. It is possible to control each Ht1 > Ht2, so that T1 > T2, thereby increasing the light emission time of the second display stage Ti2, compensating for brightness changes and flickering problems during frequency switching, and further improving the display effect of the display panel. Of course, the width of the invalid pulses of the three light emission control signals EMIT can also be different in the first display stage Ti1 and the second display stage Ti2. This embodiment does not impose any special limitation on this.

[0057] Figure 9 for Figure 2 A brightness diagram illustrating the driving timing of the display panel. Figure 10 for Figure 8 This is a brightness diagram illustrating the driving timing of the display panel. Assuming a current refresh rate of 40Hz, it includes one valid frame and two invalid frames. Each frame comprises three display sub-phases (pulses). This embodiment uses a brightness of 500 nits and a G255 grayscale level for brightness simulation experiments. It should be noted that when using frame interpolation to achieve frequency switching, the first display phase Ti1 is the valid frame, and the second display phase Ti2 is the invalid frame. Figure 9 In the display panel, the invalid pulses of the EMIT light emission control signal for invalid frames and valid frames are equal, meaning that the light emission duration of the light-emitting element in the invalid frame is not compensated. The horizontal axis represents time, and the vertical axis represents the ratio of the current brightness Lv to the maximum brightness Lv(max). The maximum brightness Lv(max) is the display brightness, and the current brightness Lv is the grayscale brightness at the current grayscale level. It should be noted that the brightness mentioned in this embodiment refers to grayscale brightness; if it refers to display brightness, it will be specifically marked or indicated by the maximum brightness Lv(max). Three Lv pulse signals constitute one frame, and nine Lv pulse signals constitute one display cycle (including one valid frame and two invalid frames). Figure 9It can be concluded that the brightness difference between adjacent frames is significant, resulting in the brightness variation perceived by the human eye as shown by the curve Lv(jeita). This indicates that the human eye can clearly perceive fluctuations in brightness. (Reference) Figure 10 , Figure 10 The brightness of the second display stage Ti2 (invalid frame) is specifically compensated by increasing the emission time of Ti2 and decreasing the invalid pulse duration of the emission control signal EMIT of Ti2. Figure 10 The results show that the brightness curve Lv(jeita) perceived by the human eye is relatively flat, with small fluctuation amplitude and a small range of brightness change, which avoids the human eye perceiving flicker and improves the display effect of the display panel.

[0058] To further elaborate on the issues of brightness differences and flicker, such as Figure 11 and Figure 12 As shown, Figure 11 This is a schematic diagram illustrating the brightness improvement of a display panel provided in an embodiment of the present invention. Figure 12 This is a schematic diagram illustrating flicker reduction in a display panel provided in an embodiment of the present invention. Figure 11 As shown, the horizontal axis represents frequency, and the vertical axis represents the ratio of luminance Lv to luminance Lv_120Hz at the reference frequency of 120Hz. The dashed line represents... Figure 2 The brightness variation curves of the display panel driving timing shown are illustrated. The solid line represents the brightness variation curve of the display panel driving timing in this embodiment. It is clearly visible that the scheme after compensating for the emission time of Ti2 in the second display stage can effectively reduce brightness variation. For the uncompensated scheme, the brightness variation range is large and easily perceived. The compensated scheme maintains a stable brightness, effectively improving display efficiency. (Reference) Figure 12 The horizontal axis represents frequency, and the vertical axis represents flicker intensity. The dashed line represents... Figure 2 The flickering curve of the display panel driving timing shown is shown in the figure. The solid line is the flickering curve of the display panel driving timing in this embodiment. It can be seen that the scheme after compensating for the light emission time of Ti2 in the second display stage effectively improves the flickering problem, and the flickering degree is closer to 0dB, which effectively alleviates the flickering problem and improves the display effect of the display panel.

[0059] Optionally, both the first display stage Ti1 and the second display stage Ti2 include c display sub-stages; each display sub-stage is provided with an invalid pulse of the light emission control signal; c is an integer greater than or equal to 1.

[0060] When both the first display stage Ti1 and the second display stage Ti2 include c display sub-stages, since the duration of each display sub-stage is fixed, the durations of the first display stage Ti1 and the second display stage Ti2 are the same. Therefore, the first display stage Ti1 is a valid frame, and the second display stage Ti2 is an invalid frame. The above embodiments illustrate this by using the example of the first display stage Ti1 being a valid frame and the second display stage Ti2 being an invalid frame. Figure 8 As shown, each display sub-stage is provided with an invalid pulse for the light emission control signal EMIT. In each display stage (first display stage Ti1 or second display stage Ti2), the width of the invalid pulse for the light emission control signal EMIT in each display sub-stage can be the same or different; this embodiment does not impose any special limitations on this. It is worth noting that each display stage can include multiple display sub-stages, in which case each display stage can be provided with multiple invalid pulses for the light emission control signal; alternatively, each display stage can include only one display sub-stage, in which case each display stage can be provided with only one invalid pulse for the light emission control signal.

[0061] Specifically, such as Figure 8 As shown, optionally, c is an integer greater than or equal to 2. In the same first display stage Ti1 or second display stage Ti2, the invalid pulse width of the light emission control signal EMIT of each display sub-stage pulse is the same. Optional, such as Figure 13 As shown, Figure 13 In another display panel driving timing diagram provided by an embodiment of the present invention, the difference in invalid pulse width of the light emission control signal in two adjacent second display stages Ti2 is E = H21 - H22; where H21 and H22 are the invalid pulse widths of the light emission control signal in two adjacent second display stages Ti2, respectively; 2L≤E≤8L; L is the line time at the current driving frequency f of the pixel circuit; L = 1 / (f*b); b is the total number of rows of the display panel.

[0062] It can be seen that in two adjacent second display stages Ti2, if the invalid pulse duration of the light emission control signal of one second display stage Ti2 is T21, then the invalid pulse width of the light emission control signal EMIT of each pulse is H21 = T21 / c; similarly, if the invalid pulse duration of the light emission control signal of the other second display stage Ti2 is T22, then the invalid pulse width of the light emission control signal EMIT of each pulse is H22 = T22 / c. The difference E between the two can range from 2 to 8 line times, that is, 2L≤E≤8L. ​​The line time is the time required for the scanning circuit to scan one line of sub-pixels. It should be noted that the time per frame is 1 / f. If the display panel includes b lines of sub-pixels, the time per line is L = 1 / (f*b). When there are multiple invalid frames, there is a light emission time difference of 2 to 8 line times between the display sub-stage pulses of adjacent frames. By gradually increasing the light emission time of the light emission element of the invalid frame according to this rule, the change in display brightness during frequency switching and the flickering problem at low gray levels can be effectively improved, thus effectively enhancing the display effect. Optionally, for low-frequency switching brightness and flicker control, in this embodiment, E can refer to an integer multiple of the minimum period that causes the output of the light emission control signal EMIT to change. For example, if a shift register circuit of the gate scan circuit drives one row of sub-pixels, its minimum period is 2 row times. If a shift register circuit drives two rows of sub-pixels, its minimum period is 4 row times. Therefore, the value range of E can be 4 to 8 row times.

[0063] Optionally, the effective pulse width of the light emission control signal for each display sub-stage of the first second display stage Ti2 is increased relative to the light emission control signal for each display sub-stage of the first display stage. a% is the brightness decrease value when the driving frequency of the pixel circuit drops from the reference frequency to the current driving frequency f; the effective pulse duration of the light emission control signal of each display sub-stage of the p-th second display stage Ti2 relative to the light emission control signal of each display sub-stage of the first display stage. 2≤p≤N; p is an integer.

[0064] When the first display stage Ti1 is a valid frame and the second display stage Ti2 is an invalid frame, there can be a light emission time difference of 2 to 8 line times between the display sub-stage pulses of two adjacent invalid frames. Based on this, this embodiment precisely controls the width of the effective pulse of the light emission control signal of the first invalid frame closest to the valid frame, thereby accurately compensating for the light emission brightness according to the brightness decay law, effectively maintaining the stability of the light emission brightness, and improving the display effect. Specifically, it can be seen that both the second display stage Ti2 and the first display stage Ti1 include c display sub-stages, and each display sub-stage includes a valid pulse and an invalid pulse of the light emission control signal EMIT. In this embodiment, the effective pulse width of the light emission control signal of each display sub-stage of the first second display stage Ti2 can be widened relative to each display sub-stage of the first display stage Ti1. Where a% represents the brightness decrease when the pixel circuit's driving frequency drops from the reference frequency to the current driving frequency f. In this embodiment, the brightness of the entire display cycle is evenly distributed to each display sub-stage for display. That is, the compensation principle in this embodiment is to compensate for all brightness decreases during frequency switching to maximize the compensation for brightness attenuation caused by leakage current in the pixel circuit, reduce brightness differences, and effectively alleviate flickering problems. Based on this, the effective pulse width of the light emission control signal in each display sub-stage of the second display stage Ti2 is wider than that in each display sub-stage of the first display stage Ti1. The effective pulse width of the light emission control signal in each display sub-stage of the third second display stage Ti2 is wider than that in each display sub-stage of the first display stage Ti1. Similarly, there is a light emission time difference of 2 to 8 line times between the display sub-stage pulses of adjacent frames. By gradually increasing the light emission time of the light-emitting elements of invalid frames according to this rule, the change in display brightness during frequency switching can be effectively improved.

[0065] It should be noted that for display panels that have already undergone luminance compensation in the second display stage Ti2, the value of a% can still be obtained from the compensated display panel to set the effective pulse width of the luminance control signal for each of the above display sub-stages. Figure 14 This is a brightness diagram of the display panel driving timing provided in an embodiment of the present invention. The a% method process is as follows: Figure 14Taking a 40Hz waveform as an example, the time interval between the two solid lines represents a complete 40Hz frame (valid or invalid frame), divided into three display sub-stages ①②③. Repeating ① for two cycles represents three frames of 120Hz waveform. Integrating the three 120Hz waveforms over time yields the average brightness at 120Hz. Comparing this with the average brightness at 40Hz provides the brightness compensation value, and thus the value of a%. Furthermore, the effective pulse of the light emission control signal EMIT can be easily verified by comparing the emission time of each display sub-stage pulse, thus providing simple evidence for the scheme in this embodiment.

[0066] Figure 15 In another display panel driving timing diagram provided by an embodiment of the present invention, optionally, within the same second display stage Ti2, the invalid pulse widths of the light emission control signals in the two display sub-stages are different. In the same second display stage Ti2, this embodiment can set the invalid pulse width H21 of the light emission control signal EMIT in the two display sub-stages to be different, so as to further refine the specific setting of the invalid pulse width H21 of the light emission control signal EMIT according to the brightness attenuation law of the pixel circuit, thereby further improving the problems of large brightness variations and flickering. Optionally, continue to refer to... Figure 15 In the same second display stage Ti2, the invalid pulse width of the light emission control signal of the m-th display sub-stage is Hm, and the invalid pulse width of the light emission control signal of the (m+1)-th display sub-stage is Hm+1; where Hm > Hm+1; 1 ≤ m ≤ c-1; and m is an integer. Similarly, the display brightness of the light-emitting element will decrease as the time of the invalid frame (second display stage Ti2) increases. In this embodiment, according to the brightness decay law, when the same second display stage Ti2 includes multiple display sub-stages, the invalid pulse width Hm of the previous display sub-stage is greater than the invalid pulse width Hm+1 of the next display sub-stage. Therefore, in the same second display stage Ti2, the effective pulse width of the light emission control signal EMIT of the display sub-stage gradually increases to further enhance the light emission compensation according to the brightness decay law of the pixel circuit, thereby further improving the problem of large brightness changes and flickering, and improving the display effect.

[0067] In this embodiment, the first display stage Ti1 is a valid frame, and at least part of the second display stage Ti2 may not be invalid frames. Specifically, when switching between the same base frequency and its down-clocked frequency, frame interpolation may not be used; this embodiment uses pulse interpolation. When frame interpolation is used to change the refresh rate of the display panel, the pulse duration of all display sub-stages is the same. Therefore, when the number of inserted pulses is an integer multiple of the number of pulses c in the valid frame, the second display stage Ti2 is entirely invalid frames. When the number of inserted pulses is not an integer multiple of the number of pulses c in the valid frame, the number of pulses in the second display stage Ti2 will inevitably differ from the number of pulses in the valid frame. This embodiment uses pulse interpolation, which enables frequency switching between 120Hz and 60Hz, such as a 90Hz frequency adjustment, thus improving the refresh rate switching range.

[0068] Specifically, such as Figure 16 As shown, Figure 16 In another display panel driving timing diagram provided by an embodiment of the present invention, optionally, the first display stage Ti1 and / or part of the second display stage Ti2 may include c1 display sub-stages; each display sub-stage is provided with an invalid pulse of the light emission control signal; c1 is an integer greater than or equal to 2; there exists a second display stage Ti2 including c2 display sub-stages; c2 is an integer greater than or equal to 1; c2 < c1. In this embodiment, the number of pulses of the effective frame can be c1, for example, 3. When the inserted pulse is not an integer multiple of 3, for example, 5, then there exists a second display stage Ti2 including c1 display sub-stage pulses, but there is also a second display stage Ti2 including (5-c1) display sub-stage pulses, that is, including c2 display sub-stages. In this example, the value of c2 is 2. In this embodiment, the refresh rate is between 120Hz and 60Hz, then this embodiment can effectively improve the refresh rate adjustment range of the display panel, improve the brightness adjustment accuracy, further alleviate the flicker problem, and improve the screen display effect.

[0069] For example, such as Figure 17 As shown, Figure 17 Another display panel driving timing diagram provided in this embodiment of the invention addresses the issue of frequency switching involving multiple pulses instead of a single frame, such as switching from 120Hz to 90Hz. This requires adding half the number of pulses c per frame. For example, if the effective frame includes 6 pulses, the added second display stage Ti2 includes 3 pulses. In this case, compensation for the multiple inserted pulses using the EMIT light emission control signal is also necessary. The calculation method is as follows:

[0070] Assuming a brightness decrease of approximately a% when switching from 120Hz to 90Hz, a total of b lines, and cpulse as the effective EM frame, the compensation formula for the Emittance Control Signal (EMIT) is as follows:

[0071] The effective pulse width of the light emission control signal of the first pulse in the second display stage Ti2 is increased by H1 = b*a% / c relative to each display sub-stage of the first display stage Ti1;

[0072] The effective pulse width of the light emission control signal of the second pulse in the second display stage Ti2 is increased by H2 = b*a% / c + (2~8)L relative to each display sub-stage of the first display stage Ti1;

[0073] The effective pulse width of the light emission control signal of the third pulse in the second display stage Ti2 is increased relative to each display sub-stage of the first display stage Ti1 by = b*a% / c+(4~16)L.

[0074] The above-mentioned compensation method for the light emission control signal effectively improves the refresh rate adjustment range of the display panel, and compensates the light emission control signal for each inserted pulse individually, thereby improving the brightness adjustment accuracy and further alleviating the flicker problem and improving the display effect.

[0075] Optionally, the first display stage Ti1 includes multiple display sub-stages; the second display stage Ti2 includes at least one display sub-stage; each display sub-stage is provided with an invalid pulse of the light emission control signal; in the Nth second display stage Ti2, the first display sub-stage is adjacent to the (N-1)th second display stage Ti2; the invalid pulse duration of the light emission control signal of the last display sub-stage is Ta, and the invalid pulse duration of the light emission control signal of the display sub-stage adjacent to the last display sub-stage is Tb, where Ta > Tb.

[0076] Based on the above embodiments, regardless of whether the refresh rate switching method is frame interpolation or pulse interpolation, the first display stage Ti1 can include multiple display sub-stages, and the second display stage Ti2 can include at least one display sub-stage. This embodiment can include N second display stages Ti2, with the first second display stage Ti2 adjacent to the first display stage Ti1, and the Nth second display stage Ti2 adjacent to the (N-1)th second display stage Ti2. The display sub-stages in the first N-1 second display stages Ti2 can have the same data as the display sub-stages in the first display stage Ti1. For example... Figure 18 As shown, Figure 18In another display panel driving timing diagram provided by an embodiment of the present invention, when the Nth second display stage Ti2 includes multiple display sub-stages, the first display sub-stage is adjacent to the (N-1)th second display stage Ti2. The invalid pulse duration of the light emission control signal of the last display sub-stage is Ta, and the invalid pulse duration of the light emission control signal of the display sub-stage adjacent to the last display sub-stage is Tb, and Ta is limited to be greater than Tb. In this embodiment, when the second display stage Ti2 includes multiple display sub-stages, the effective pulse duration of the light emission control signal EMIT of the last display sub-stage of the last second display stage Ti2 in one display cycle is reduced, thereby reducing the amount of light emission compensation. This can mitigate the sudden change in display panel brightness during frequency switching and optimize the display effect.

[0077] like Figure 19 As shown, Figure 19 This is another display panel driving timing diagram provided in an embodiment of the present invention. When the Nth second display stage Ti2 includes a display sub-stage, the first display sub-stage and the last display sub-stage are the same display sub-stage. In this case, the invalid pulse duration of the light emission control signal EMIT in the Nth second display stage Ti2 is Ta, and the invalid pulse duration of the light emission control signal EMIT in the last display sub-stage of the (N-1)th second display stage Ti2 is Tb. Similarly, by reducing the effective pulse duration of the light emission control signal EMIT in the last display sub-stage of the last second display stage Ti2 of a display cycle, the sudden change in display panel brightness during frequency switching can be mitigated. Optionally, the effective pulse duration of the light emission control signal EMIT in the last display sub-stage of the last second display stage Ti2 of a display cycle can be reduced to be the same as the effective pulse duration of the light emission control signal EMIT in the first display stage Ti1.

[0078] Specifically, such as Figure 20 and Figure 21 As shown, Figure 20 This is a schematic diagram illustrating the brightness effect without reduction compensation in the last display sub-stage of the display cycle provided in an embodiment of the present invention. Figure 21 This is a schematic diagram illustrating the brightness reduction effect of the last display sub-stage in the display cycle provided by an embodiment of the present invention. It assumes a brightness simulation of 500 nits L64. Figure 20 As shown, the horizontal axis represents time, and the vertical axis represents the brightness value. Figure 20The dense pulse pattern (originally - raw) is a schematic diagram of the effective pulse duration of the light emission control signal EMIT in the last display sub-stage before reducing one display cycle (including the sequentially set first display stage Ti1 and multiple second display stages Ti2). The waveform diagram (originally - jeita) is the real-time average brightness of multiple pixels, which can represent the visual brightness effect. It can be seen that at the instant of frequency switching, that is, at the time point of 0.1 seconds in the figure, the fluctuation range of the waveform diagram can reach 5-30 nits. Figure 21 As shown, Figure 21 The dense pulse pattern (optimized-raw) is a schematic diagram illustrating the reduction of the effective pulse duration of the light emission control signal EMIT in the last display sub-stage of a display cycle (including the sequentially set first display stage Ti1 and multiple second display stages Ti2). The waveform (original-jeita) represents the real-time average brightness of multiple pixels. It can be seen that at the instant of frequency switching, i.e., at the 2-second point in the diagram, the waveform fluctuation range can reach 15-30 nits, and the brightness difference before and after the switching is small; at least the effect is not worse than... Figure 20 The results are poor. Therefore, we can see that when we control the last display sub-stage of a display cycle separately and reduce the compensation value of the effective pulse of the EMIT light emission control signal, we can further reduce the brightness jitter amplitude during frequency switching, improve the flicker problem, and because the last display sub-stage accounts for a small proportion of the entire display cycle, it will not worsen the brightness difference before and after frequency switching, thus further improving the display effect.

[0079] Figure 22 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 23 This is another timing diagram for driving a display panel according to an embodiment of the present invention. Optionally, the display panel may further include: a first initialization module 12; the first initialization module 12 is used to provide a first initialization voltage REF1 to a first node N1, the first node N1 being connected to a light-emitting element; the control terminal of the first initialization module 12 transmits the first initialization voltage REF1 to the first node N1 in response to a first scan signal SP; in the first display stage Ti1 and the second display stage Ti2, the effective pulse time period of the first scan control signal SP is located within the invalid pulse time period of the light-emitting control signal EMIT.

[0080] The first initialization module 12 can influence the transmission of the first initialization voltage VREF1 to the first node N1 by the first scan signal SP. In this embodiment, the first node N1 is connected to one of the anode and cathode of the light-emitting element 20, thereby resetting the light-emitting element 20. When the first node N1 is connected to the anode of the light-emitting element 20, the first initialization voltage VREF1 is negative; when the first node N1 is connected to the cathode of the light-emitting element 20, the first initialization voltage VREF1 is positive. This embodiment illustrates the connection of the first node N1 to the anode of the light-emitting element 20 as an example. It should be noted that each display stage in the first display stage Ti1 and the second display stage Ti2 requires at least one invalid pulse of the first scan control signal SP to reset the light-emitting element (first node N1) in each display stage, effectively suppressing the continuous increase of the brightness of the light-emitting element in the second display stage Ti2 and effectively maintaining the stability of the display brightness. Figure 23 As shown, whether it is the first display stage Ti1 or the second display stage Ti2, the effective pulse time period of the first scan control signal SP is within the invalid pulse time period of the light emission control signal EMIT. That is, the reset of the light emission element 20 should be during the time period when the light emission element 20 does not emit light.

[0081] Figure 24 In another display panel driving timing diagram provided by an embodiment of the present invention, optionally, in the first display stage Ti1 and the second display stage Ti2, a set time delay is set between the end time of the effective pulse of the first scan control signal SP and the end time of the invalid pulse of the corresponding light emission control signal EMIT. To clearly illustrate the timing relationship between the first scan control signal SP and the light emission control signal EMIT, in this embodiment, only one invalid pulse of the light emission control signal EMIT is shown in each display stage. In reality, each display stage may include at least one invalid pulse of the light emission control signal EMIT, but each display stage has one invalid pulse of the light emission control signal EMIT that covers the effective pulse time period of the first scan control signal SP. As can be seen from the above embodiment, the time period of the effective pulse of the first scan control signal SP is located within the time period of the invalid pulse of the light emission control signal EMIT. In this embodiment, a set time delay s3 is set between the end time of the effective pulse of the first scan control signal SP and the end time of the invalid pulse of the corresponding light emission control signal EMIT. The light emission element can only emit light normally after a period of time following its reset, enhancing the reset effect of the light emission element, effectively suppressing the increase in brightness of the light emission element at low gray levels, and avoiding the problem of large changes in display panel brightness during frequency switching.

[0082] Continue to refer to Figure 24Optionally, in the two second display stages Ti2, the effective pulse duration s4 of the first scan control signal SP has a different proportion in the invalid pulse of the corresponding light emission control signal EMIT. The brightness of the display panel increases with the increase of the light emission time. Since the second display stage Ti2 is located after the first display stage Ti1, the brightness of the second display stage Ti2 is prone to increase. In this embodiment, the effective pulse duration of the second display stage Ti2 can be controlled independently. For example, by increasing the effective pulse duration of the first scan control signal SP in part of the second display stage Ti2, the reset time of the light-emitting element can be extended, thereby effectively suppressing the brightness increase of the light-emitting element and maintaining the brightness of the display panel within a set range. For example, as shown... Figure 24 As shown, there are two second display stages Ti2, and the proportion of the effective pulse duration s4 of the first scan control signal SP in the invalid pulse of the corresponding light emission control signal EMIT is different. Optionally, when there are multiple second display stages Ti2, the proportion of the effective pulse duration s4 of the first scan control signal SP in the invalid pulse of the corresponding light emission control signal EMIT can be gradually increased, thereby gradually enhancing the brightness suppression effect on the light-emitting element and effectively avoiding excessive brightness difference or flickering problems when switching frequencies.

[0083] Continue to refer to Figure 24 Optionally, the duration of the set delay s3 in the first display stage Ti1 is shorter than the duration of the set delay s3 in the second display stage Ti2. The brightness of the display panel increases with the duration of light emission, and since the second display stage Ti2 is located after the first display stage Ti1, its brightness is prone to increase. In this embodiment, the set delay between the reset time and the light emission time of the light-emitting element in the second display stage Ti2 can be controlled to be different from that in the first display stage Ti1. Specifically, the duration of the set delay s3 in the second display stage Ti2 is controlled to be longer than that in the first display stage Ti1, thereby enhancing the anode reset effect of the light-emitting element in the second display stage Ti2, effectively preventing an increase in display brightness, and maintaining the stability of the brightness of the light-emitting element at low grayscale levels.

[0084] Figure 25 In another display panel driving timing diagram provided in this embodiment of the invention, optionally, when the driving frequency of the pixel circuit is the first frequency f1, the invalid pulse duration of the light emission control signal EMIT in the second display stage Ti2 is T23; when the driving frequency of the pixel circuit is the second frequency f2, the invalid pulse duration of the light emission control signal in the second display stage Ti2 is T24; wherein, f1 > f2; T23 > T24.

[0085] When using frame interpolation or pulse interpolation to change the frequency, a lower frequency allows the light-emitting element to maintain the current data signal (Data) brightness for a longer period. When the refresh rate of the display panel is set to the first frequency f1, the total duration of the effective pulses controlling the light-emitting control signal (EMIT) in the second display stage Ti2 is T23. When the refresh rate of the display panel is set to the second frequency f2, the total duration of the effective pulses controlling the light-emitting control signal (EMIT) in the second display stage Ti2 is T24. Figure 25 The illustration only considers the case where each display stage includes a display sub-stage pulse. If f1 > f2, it means that the brightness of the light-emitting element is maintained for a longer time at the second frequency f2. At this time, it is easier for the display brightness to increase too much. In this embodiment, T23 > T24 can be controlled to effectively balance the display brightness of the light-emitting element at different refresh frequencies. This makes it less likely for the human eye to perceive changes in display brightness and flickering when the display panel switches frequencies, for example, when the first frequency f1 switches to the second frequency f2.

[0086] Continue to refer to Figure 22 and Figure 24 Optionally, the display panel may also include: a data writing module 14 and a threshold compensation module 15; the data writing module 14 is used to provide data signals to the first terminal of the drive module 11; the threshold compensation module 15 is connected between the control terminal of the drive module 11 and the second terminal of the drive module; the data signal in the first display stage Ti1 is D1; ​​the data signal in the second display stage Ti2 is D2; wherein, |D1| < |D2|.

[0087] In this embodiment, the pixel circuit further includes a data writing module 14 and a threshold compensation module 15. In the first display stage Ti1, the data writing module 14 first writes the data signal to the first terminal of the driving module 11, and the threshold compensation module 15 writes the data signal to the control terminal of the driving module 11. In the second display stage Ti2, the data writing module 14 only writes the data signal to the first terminal of the driving module 11, while controlling the threshold compensation module 15 to turn off, thereby controlling the data signal to reset the first terminal of the driving module 11, i.e., the second node N2. If the data signal in the first display stage Ti1 is D1 and the data signal in the second display stage Ti2 is D2, this embodiment controls |D1| < |D2| to reduce the difference between the bias state of the driving module 11 in the second display stage Ti2 and the bias state of the driving module 11 in the first display stage Ti1, thereby reducing the display brightness at low refresh rates, especially the display brightness at low grayscale levels. In the first display stage Ti1, data signal D1 is a variable voltage signal depending on the displayed image, and data signal D2 can be a constant voltage. Therefore, in the second display stage Ti2, the driver chip provides a constant voltage to the data writing module 14, thereby simplifying the driver chip's operation. Of course, in this embodiment, data signal D2 can also be a variable voltage signal, as long as it is greater than data signal D1.

[0088] Figure 26 Another display panel driving timing diagram provided in this embodiment of the invention, optionally, the display cycle of the display panel includes a first display stage Ti1 and N second display stages Ti2; the first second display stage Ti2 is adjacent to the first display stage Ti1, in the q-th second display stage Ti2, the data signal is D21; in the (q+1)-th second display stage Ti2, the data signal is D22; where |D21|<|D22|; 1≤q≤N-1; q is an integer.

[0089] When switching from high frequency to low frequency, the more second display stages Ti2 there are and the longer the duration of the second display stages Ti2, the more the bias state of the second node N2 of the driving module 11 will shift. When the display cycle includes multiple second display stages Ti2, the data signal D22 of the (q+1)th second display stage Ti2 is controlled to be greater than the data signal D21 of the qth second display stage Ti2. In each display cycle, the difference between the bias state of the driving module 11 in the second display stage Ti2 and the bias state of the driving module 11 in the first display stage Ti1 is gradually reduced, the light emission brightness of the light-emitting element is gradually reduced, and the display brightness is maintained stably when the display panel switches frequencies.

[0090] Figure 27Another display panel driving timing diagram provided by an embodiment of the present invention. Optionally, the first initialization voltage in the first display stage Ti1 is V1; the first initialization voltage in the second display stage Ti2 is V2; where |V1| < |V2|.

[0091] When resetting the anode of the light-emitting element, the first initialization voltage is negative, V1 > V2. When resetting the cathode of the light-emitting element, the first initialization voltage is positive, V1 < V2. Taking the reset of the anode of the light-emitting element as an example, by setting the first initialization voltage VREF1, the charging speed for charging the light-emitting element 20 is adjusted. In an embodiment of the present invention, the voltage value V2 of the first initialization voltage in the second display stage Ti2 is pulled down, the voltage value of the anode of the light-emitting element 20 is reduced, the driving current is reduced, the light-emitting brightness of the light-emitting element 20 is reduced, so that the dark-state brightness after frequency switching is reduced, and the display brightness at low refresh rates in low gray levels is pulled down, reducing the difference between the display brightness at high refresh rates and low refresh rates in low gray levels, and improving the display effect of the display panel.

[0092] Figure 28 Another display panel driving timing diagram provided by an embodiment of the present invention. Optionally, the display cycle of the display panel includes a first display stage Ti1 and N second display stages Ti2; the first second display stage Ti2 is adjacent to the first display stage Ti1. In the r-th second display stage Ti2, the first initialization voltage is V21; in the (r + 1)-th second display stage Ti2, the first initialization voltage is V22; where |V21| < |V22|; 1 ≤ r ≤ N - 1; r is an integer.

[0093] It can be set that the first second display stage Ti2 is adjacent to the first display stage Ti1. Then, in this embodiment, it can be further set that the absolute value of the value V2 of the first initialization voltage gradually increases from the first second display stage Ti2 to the last second display stage Ti2. Specifically, if the total number of the second display stages Ti2 is N, if the first initialization voltage in the r-th second display stage Ti2 is V21 and the first initialization voltage in the (r + 1)-th second display stage Ti2 is V22, |V21| < |V22|. In principle, the leakage degree of the pixel circuit in the (r + 1)-th second display stage Ti2 is greater than that in the r-th second display stage Ti2. Then, the data signal in the (r + 1)-th second display stage Ti2 is increased, and the first initialization voltage is reduced, the voltage value of the anode of the light-emitting element 20 is reduced, the driving current is reduced, the light-emitting brightness of the light-emitting element 20 is reduced, the difference between the display brightness during frequency switching is reduced, and the display effect of the display panel is improved.

[0094] Optionally, the difference between the first initialization voltage V1 in the first display stage Ti1 and the first initialization voltage V2 in the second display stage Ti2 is the first difference S1; the difference between the first initialization voltage V21 in the r-th second display stage Ti2 and the first initialization voltage V22 in the (r+1)-th second display stage Ti2 is the second difference S2; the first difference S1 is greater than or equal to the second difference S2.

[0095] The voltage drop from the first initialization voltage V1 of the first display stage Ti1 to the first initialization voltage V2 of the second display stage Ti2, i.e., the first difference S1, is equal to the voltage drop from the first initialization voltage V21 of the r-th second display stage Ti2 to the first initialization voltage V22 of the (r+1)-th second display stage Ti2, i.e., the second difference S2. The first difference S1 and the second difference S2 can have the same value, thereby reducing the design requirements of the driving circuit in the display panel.

[0096] In other implementations, the leakage current of the transistor decreases over time and as leakage continues. The voltage drop from the first initialization voltage V1 of the first display stage Ti1 to the first initialization voltage V2 of the second display stage Ti2 is relatively large, while the voltage drop from the first initialization voltage V21 of the r-th second display stage Ti2 to the first initialization voltage V22 of the (r+1)-th second display stage Ti2 is relatively small, in order to maintain stable display brightness.

[0097] Continue to refer to Figure 22 Optionally, the display panel may further include: a second initialization module 16 and a storage module 17; the second initialization module 16 is used to connect the second initialization voltage VREF2 and the control terminal of the drive module 11; the storage module 17 is connected between the control terminal of the drive module 11 and the first power signal PVDD; the control terminal of the data writing module 14 is connected to the second scan control signal SP2; the control terminal of the second initialization module 16 is connected to the third scan control signal SN1; the control terminal of the threshold compensation module 15 is connected to the fourth scan control signal SN2; in the first display stage Ti1, the first scan signal SP controls the first initialization module 12 to be turned on, the second scan signal SP2 controls the data writing module 14 to be turned on, the third scan signal SN1 controls the second initialization module 16 to be turned on, and the fourth scan signal SN2 controls the threshold compensation module 15 to be turned on; in the second display stage Ti2, the first scan signal SP controls the first initialization module 12 to be turned on, and the second scan signal SP2 controls the data writing module 14 to be turned on.

[0098] Figure 29 A schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, as shown below. Figure 29 As shown, in this embodiment, the first scan signal and the second scan signal can be the same signal, that is, the first scan signal SP. Therefore, its timing diagram can be as follows: Figure 30 As shown, Figure 30 In another display panel driving timing diagram provided by this embodiment of the invention, in the first display stage Ti1, the first scan signal SP controls the first initialization module 12 and the data writing module 14 to be turned on, the third scan signal SN1 controls the second initialization module 16 to be turned on, and the fourth scan signal SN2 controls the threshold compensation module 15 to be turned on; in the second display stage Ti2, the first scan signal SP controls the first initialization module 12 and the data writing module 14 to be turned on, while the second initialization module 16 and the threshold compensation module 15 are no longer turned on. To reset the first node N1 and the second node N2 respectively, this embodiment controls the first initialization module 12 to be turned on by the first scan signal SP and controls the data writing module 14 to be turned on by the second scan control signal SP2. Specifically, as shown... Figure 31 As shown, Figure 31 Another display panel driving timing diagram provided in this embodiment of the invention: In the first display stage Ti1, the first scan signal SP controls the first initialization module 12 to be turned on, the second scan signal SP2 controls the data writing module 14 to be turned on, the third scan signal SN1 controls the second initialization module 16 to be turned on, and the fourth scan signal SN2 controls the threshold compensation module 15 to be turned on; in the second display stage Ti2, the first scan signal SP controls the first initialization module 12 to be turned on, and the second scan signal SP2 controls the data writing module 14 to be turned on. Then... Figure 31 As shown, when the light-emitting element, i.e., the first node N1, needs to be reset, it can be reset through the first scan signal SP. The reset time is increased during the second display stage Ti2, thereby enhancing the reset effect on the light-emitting element and effectively preventing the brightness of each sub-pixel from exceeding a reasonable range. Furthermore, when resetting the second node N2, the reset time of the second node N2 during the second display stage Ti2 can be less than the reset time of the first node N1, thus preventing current from flowing back from the second node N2 into the first power signal PVDD during the reset process, thus avoiding power waste.

[0099] Optional, continue to refer to Figure 31 When the first initialization module 12 is turned on by the first scan signal SP and the data writing module 14 is turned on by the second scan control signal SP2, the effective pulse of the first scan signal SP2 overlaps with the effective pulse of the third scan signal SN1, and the effective pulse of the second scan signal SP2 overlaps with the effective pulse of the fourth scan signal SN2.

[0100] It is important to note that the effective pulse widths of the first scan signal SP and the second scan signal SP2 can be smaller than those of the third scan signal SN1 and the fourth scan signal SN2 to improve the flexibility of the reset control of the first scan signal SP and the second scan signal SP2. For example, if the minimum effective pulse width of the third scan signal SN1 and the fourth scan signal SN2 is 4 line times, where each line time is the scan time of each sub-pixel, and the scan time of each sub-pixel = effective frame time / total number of lines, then the minimum effective pulse width of the first scan signal SP and the second scan signal SP2 is 2 line times. Therefore, the effective pulse widths of the third scan signal SN1 and the fourth scan signal SN2 can be 4 line times, 8 line times, 12 line times, and so on. The first scan signal SP and the second scan signal SP2 can achieve 2 line times, 4 line times, 6 line times, etc., enhancing the control accuracy of the first scan signal SP on the reset time of the light-emitting element and improving the control accuracy on the display brightness of each pixel.

[0101] This invention also provides a display device. Figure 32 A schematic diagram of the structure of a display device provided in an embodiment of the present invention is shown below. Figure 32 As shown, the display device provided in this embodiment of the invention includes the display panel 1 described in any embodiment of the invention. The display device can be as follows: Figure 32 The mobile phone shown can also be a computer, television, smart wearable device, etc., and this embodiment does not make any special limitation on it.

[0102] The display device provided in the embodiments of the present invention includes the technical features of the display panel provided in any embodiment of the present invention, and has the beneficial effects of the corresponding features.

[0103] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, It includes a pixel circuit and a light-emitting element, wherein the pixel circuit is used to drive the light-emitting element to emit light; The pixel circuit includes a driving module and a light-emitting control module; the driving module is used to generate driving current. The light-emitting control module responds to the light-emitting control signal to control the transmission of the driving current to the light-emitting element; The display panel includes a first working mode and a second working mode, wherein the refresh rate of the first working mode is greater than the refresh rate of the second working mode. In the second working mode, the display cycle of the display panel includes a first display stage and a second display stage; in the first display stage, the duration of the invalid pulse of the light emission control signal is T1; in the second display stage, the duration of the invalid pulse of the light emission control signal is T2; wherein, T1 > T2; The second display stage includes at least two display sub-stages; each display sub-stage is provided with an invalid pulse of the light emission control signal; The invalid pulse duration of the light emission control signal of the last display sub-stage is Ta, and the invalid pulse duration of the light emission control signal of the display sub-stage adjacent to the last display sub-stage is Tb, where Ta > Tb.

2. The display panel according to claim 1, characterized in that: The display cycle of the display panel includes a first display stage and multiple second display stages; The duration of the invalid pulse of the light emission control signal in each of the second display stages is the same.

3. The display panel according to claim 1, characterized in that: The display cycle of the display panel includes a first display stage and multiple second display stages; There are at least two invalid pulse durations of the light emission control signals in the second display stage that are different.

4. The display panel according to claim 3, characterized in that, The display cycle of the display panel includes a first display stage and N second display stages; N is an integer greater than or equal to 2. The first second display stage is adjacent to the first display stage. In the i-th second display stage, the duration of the invalid pulse of the light emission control signal is T21. In the (i+1)th second display stage, the duration of the invalid pulse of the light emission control signal is T22; where T21 > T22; 1 ≤ i ≤ N-1; and i is an integer.

5. The display panel according to claim 4, characterized in that, Both the first display stage and the second display stage include c display sub-stages; each display sub-stage is provided with an invalid pulse of the light emission control signal; c is an integer greater than or equal to 1.

6. The display panel according to claim 5, characterized in that, c is an integer greater than or equal to 2; Within the same first display stage or second display stage, the invalid pulse width of the light emission control signal in each display sub-stage is the same; In two adjacent second display stages, the difference in the invalid pulse width of the light emission control signal is E = H21 - H22; Wherein, H21 and H22 are the invalid pulse widths of the light emission control signals in two adjacent second display stages, respectively; 2L≤E≤8L; L is the line time of the pixel circuit at the current driving frequency f; b represents the total number of rows on the display panel.

7. The display panel according to claim 6, characterized in that, The effective pulse width H1 of the light emission control signal of each display sub-stage in the first second display stage is increased relative to the light emission control signal of each display sub-stage in the first display stage. a% represents the brightness decrease when the driving frequency of the pixel circuit drops from the reference frequency to the current driving frequency f. The effective pulse duration Hp is increased by the light emission control signal of each display sub-stage in the p-th second display stage relative to the light emission control signal of each display sub-stage in the first display stage. +(p-1) ×E;2≤p≤N;p is an integer.

8. The display panel according to claim 5, characterized in that, Within the same second display stage, the invalid pulse widths of the light emission control signals in the two display sub-stages are different.

9. The display panel according to claim 8, characterized in that, In the same second display stage, the invalid pulse width of the light emission control signal in the m-th display sub-stage is Hm, and the invalid pulse width of the light emission control signal in the (m+1)-th display sub-stage is Hm+1; where Hm>Hm+1; 1≤m≤c-1; and m is an integer.

10. The display panel according to claim 4, characterized in that, The first display stage and / or part of the second display stage each include c1 display sub-stages; each display sub-stage is provided with an invalid pulse of the light emission control signal; c1 is an integer greater than or equal to 2; The second display stage includes c2 display sub-stages; c2 is an integer greater than or equal to 1; c2 < c1.

11. The display panel according to claim 4, characterized in that, The first display stage includes multiple display sub-stages; in the Nth second display stage, the first display sub-stage is adjacent to the (N-1)th second display stage.

12. The display panel according to claim 1, characterized in that, Also includes: First initialization module; The first initialization module is used to provide a first initialization voltage to the first node, and the first node is connected to the light-emitting element; The control terminal of the first initialization module transmits the first initialization voltage to the first node in response to the first scan signal; In the first display stage and the second display stage, the time period of the effective pulse of the first scanning signal is located within the time period of the invalid pulse of the light emission control signal.

13. The display panel according to claim 12, characterized in that, In the first display stage and the second display stage, a set time delay is set between the end time of the valid pulse of the first scanning signal and the end time of the invalid pulse of the corresponding light emission control signal.

14. The display panel according to claim 12, characterized in that, In the two second display stages, the proportion of valid pulses of the first scanning signal to invalid pulses of the corresponding light emission control signal is different.

15. The display panel according to claim 13, characterized in that, The duration of the set delay in the first display stage is less than the duration of the set delay in the second display stage.

16. The display panel according to claim 1, characterized in that, When the driving frequency of the pixel circuit is the first frequency f1, the duration of the invalid pulse of the light emission control signal in the second display stage is T23; when the driving frequency of the pixel circuit is the second frequency f2, the duration of the invalid pulse of the light emission control signal in the second display stage is T24; wherein, f1 > f2; T23 > T24.

17. The display panel according to claim 12, characterized in that, Also includes: A data writing module and a threshold compensation module; the data writing module is used to provide data signals to the first terminal of the driving module; the threshold compensation module is connected between the control terminal of the driving module and the second terminal of the driving module; The data signal in the first display stage is D1; ​​the data signal in the second display stage is D2; where |D1| < |D2|.

18. The display panel according to claim 17, characterized in that, The display cycle of the display panel includes a first display stage and N second display stages; The first second display stage is adjacent to the first display stage. In the q-th second display stage, the data signal is D21; in the (q+1)-th second display stage, the data signal is D22; where |D21|<|D22|; 1≤q≤N-1; and q is an integer.

19. The display panel according to claim 12 or 17, characterized in that, The first initialization voltage of the first display stage is V1; the first initialization voltage of the second display stage is V2; wherein, |V1| < |V2|.

20. The display panel according to claim 19, characterized in that, The display cycle of the display panel includes a first display stage and N second display stages; The first second display stage is adjacent to the first display stage. In the r-th second display stage, the first initialization voltage is V21; in the (r+1)-th second display stage, the first initialization voltage is V22; where |V21|<|V22|; 1≤r≤N-1; and r is an integer.

21. The display panel according to claim 20, characterized in that, The difference between the first initialization voltage in the first display stage and the first initialization voltage in the second display stage is the first difference S1; the difference between the first initialization voltage in the r-th second display stage and the first initialization voltage in the (r+1)-th second display stage is the second difference S2; the first difference S1 is greater than or equal to the second difference S2.

22. The display panel according to claim 17, characterized in that, Also includes: The second initialization module and the storage module; The second initialization module is used to connect the second initialization voltage and the control terminal of the drive module; The storage module is connected between the control terminal of the drive module and the first power signal; The control terminal of the data writing module is connected to the second scan signal; the control terminal of the second initialization module is connected to the third scan signal; the control terminal of the threshold compensation module is connected to the fourth scan signal. During the first display phase, the first scan signal controls the first initialization module to be turned on, the second scan signal controls the data writing module to be turned on, the third scan signal controls the second initialization module to be turned on, and the fourth scan signal controls the threshold compensation module to be turned on. During the second display phase, the first scanning signal controls the first initialization module to turn on, and the second scanning signal controls the data writing module to turn on.

23. A display device, characterized in that, Includes the display panel as described in any one of claims 1-22.

Images