Apparatus, system, and method for main sketch and fine sketch circuit for row address tracking

Abstract

Apparatuses, systems, and methods for master sketch and fine sketch circuitry for address tracking. The master sketch circuitry receives a row address and changes selected count values in a first storage structure based on a hash value, where the hash value is generated based on the row address. These count values are compared to a first threshold, and if the threshold is exceeded, then the fine sketch circuitry also receives the row address and changes selected count values in a second storage structure based on a hash value, where the hash value is generated based on the row address. Based on the selected count values in the first storage structure, the second storage structure, or a combination thereof, the row address can be determined to be an attack address.

Description

Technical Field

[0001] This application relates to apparatus, systems, and methods for master sketch and fine sketch circuitry for address tracking. Background Technology

[0002] This disclosure generally relates to semiconductor devices, and more specifically to semiconductor memory devices. In particular, this disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Information can be stored as physical signals (e.g., the charge on a capacitor element) in individual memory cells. The memory can be volatile, and the physical signals may decay over time (which can degrade or destroy the information stored in the memory cells). Therefore, it may be necessary to periodically refresh the information in the memory cells, for example by rewriting the information to restore the physical signals to their initial values.

[0003] Different memory cells may lose information at different rates (e.g., different memory decay rates). Memory can perform automatic refresh operations by sequentially refreshing word lines, resulting in a refresh rate for each word line that is faster than the expected information decay rate. In certain situations, such as certain access patterns, this can lead to an accelerated data decay rate. To address this, as part of the target refresh operation, the memory can identify row addresses that should be refreshed out of order. While tracking accesses to each row of memory individually provides the finest control, this can lead to decreased space and power efficiency. Therefore, row address tracking that reduces footprint while achieving sufficient coverage may be required. Summary of the Invention

[0004] According to an embodiment of this application, an apparatus is described. The apparatus includes a refresh control circuit. The refresh control circuit includes: a first sketch circuit for updating a selected count value among a first plurality of count values ​​based on a row address; a second sketch circuit for updating a selected count value among a second plurality of count values ​​based on the row address when at least one of the selected count values ​​among the first plurality of count values ​​exceeds a first threshold; a target refresh queue for storing the row address when the larger of the minimum value among the selected count values ​​among the first plurality of count values ​​and the minimum value among the selected count values ​​among the second plurality of count values ​​exceeds a second threshold; and a refresh address generator for generating a target refresh address based on the row address in the target refresh queue.

[0005] According to an embodiment of this application, an apparatus is described. The apparatus includes: a first plurality of hash circuits for receiving a row address and providing each of a first plurality of hash values ​​based on the row address; a first storage structure including a first plurality of counter values; a second plurality of hash circuits for receiving the row address in response to activation of a command signal, and for providing each of a second plurality of hash values ​​based on the row address; a second storage structure including a second plurality of counter values, wherein a selected counter value among the second plurality of counter values ​​is changed in response to the second plurality of hash values; and an address queue for storing the row address based on the selected counter value among the first plurality of counter values ​​and a comparison of the selected counter value among the second plurality of counter values ​​with the second threshold. The selected counter value among the first plurality of counter values ​​is changed in response to the first plurality of hash values, and the command signal is activated based on the comparison of the selected counter value among the first plurality of counter values ​​with the first threshold.

[0006] According to an embodiment of this application, a method is described. The method includes: receiving a row address; hashing the row address into a first plurality of hash values; changing a selected count value among the first plurality of count values ​​based on the first plurality of hash values; comparing the selected count value among the first plurality of count values ​​with a threshold; if the selected count value among the first plurality of count values ​​is greater than the threshold, hashing the row address into a second plurality of hash values; changing a selected count value among the second plurality of count values ​​based on the second plurality of hash values; and storing the row address in an address queue based on a comparison result between the selected count value among the first plurality of count values ​​and the selected count value among the second plurality of count values ​​and a second threshold. Attached Figure Description

[0007] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 This is a block diagram of a refresh control circuit according to some embodiments of the present disclosure.

[0009] Figure 3 This is a block diagram of an attack detection circuit according to some embodiments of the present disclosure.

[0010] Figure 4 These are tables according to some embodiments of this disclosure.

[0011] Figure 5 This is a flowchart of a method according to some embodiments of the present disclosure. Detailed Implementation

[0012] The following description of certain embodiments is exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings, which form part of the present system and method, illustrating specific embodiments in which the described system and method can be implemented. These embodiments have been described in detail to enable those skilled in the art to implement the systems and methods currently disclosed, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, certain features that are obvious to those skilled in the art will not be described in detail so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be considered limiting, and the scope of this disclosure is defined only by the appended claims.

[0013] Information in volatile storage devices can be stored in memory cells (e.g., as charge on a capacitor element) and may decay over time. In each bank of a memory array, memory cells can be organized into rows (word lines) and columns (bit lines). Memory cells can be refreshed row by row. To prevent information from being lost or corrupted due to this decay, the memory can perform a background refresh process, such as an auto-refresh operation. During a refresh operation, information can be rewritten to the memory cells associated with the word lines to restore their initial state. Auto-refresh operations can be performed sequentially on the word lines of the memory, such that all word lines are refreshed within a refresh cycle.

[0014] The rate at which refresh operations are performed can be selected to prevent information loss; ideally, each memory cell should be refreshed before the information stored in it is lost. The rate at which refresh cycles are performed can be based on the expected fastest rate of information decay. However, certain access patterns to memory rows (attack rows or attack word lines) may cause a faster rate of decay for memory cells in nearby rows (victim rows or victim word lines). Therefore, it may be important to identify these attack rows so that the victim rows associated with the attack rows can be refreshed as part of a targeted refresh operation outside of the normal auto-refresh sequence.

[0015] Sketch circuits can be used to track accesses to row addresses. In a sketch circuit, the row address is input to a set of hash circuits, each providing an output value based on the row address. The output values ​​may differ because the hash circuits use different hash functions (and / or different seed values). These output values ​​are used to index one of multiple count values ​​that vary (e.g., increment). The state (e.g., number of bits) of each hash circuit's output value may be less than the state (e.g., number of bits) of the row address. Therefore, more than one row address may cause a particular hash circuit to have the same output value (e.g., a collision). This can lead to overcounting of accesses. Similarly, when a row is flushed and the count changes in a second direction (e.g., decrement, reset, etc.), there may be incomplete counting of accesses to a particular row. This can be problematic because a row is accessed frequently enough that its victim row should be flushed, but its count is artificially lowered.

[0016] This disclosure relates to sketch and fine-scale sketch circuitry for address tracing. Attack detection circuitry for a memory may include two sketch circuits—a main sketch circuit and a fine-scale sketch circuit. The two sketch circuits may have their own sets of hash circuits. The hash circuit of the main sketch circuit may provide a value with more bits than the hash circuit of the fine-scale sketch circuit. Therefore, the fine-scale sketch circuit may have more collisions and fewer memory count values ​​compared to the main sketch circuit.

[0017] When a row address is received, it is provided to the main sketch circuit, which modifies (e.g., increments) a set of count values, each indexed by a value from the corresponding hash circuit. If any count value exceeds a fine sketch threshold, the row address can also be received by the fine sketch circuit, which modifies (e.g., increments) a set of count values, each indexed by a value from the corresponding hash circuit. The updated count values ​​in both the main sketch circuit and the fine sketch circuit can be compared, and the minimum change count value (i.e., the count value associated with the row address) can be obtained from both. The larger of these two minimum values ​​is compared to a hammer threshold; if it is greater than the hammer threshold, the row address can be stored in the attack address queue so that its victim row can be refreshed later. This helps reduce errors caused by undercounting access to a particular address.

[0018] In some embodiments, the attack detection circuitry can also track the address associated with the maximum count value in the main sketch circuitry. This address can also be provided to the fine sketch circuitry when the address changes (e.g., when the count value at a new address becomes the maximum value).

[0019] Figure 1This is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0020] Semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory cells. Figure 1 In one embodiment, the memory array 118 is shown as comprising eight memory banks BANK0 to BANK7. In other embodiments, the memory array 118 may include more or fewer memory banks. Each memory bank includes multiple word lines WL, multiple bit lines BL and / BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / BL. Word lines WL are selected by row decoder 108, and bit lines BL and / BL are selected by column decoder 110. Figure 1 In this embodiment, row decoder 108 includes a row decoder for each memory bank, and column decoder 110 includes a column decoder for each memory bank. Bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). Read data from bit lines BL or / BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 120 via the complementary local data line (LIOT / B), the transmission gate (TG), and the complementary master data line (MIOT / B). Conversely, write data output from the read / write amplifier 120 is transmitted to the sense amplifier SAMP via the complementary master data line MIOT / B, the transmission gate TG, and the complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0021] Semiconductor device 100 may employ multiple external terminals, including command and address (C / A) terminals coupled to the command and address bus to receive command and address signals and CS signals, clock terminals for receiving clocks CK and / CK, data terminals DQ for providing data, and power terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0022] An external clock CK and / CK is provided to the clock terminal of the input circuit 112. The external clocks can be complementary. The input circuit 112 generates an internal clock ICLK based on the clocks CK and / CK. The clock ICLK is provided to the command decoder 110 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the clock ICLK. The clock LCLK can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of the circuits included in the input / output circuit 122, for example, to the data receiver to time the reception of written data.

[0023] A memory address can be provided to the C / A terminal. The memory address provided to the C / A terminal is transmitted to the address decoder 104 via command / address input circuitry 102. Address decoder 104 receives the address and provides the decoded row address XADD to row decoder 108 and the decoded column address YADD to column decoder 110. Address decoder 104 can also provide a decoded bank address BADD, which indicates the bank of memory in memory array 118 containing the decoded row address XADD and column address YADD. Commands can be provided to the C / A terminal. Examples of commands include timing commands for controlling various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, as well as other commands and operations. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cell to be accessed.

[0024] Commands can be provided to the command decoder 106 as internal command signals via the command / address input circuit 102. The command decoder 106 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0025] The access command received by device 100 can be a read command. When a read command is received and is promptly provided with the bank address, row address, and column address, read data is read from the memory cells of memory array 118 corresponding to the row and column addresses. Command decoder 106 receives the read command and provides an internal command to provide the read data read from memory array 118 to read / write amplifier 120. The read data is output to the outside via input / output circuit 122 from data terminal DQ.

[0026] The access command received by device 100 can be a write command. When a write command is received and is promptly provided to the memory bank address, row address, and column address, the write data provided to the data terminal DQ is written to the memory cell of memory array 118 corresponding to the row address and column address. Command decoder 106 receives the write command and provides an internal command so that the write data can be received by the data receiver in input / output circuit 122. A write clock can also be provided to an external clock terminal to time the operation of the data receiver of input / output circuit 122 receiving write data. The write data is provided to read / write amplifier 120 through input / output circuit 122, and then provided to memory array 118 by read / write amplifier 120 to be written to memory cell MC.

[0027] As part of the self-refresh mode, device 100 may also receive commands that cause it to perform one or more refresh operations. In some embodiments, the self-refresh mode command may be sent from an external source to storage device 100. In some embodiments, the self-refresh mode command may be generated periodically by components of the device. In some embodiments, a refresh signal AREF may be activated simultaneously when an external signal indicates a self-refresh entry command. The refresh signal AREF may be a pulse signal that is activated when command decoder 106 receives a signal indicating entry into self-refresh mode. The refresh signal AREF may be activated immediately after command input and may subsequently be activated periodically within a predetermined internal timing period. The refresh signal AREF can be used to time refresh operations during self-refresh mode. Therefore, refresh operations can be performed automatically. A self-refresh exit command may cause the refresh signal AREF to stop being automatically activated and cause device 100 to return to an idle state and / or resume other operations.

[0028] The refresh signal AREF is provided to the refresh control circuit 116. The refresh control circuit 116 provides a refresh row address RXADD to the row decoder 108, which can refresh one or more word lines WL indicated by the refresh row address RXADD. In some embodiments, the refresh address RXADD may represent a single word line. In some embodiments, the refresh address RXADD may represent multiple word lines, which can be refreshed sequentially or simultaneously by the row decoder 108. In some embodiments, the number of word lines represented by the refresh address RXADD may vary depending on the refresh address. The refresh control circuit 116 can be controlled to change the details of the refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address, and the number of word lines represented by the address), or the refresh control circuit 116 can operate based on internal logic.

[0029] The refresh control circuit 116 can selectively output a target refresh address (e.g., which determines one or more victim addresses based on an attack) or an auto-refresh address (e.g., from an auto-refresh address sequence) as the refresh address RXADD. Based on the type of the refresh address RXADD (in some embodiments, the type of operation is indicated by one or more additional signals), the row decoder 108 can perform a target refresh or auto-refresh operation. The auto-refresh address can be derived from an address sequence such that all word lines are refreshed within one cycle of the sequence. For example, a counting circuit can be used to increment or otherwise “count” the row address values ​​of possible RXADDs. The refresh control circuit 116 can cycle through the auto-refresh address sequence at a rate determined by AREF. One refresh cycle can represent that the auto-refresh address generator refreshes each row of the memory (e.g., provides the value for each auto-refresh address). In some embodiments, the auto-refresh operation can typically occur periodically, thereby cyclically operating the auto-refresh address sequence so that for a given word line, no information degradation occurs between the execution of auto-refresh operations. In other words, the automatic refresh operation is performed to refresh each word line at a rate that is faster than the expected information decay rate.

[0030] The refresh control circuit 116 can also determine the target refresh address (e.g., the victim address corresponding to the victim row) to be refreshed based on the access patterns of nearby addresses (e.g., the attack address corresponding to the attack row) in the memory array 118. The refresh control circuit 116 can use one or more signals from device 100 to calculate the target refresh address RXADD. For example, the refresh address RXADD can be calculated based on the row address XADD provided by the address decoder.

[0031] While this disclosure generally relates to identifying attacking and victim word lines and addresses, it should be understood that, herein, an attacking word line does not necessarily cause data degradation in adjacent word lines, nor does a victim word line necessarily experience such degradation. The refresh control circuit 116 can determine whether an address is an attacking address based on certain criteria, thereby acquiring potential attacking addresses, rather than explicitly determining which addresses are causing data degradation at nearby victim addresses. For example, the refresh control circuit 116 can determine potential attacking addresses based on address access patterns, and this criterion may include some addresses that are not attacking addresses and omit some addresses that are attacking addresses. Similarly, victim addresses can be determined based on which word lines are expected to be affected by an attack, rather than explicitly determining which word lines are experiencing increasing data decay rates.

[0032] The refresh control circuit 116 includes an attack detection circuit that monitors row addresses XADD to determine which rows are attack rows, where the row addresses XADD are provided as part of an access operation. The attack detection circuit includes a main sketch circuit and a fine sketch circuit. The main sketch circuit receives all row addresses XADD provided via the row address bus. The main sketch circuit hashes the row addresses XADD into a set of hash values, each hash value coming from a corresponding hash circuit. Each hash value is used to index a value in a set of count values ​​associated with each hash circuit. For example, if there are i hash circuits, each outputting a j-bit hash value, then there may be i*2^j count values, and for each possible hash value, each hash circuit is associated with a count value. Based on the hash values, the count values ​​are updated (e.g., incremented). If any updated count value exceeds a fine count threshold, the fine sketch circuit can also update a set of count values ​​based on the row addresses XADD (in a manner similar to the main sketch circuit). The values ​​stored in the main sketch circuit and the fine sketch circuit can be used to determine whether address XADD is an attack address. Figure 2 An exemplary refresh control circuit using a master sketch circuit and a fine sketch circuit is described in more detail below.

[0033] Power supply potentials VDD and VSS are provided to the power supply terminals. These potentials are also provided to the internal voltage generation circuit 124. The internal voltage generation circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS provided to the power supply terminals. Internal potential VPP is primarily used in the row decoder 108, internal potentials VOD and VARY are primarily used in the sense amplifiers (SAMPs) included in the memory array 118, and internal potential VPERI is used in multiple peripheral circuit blocks.

[0034] Simultaneously, power supply potentials VDDQ and VSSQ are provided to the power supply terminals. These potentials are supplied to the input / output circuit 122. In one embodiment of this disclosure, the power supply potentials VDDQ and VSSQ provided to the power supply terminals may be the same as the power supply potentials VDD and VSS provided to the power supply terminals. In another embodiment of this disclosure, the power supply potentials VDDQ and VSSQ provided to the power supply terminals may be different from the power supply potentials VDD and VSS provided to the power supply terminals. The power supply potentials VDDQ and VSSQ provided to the power supply terminals are used in the input / output circuit 122 to prevent power supply noise generated by the input / output circuit 122 from propagating to other circuit blocks.

[0035] Figure 2 This is a block diagram of a refresh control circuit according to some embodiments of the present disclosure. In some embodiments, the refresh control circuit 200 may include... Figure 1In the refresh control circuit 116. The refresh control circuit 200 receives the refresh signal AREF, which controls the time at which the refresh control circuit 200 provides the refresh address RXADD. Figure 2 The diagram also shows a line decoder 250 (such as...). Figure 1 The row decoder 108 can refresh one or more word lines of the memory array based on the refresh address RXADD.

[0036] The refresh control circuit 200 includes a refresh cycle generator 202 that receives a refresh signal AREF and determines the timing of a refresh operation based on AREF. The refresh control circuit 200 also determines whether an automatic refresh operation or a targeted refresh operation should be performed and provides signals such as a target refresh signal RHR and an internal refresh signal IREF, indicating which type of refresh operation should be performed. The refresh control circuit 200 includes a refresh address generator 204 that generates a refresh address RXADD based in part on signals received from the refresh cycle generator 202. During a targeted refresh operation, the target refresh address generator 206 of the refresh address generator 204 can provide a target refresh address as RXADD based on an attack address AggXADD identified by an attack detector. During an automatic refresh operation, the automatic refresh address generator 208 of the refresh address generator 204 can generate an automatic refresh address as RXADD. Based on the refresh address RXADD, along with other signals such as IREF / RHR, the row decoder 250 refreshes the memory array (e.g., memory array) associated with the refresh address RXADD. Figure 1 One or more word lines in 118).

[0037] The refresh cycle generator 202 can receive the refresh signal AREF based on the timing of the refresh signal AREF and provide internal refresh signals IREF and / or RHR. Signals IREF and RHR can be used to indicate which type of refresh operation should be performed. For example, in some embodiments, IREF being activated while RHR is not activated can indicate an automatic refresh operation, while both IREF and RHR being activated can indicate a target refresh operation. Other signal patterns can be used in other embodiments. In response to the activation of the refresh signal AREF, the refresh cycle generator 202 can indicate that one or more refresh operations should be performed. In some embodiments, in response to the individual activation of AREF, the refresh cycle generator 202 can perform multiple "pumps" associated with a refresh operation. In example operations, when AREF is activated, the refresh cycle generator 202 can perform 2, 4, 6, or 8 pumps, each pump associated with a refresh operation. More or fewer refresh operations can also be performed each time AREF is activated. The refresh cycle generator 202 can use internal logic to determine whether each refresh operation should be a target refresh operation or an automatic refresh operation.

[0038] Refresh address generator 204 may include circuitry for generating a refresh address RXADD when a target refresh operation is required (e.g., when both IREF and RHR are activated). Target refresh address generator 206 may generate a target refresh address and provide it as RXADD. The refresh address RXADD may be based on an attack address AggXADD identified by attack detector 210. For example, the refresh address may represent a word line adjacent to the attack address AggXADD (e.g., AggXADD+1 and AggXADD-1). Other associated addresses (e.g., AggXADD+ / -2, AggXADD+ / -3, etc.) may also be used. Target refresh address generator 206 may provide multiple refresh addresses based on a single identified attack address. For example, a first refresh address RXADD may correspond to a first adjacent word line (e.g., AggXADD+1), and a second refresh address RXADD provided as part of a different refresh operation (e.g., as part of a different pump) may represent a second adjacent word line (e.g., AggXADD-1).

[0039] Refresh address generator 204 may include auto-refresh address generator 208, which provides an auto-refresh address as RXADD in response to an auto-refresh operation (e.g., IREF is activated while RHR is not activated). The auto-refresh address may be generated from a refresh address sequence. For example, a counter may be used to count the values ​​of all possible row addresses so that all word lines are refreshed during a refresh cycle. In some embodiments, the auto-refresh address may be associated with more than one word line. For example, with a normal row address (e.g., ...). Figure 1 Compared to XADD in the past, the auto-refresh address can be truncated and associated with each word line that shares the truncated portion.

[0040] Attack detection circuit 210 uses a sketch data structure to store information about access counts for different row addresses XADD. Based on these access counts, a row can be identified as an attack row and provided as the attack address AggXADD. Attack detector 210 includes a main sketch circuit, which includes a first set of hash circuits 212 and a storage structure 214, and a 'fine' sketch circuit, which includes a second set of hash circuits 222 and a second storage structure 224. The terms 'main' and 'fine' as used herein are used only to distinguish the two sketch circuits. The main sketch circuit and the fine sketch circuit may include similar components and operate in a similar manner. In some embodiments, the two sketch circuits may share components. Each sketch circuit includes a respective storage structure 214 / 224, which includes a table of count values. Figure 3As explained in more detail below, the table entries may include rows indexed by hash functions in hash circuits 212 or 222, and columns indexed by values ​​output by the hash functions. It should be understood that the description of table entries by rows and columns is a conceptualization of how table entries are composed. Table entries can be physically composed in any manner.

[0041] The main sketch circuitry includes multiple hash circuits 212. Each hash circuit 212 can receive a common row address XADD and provide corresponding values ​​from Value0 to ValueM. Each hash circuit 212 can receive address XADD as an input value and provide a corresponding value (Value0 to ValueN) based on address XADD. For example, the number of hash circuits 212 may be equal to the number of output values ​​(e.g., Hash0 to HashN), and the i-th hash circuit can provide the i-th output value (e.g., Hashi).

[0042] Address XADD may have a first bit (e.g., 17 bits). Value may have a second bit less than the first bit. Therefore, the total number of possible states for the value may be less than the number of states for address XADD. Thus, conflicts may exist between input states (e.g., the value of XADD) and output states (e.g., the value of Value) provided by each hash circuit 212. For example, each state of Value may represent 8, 16, 32, or some other number of possible values ​​for XADD. In some embodiments, each value output by hash circuit 212 may have the same number of bits. If each hash circuit 212 can provide a total of M possible values ​​(e.g., the number of bits k such that 2^k = 2^k), then... k =M), and there are N hash circuits 212 in total, then the storage structure 214 can be a table with a total of N×M entries.

[0043] Each hash circuit 212 can perform different hash operations on the input value (e.g., XADD) by implementing different hash operations. In some embodiments, this may be due to the different hash functions used by each hash circuit 212. In some embodiments, the different operations may also be due to the different seed values ​​input to each hash circuit 212. For example, each hash circuit 212 may have the same hash function but may have different seed values. In some embodiments, different combinations of hash functions and seed values ​​can be used to change the hash operation of the hash circuit 212.

[0044] The count values ​​associated with (e.g., indexed by) the provided values ​​Value0 to ValueM (and the hash circuitry providing these values) in storage structure 214 can be retrieved and provided to logic circuitry 216. Logic circuitry 216 can determine whether the current row address XADD is an attack address based on the count values. If the address is an attack address, the address XADD can be stored (e.g., in an attack address queue) and provided as address AggXADD. The count values ​​retrieved from storage structure 214 can also be used to determine whether the signal Slim_Insert should be provided. If the signal Slim_Insert is active, the fine hash circuitry (e.g., hash circuitry 222 and storage structure 224) can also receive the address XADD and update the corresponding count value in fine storage structure 224.

[0045] Hash circuit 222 and fine storage structure 224 can operate in a manner similar to hash circuit 212 and storage structure 214 previously described. When the signal Slim_Insert is activated, hash circuit 222 provides a set of hash values ​​Value0 to ValueM for indexing count values ​​stored in fine storage structure 224. Hash circuits 212 and 222 can have different or the same number of hash circuits. The hash value generated by hash circuit 222 can have a different number of bits than the hash value generated by hash circuit 212. For example, the number of bits in the value hashed by hash circuit 222 can be less than the number of bits in the value hashed by hash circuit 212. Accordingly, if there are P hash circuits in hash circuit 222, and each hash value has L distinct states, then fine storage structure 224 can be a table with P×L count values. Typically, fine storage structure 224 stores fewer count values ​​than storage structure 214. In response to the value from hash circuit 222, the fine storage structure can provide a set of count values ​​Slim_Counts.

[0046] As described in more detail herein, detection logic 216 can modify count values ​​Counts and / or Slim_Counts. For example, count values ​​Counts and / or Slim_Counts can be incremented to indicate that the row address XADD associated with that count value has been accessed. Detection logic 216 can use count values ​​Counts and / or Slim_Counts to determine whether address XADD is an attack address (e.g., by comparing one or more Counts and Slim_Counts with a threshold). If address XADD is an attack address, detection logic 216 can also delete (e.g., by subtracting a minimum count value) one or more Counts or Slim_Counts to indicate that address XADD has been placed in the attack address queue.

[0047] In some embodiments, the attack detection circuit 210 may use different methods to determine whether address XADD is an attack address. For example, one method may be to compare one or more count values ​​Counts and / or Slim_Counts with a threshold. Another method may be to obtain the address associated with the maximum value of the count values ​​Counts and / or Slim_Counts, regardless of whether that value exceeds the threshold. The address associated with the current maximum count value may be stored and updated if the count value of a different address exceeds it. In some embodiments, the attack detector 210 may use multiple methods. For example, the count value may be compared with a threshold, and the address associated with the current maximum value may be used.

[0048] Similarly, different criteria can be used to determine when to provide the Slim_Insert signal and update the fine-grained circuitry. For example, one or more count values ​​(Counts) can be compared to a threshold and / or the Slim_Insert signal can be provided each time the address associated with the maximum count value is updated. The threshold used to determine whether the Slim_Insert signal should be provided can be the same as or different from the threshold used to determine whether an address is an attack address.

[0049] Figure 3 This is a block diagram of an attack detection circuit according to some embodiments of the present disclosure. In some embodiments, the attack detection circuit 300 may include... Figure 2 The attack detector 200 includes a main sketch circuit 310, a fine sketch circuit 320, and a logic circuit 330 (such as...). Figure 2 (See section 216). An exemplary attack detector 300 illustrates one embodiment where a count value is compared to a threshold to determine if address XADD is an attack address, which can then be stored in a refresh address queue 336. The attack detector 300 also stores addresses associated with a maximum count value, which are used as attack addresses if a target refresh requires an address but no count value is stored in queue 336.

[0050] The attack detector 300 includes a main sketch circuit 310 and a fine sketch circuit 320. Since the two circuits may be largely similar, only the main sketch circuit 310 will be described in detail here. The main sketch circuit 310 includes a set of hash generators 312 (e.g., Figure 2Hash generator 312 (212 in the original text) receives a row address XADD, which is provided as part of an access operation in memory (e.g., a read or write operation). Hash generator 312 includes multiple hash circuits, each providing a hash value based on the row address XADD. For example, if hash generator 312 includes three hash circuits, it produces three hash values. Each hash circuit can use a different hash function (and / or the same hash function but a different seed value, etc.) to make the hash values ​​independent of each other.

[0051] Hash values ​​are used to index data storage structure 314 (e.g., Figure 2 A set of count values ​​in (214) of the hash circuit. For example, if each hash value is a 6-bit number, then any given hash value may have 64 unique values. Therefore, the storage structure can include 64 distinct count values ​​on each row, and the number of rows is equal to the number of hash circuits in hash circuit 312. For clarity, Figure 3 Only a portion of the rows and columns are shown. Each count value can be a binary number used to indicate the number of accesses.

[0052] Based on the hash value received from hash circuit 312, an index count value is provided to counting circuit 316. Counting circuit 316 can adjust the index count value. For example, counting circuit 316 can increment the index count value. Counting circuit 316 can compare the index count values ​​and use the minimum value among them as Main_Count. In response to the Delete signal being active, delete logic circuit 350 can activate Delete based on the attack address AggXADD provided by multiplexer 338. In response to the activation of Delete, the minimum count value associated with the current address XADD can be subtracted from all count values ​​associated with XADD.

[0053] The main counting circuit 316 can provide the detection logic circuit 330 with the minimum of the count values ​​associated with the current row address XADD. The detection logic circuit 330 includes a comparator 332 that compares the current count value with a fine threshold to determine whether the signal Slim_Insert should be activated. The signal Slim_Insert is activated if Main_Count (which is the minimum count value indexed by the hash value) is greater than the fine threshold. As described in more detail herein, the comparator 332 can also compare one or more main count values ​​Main_Count and the fine count value from the fine sketch circuit 320 with an attack threshold to determine whether the attack detection signal AggDet should be activated. The fine threshold and the attack threshold can be the same and / or different. One or both of the thresholds can be memory settings a.

[0054] The fine sketch circuit 320 has essentially similar components and operations to the main sketch circuit 310, except that when the Slim_Insert signal is activated (e.g., when Main_Count exceeds a threshold in the comparison circuit 332), the fine sketch circuit 320 only responds to the row address XADD. The fine sketch circuit 320 includes a set of hash circuits 322 that, when Slim_Insert is activated, provides a set of hash values ​​based on the row address XADD. These hash values ​​are used to index the storage structure 324 (e.g., ...). Figure 2 The fine storage structure 324 can include fewer entries than the main storage structure 224. For example, each hash value provided by the fine hash circuit 322 can include fewer bits, so the fine storage structure 324 can have fewer "columns". For example, a fine hash value might be a 3-digit number, so there could be 8 columns. If there are 3 hash circuits in the hash circuit 322, the storage structure 324 can include 3 × 8 count values.

[0055] The index count value is provided to the counting circuit 326. The counting circuit 326 can update the index count value. For example, the counting circuit 326 can compare the index count value with the count value of the index in the main storage structure 314, and set the index count value of the fine storage structure 324 to the maximum value of the index count values ​​in the main storage structure 314 and the fine storage structure 324. The count values ​​are compared, and the minimum value among the index count values ​​is provided as the value Slim_Count.

[0056] The delete logic circuit 350 can generate the Slim_Delete signal separately from the Delete signal. When the Slim_Delete signal is received, the fine sketch circuit 320 can compare the index count value with the index count value in the main sketch storage structure 314. The minimum index count value Main_Count in the main storage structure 314 can be compared with the minimum index count value in the fine storage structure 324. Then, the smaller value between Slim_Count and Main_Count can be subtracted from all the count values ​​associated with the row address XADD.

[0057] If the comparator receives only Main_Count (e.g., Slim_Insert is not activated), it compares the count value Main_Count with the attack threshold. If both Main_Count and Slim_Count are received (e.g., Slim_Insert is activated), comparator 332 compares the larger of Main_Count and Slim_Count with the attack threshold. If the attack threshold is exceeded, the signal AggDet is activated. In response to the activation of AggDet, the current row address XADD is retrieved and added to the refresh address queue 336. In response to the activation of AggDet, the row address XADD provided by logic circuit 339 is retrieved and added to queue 336. Queue 336 may be a storage structure that holds multiple addresses. In response to the activation of AggDet, multiplexer 338 provides one of the addresses stored in queue 336 as the attack address AggXADD.

[0058] The attack detector 300 also includes logic circuitry for storing and providing the row address associated with the maximum value among the minimum index count values ​​in the address of the main count value storage structure 314. The main count value Main_Count is provided to the maximum detection logic circuitry 340. The maximum count value logic circuitry 340 includes a maximum count value storage structure 344 and an address storage structure 346. The maximum count value storage structure 344 holds the maximum count value, and the address storage structure 346 holds the address associated with that count value. Comparator 342 compares the main count value Main_Count with the count value stored in the maximum count value storage structure 344. If the count value Main_Count is greater than the stored count value, a signal is sent to the acquisition logic circuitry 348 to replace the value stored in the count value storage structure 344 with the value of Main_Count and replace the address stored in the address storage structure 346 with XADD. The above signal can also be used as the signal Slim_Insert. Therefore, when the Main_Count value exceeds the threshold or is greater than the maximum count value stored in the count value storage structure 344, the fine sketch circuit 320 can receive the row address XADD.

[0059] The address from address storage structure 346 is stored in latch circuit 334. Multiplexer 338 provides the attack address AggXADD. If signal AggDet is activated, indicating that there is at least one address in refresh queue 336, the address in address queue 336 is provided as AggXADD, and the delete logic circuit 350 activates signal Delete. Otherwise, the address in latch 334 is provided as address AggXADD.

[0060] Figure 4This is a table according to some embodiments of the present disclosure. Table 400 may represent, for example... Figure 2 210 and / or Figure 3 The table shows a set of operations for an exemplary attack detection circuit of type 300. The table displays three rows, each representing one of the operations that the sketch circuit can perform, such as updating a value in a memory structure, querying a value in a memory structure, or deleting one or more values ​​in a memory structure. The columns in the table represent the main sketch circuit (e.g., ...). Figure 3 310) and fine sketch circuits (e.g., Figure 3 (320) operations or further comments on operations.

[0061] Upon receiving a row address, the exemplary master sketch circuit can respond to each row address (e.g., each time the signal ACT is activated). For a row address, the count value associated with that row address can be incremented (e.g., the count value is an index of the hash value generated from the row address). In the fine sketch circuit, only when one or more count values ​​in the master sketch circuit associated with a row address (e.g., the minimum of the associated count values) exceed the fine insertion threshold HT_slim, or when the maximum row address is replaced (e.g., the count value exceeds...). Figure 3 The row address will only be received when the count value stored in the count value storage structure 344 is received. In the fine sketch circuit, when the row address is received, the count value in the fine sketch circuit is set to the maximum value of the count values ​​in the main sketch circuit and the fine sketch circuit associated with that row address.

[0062] The count values ​​provided by the main sketch circuit and the fine sketch circuit (e.g., as part of a query) can represent the minimum count value in each corresponding sketch circuit associated with the row address. It can be determined whether the count value is greater than the hammer threshold based on the larger of the two minimum count values.

[0063] The main sketch circuit and the fine sketch circuit may have separate triggered deletion operations (e.g., via separate deletion signals). When a deletion operation is triggered in the main sketch circuit, the minimum count value associated with that row address is subtracted from the other count values ​​associated with that row address. When a deletion operation is triggered in the fine sketch circuit, the minimum of the minimum count values ​​associated with the addresses in both sketch circuits is found, and that minimum value is subtracted from the count value associated with the row address in the fine sketch circuit.

[0064] Figure 5 This is a flowchart of a method according to some embodiments of the present disclosure. In some embodiments, method 500 may be implemented using any of the apparatus or systems described herein.

[0065] Method 500 includes a block 510 describing the received row address. The row address may be part of an access operation and may be accompanied by other signals, such as ACT. The row address may be determined by attack detection circuitry (e.g., Figure 2 210 and / or Figure 3 (300) Receive.

[0066] Method 500 includes block 520, which is described, for example, via a first set of hash circuits (e.g., Figure 2 212 and / or Figure 3 (312) Hash the row address into a first plurality of hash values. Each hash value of the first plurality of hash values ​​can be generated using different hash functions (and / or the same hash function with different seed values, etc.).

[0067] Method 500 includes block 530, which describes changing a selected count value among a first plurality of count values ​​based on a first plurality of hash values. The selected count value among the first plurality of count values ​​can be selected based on a corresponding hash value among the first plurality of hash values. For example, each value of the first plurality of hash values ​​can be indexed row by row, where each row is associated with a hash circuit that generated the hash value. The selected count value can be incremented.

[0068] Method 500 includes block 540, which describes comparing a selected count value from the first plurality of count values ​​with a threshold. For example, the minimum value among the selected count values ​​from the first plurality of count values ​​can be compared with the threshold. If the minimum value is greater than the threshold, the method proceeds to block 550. If the minimum value is not greater than the threshold, the minimum value can be compared with a second threshold, and if it is greater than the second threshold, the row address can be stored in an address queue.

[0069] Method 500 includes block 550, which describes hashing the row address into a second plurality of hash values ​​if a selected count value among a first plurality of count values ​​is greater than a threshold. For example, a comparator (e.g., Figure 3 (332) can provide a fine-grained insertion signal when at least one selected count value in the first count values ​​is higher than a threshold. Fine-grained sketch circuit (e.g., Figure 2 (320) can receive the row address signal when the fine insertion signal is activated, and can generate hash values ​​in a manner similar to that described in box 520.

[0070] Method 500 includes box 560, which describes changing a selected count value among a second plurality of count values ​​based on a second plurality of hash values. This operation is similar to box 530, but it modifies the count values ​​in a different fine-grained storage structure. For example, a selected count value among the second plurality of count values ​​can be set to the maximum of a selected count value among the first and second count values.

[0071] Method 500 includes block 570, which describes storing a row address in an address queue based on a comparison of a selected count value from a first plurality of count values ​​and a selected count value from a second plurality of count values ​​with a second threshold. For example, the larger of the minimum of the selected count values ​​from the first plurality of count values ​​and the minimum of the selected count values ​​from the second plurality of count values ​​is compared with the second threshold. If the larger value exceeds the second threshold, the address can be added to the address queue. The addresses in the queue can be provided as attack addresses, and as part of a target refresh operation, a target refresh address can be generated based on the attack address for use in performing the refresh operation.

[0072] In some embodiments, method 500 optionally includes comparing a selected count value from a first plurality of count values ​​with a stored maximum count value. If the minimum of the selected count values ​​in the first plurality of count values ​​exceeds the stored maximum value, the count value is stored as the new maximum value, and the row address is stored. If the minimum of the selected count values ​​in the first plurality of count values ​​exceeds the stored maximum value, a fine-grained insertion signal may be provided to allow the method to proceed to block 550, even if the selected count values ​​in the first plurality of count values ​​do not exceed a threshold. If the address queue is empty, the stored row address may be provided as the attack address.

[0073] In this document, signal activation can refer to any part of the signal waveform in response to a circuit. For example, if the circuit responds to a rising edge, a signal switching from a low level to a high level might be an activation operation. One example type of activation is a pulse, where the signal switches from a low level to a high level for a short period and then returns to a low level. This might trigger circuitry responding to rising edges, falling edges, and / or signals at high logic levels. Those skilled in the art will understand that while embodiments may be described by reference to a specific type of activation (e.g., high-level activation) used by a particular circuit, other embodiments may use other types of activation (e.g., low-level activation).

[0074] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or may be separated and / or performed in separate devices or device portions according to the system, device, and method.

[0075] Finally, the foregoing discussion is intended to illustrate the system only and should not be construed as limiting the appended claims to any particular embodiment or set of embodiments. Therefore, while the system has been described in particular detail with reference to exemplary embodiments, it should be understood that those skilled in the art can devise various modifications and alternative embodiments without departing from the broader and contemplated spirit and scope of the system set forth in the appended claims. Thus, the specification and drawings should be considered illustrative and not intended to limit the scope of the appended claims.

Claims

1. An apparatus comprising: The refresh control circuit includes: A first sketch circuit is used to update a selected count value among a first plurality of count values ​​based on a row address; The second sketch circuit is used to update the selected count value among the second plurality of count values ​​based on the row address when at least one of the selected count values ​​among the first plurality of count values ​​exceeds the first threshold. A target refresh queue is used to store the row address when the larger of the minimum value among the selected count values ​​in the first plurality of count values ​​and the minimum value among the selected count values ​​in the second plurality of count values ​​exceeds a second threshold. A refresh address generator is used to generate a target refresh address based on the row address in the target refresh queue.

2. The apparatus of claim 1, wherein the first sketch circuit comprises: A first plurality of hash circuits are configured to generate each of a first plurality of hash values ​​based on the row address; A first storage structure is used to store the first plurality of count values, wherein the selected count value is selected from the first plurality of count values ​​based on the first plurality of hash values; A second plurality of hash circuits are used to generate each of the second plurality of hash values ​​based on the row address; A second storage structure is used to store the second plurality of count values, wherein the selected count value is selected from the second plurality of count values ​​based on the second plurality of hash values.

3. The apparatus of claim 2, wherein each of the first plurality of hash values ​​has a first bit number, and wherein each of the second plurality of hash values ​​has a second bit number less than the first bit number.

4. The apparatus of claim 1, wherein the first plurality of count values ​​have a first quantity, and the second plurality of count values ​​have a second quantity, wherein the second quantity is less than the first quantity.

5. The apparatus of claim 1, further comprising a maximum value counting logic circuit for storing an address associated with the maximum value among the first plurality of count values.

6. The apparatus of claim 5, wherein the maximum value counting logic circuit is configured to compare the minimum value of the selected count values ​​among the first plurality of count values ​​with a stored count value, and if the minimum value exceeds the stored count value, store the minimum value and the row address, and wherein the second sketch circuit is further configured to update the selected count value among the second plurality of count values ​​based on the minimum value of the selected count values ​​among the first plurality of count values ​​that exceeds the stored count value in the maximum value counting logic circuit.

7. The apparatus of claim 5, wherein if the target refresh queue is empty, the address stored in the maximum value counting logic circuit is provided to the refresh address generator.

8. The apparatus of claim 1, further comprising: A first counting circuit is configured to update the selected count value among the first plurality of count values ​​by incrementing the selected count value among the first plurality of count values; and The second counting circuit is used to update the selected count value among the second plurality of count values ​​by setting the selected count value among the second plurality of count values ​​to the maximum value among the selected count value among the first plurality of count values ​​and the selected count value among the second plurality of count values.

9. An apparatus comprising: A first plurality of hash circuits are configured to receive a row address and provide each of a first plurality of hash values ​​based on the row address; A first storage structure includes a first plurality of count values, wherein a selected count value among the first plurality of count values ​​is changed in response to the first plurality of hash values, and wherein a command signal is activated based on a comparison of the selected count value among the first plurality of count values ​​with a first threshold. The second plurality of hash circuits are configured to receive the row address in response to the activation of the command signal, and to provide each of the second plurality of hash values ​​based on the row address; A second storage structure includes a second plurality of count values, wherein a selected count value among the second plurality of count values ​​is changed in response to the second plurality of hash values; An address queue is used to store the row address when the larger of the minimum value among the selected count values ​​in the first plurality of count values ​​and the minimum value among the selected count values ​​in the second plurality of count values ​​exceeds a second threshold.

10. The apparatus of claim 9, further comprising a comparison circuit for providing a second command signal when the larger of the minimum of the selected count values ​​among the first plurality of count values ​​and the minimum of the selected count values ​​among the second plurality of count values ​​exceeds the second threshold, and wherein the address queue is used to store the row address based on the second command signal.

11. The apparatus of claim 9, wherein the first plurality of count values ​​have a first quantity, and the second plurality of count values ​​have a second quantity, and wherein the second quantity is less than the first quantity.

12. The apparatus of claim 9, wherein the command signal is provided when the minimum of the selected count values ​​among the first plurality of count values ​​exceeds the first threshold.

13. The apparatus of claim 9, further comprising: A first counting circuit is configured to update the selected count value among the first plurality of count values ​​by incrementing the selected count value among the first plurality of count values; and The second counting circuit is used to update the selected count value among the second plurality of count values ​​by setting the selected count value among the second plurality of count values ​​to the maximum value among the selected count value among the first plurality of count values ​​and the selected count value among the second plurality of count values.

14. The apparatus of claim 13, further comprising a maximum value counting logic circuit for comparing the minimum value of the selected count values ​​among the first plurality of count values ​​with a stored count value, and storing the minimum value and the row address if the minimum value exceeds the stored count value, and wherein the second counting circuit is further configured to update the selected count value among the second plurality of count values ​​based on the minimum value of the selected count values ​​among the first plurality of count values ​​that exceeds the stored count value in the maximum value counting logic circuit.

15. The apparatus of claim 9, further comprising deletion logic circuitry for providing a first deletion signal or a second deletion signal, wherein in response to the first deletion signal, the minimum value of the selected count values ​​among the first plurality of count values ​​is set to an initial value, and wherein in response to the second deletion signal, the smaller of the minimum value among the first plurality of count values ​​and the minimum value among the second plurality of count values ​​is set to the initial value.

16. A method comprising: Receive line address; Hash the row address into a first plurality of hash values; Based on the first plurality of hash values, change a selected count value among the first plurality of count values; The selected count value among the first plurality of count values ​​is compared with a threshold; If the selected count value among the first plurality of count values ​​is greater than the threshold, the row address is hashed into a second plurality of hash values; Based on the second plurality of hash values, change the selected count value among the second plurality of count values; as well as If the minimum value among the selected count values ​​in the first plurality of count values ​​is not greater than the threshold, the row address is stored in the address queue based on the comparison result between the minimum value among the selected count values ​​in the first plurality of count values ​​and the second threshold.

17. The method of claim 16, further comprising: comparing the larger of the minimum of the selected count values ​​among the first plurality of count values ​​and the minimum of the selected count values ​​among the second plurality of count values ​​with a second threshold, wherein in response to the larger value exceeding the second threshold, the row address is stored in the address queue.

18. The method of claim 16, further comprising: The minimum value among the first plurality of count values ​​is compared with the stored count value; If the minimum value exceeds the stored count value, then the stored count value is replaced with the minimum value; If the minimum value exceeds the stored count value, then the row address is stored as the maximum row address.

19. The method of claim 18, further comprising: generating a refresh address based on the row address in the row address queue or the stored maximum row address.

20. The method of claim 16, further comprising: The selected count value among the first plurality of count values ​​is changed by incrementing the selected count value among the first plurality of count values; and The selected count value in the second plurality of count values ​​is changed by setting the selected count value in the second plurality of count values ​​to the maximum value of the selected count value in the first plurality of count values ​​and the selected count value in the second plurality of count values.

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