Semiconductor device, substrate, and method for manufacturing semiconductor device

Abstract

Provided are a semiconductor device, a substrate, and a manufacturing method of a semiconductor device, which enable a chip to be more appropriately connected to a substrate. A semiconductor device according to the present embodiment includes a substrate having a first surface, a second surface opposite to the first surface, a plurality of conductive connection portions provided on the first surface, and a plurality of columnar electrodes each extending from the plurality of conductive connection portions toward the second surface and having a tapered shape; and a semiconductor chip having a third surface opposite to the first surface and a plurality of connection bumps provided on the third surface and electrically connected to the plurality of conductive connection portions. The columnar electrode provided in a first region in a chip region on the first surface where the semiconductor chip is arranged has a tapered shape opposite to the columnar electrode provided in a second region in the chip region.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-192230 (filed on November 26, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] This embodiment relates to a semiconductor device, a substrate, and a method for manufacturing the semiconductor device. Background Technology

[0003] In the packaging structure of semiconductor devices, semiconductor chips are sometimes connected to the wiring substrate in a flip-chip manner. However, due to the warpage of the semiconductor chip, it can sometimes be difficult to properly connect the semiconductor chip to the wiring substrate. Summary of the Invention

[0004] Provides a semiconductor device, a substrate, and a method for manufacturing the semiconductor device that enables a chip to be more properly connected to a substrate.

[0005] The semiconductor device according to this embodiment includes: a substrate having a first surface, a second surface opposite to the first surface, a plurality of conductive connections disposed on the first surface, and a plurality of columnar electrodes, the plurality of columnar electrodes being configured to extend from the plurality of conductive connections toward the second surface and having a tapered shape; and a semiconductor chip having a third surface opposite to the first surface and a plurality of connecting bumps, the plurality of connecting bumps being disposed on the third surface and electrically connected to the plurality of conductive connections, wherein the columnar electrodes disposed in a first region of a chip region on the first surface where the semiconductor chip is disposed have a tapered shape in the opposite direction to the columnar electrodes disposed in a second region of the chip region. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0007] Figure 2 This is a cross-sectional view showing an example of the structure of the semiconductor chip and its surroundings according to the first embodiment.

[0008] Figure 3 This is a top view showing an example of the structure of the semiconductor device according to the first embodiment.

[0009] Figure 4 This is a diagram illustrating an example of the structure of the conductive connection portion and the columnar electrode according to the first embodiment.

[0010] Figure 5This is an enlarged cross-sectional view showing an example of the structure of the columnar electrode and conductive connection portion according to the first embodiment.

[0011] Figure 6A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0012] Figure 6B It continues Figure 6A The image shows a cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0013] Figure 6C It continues Figure 6B The image shows a cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0014] Figure 6D It continues Figure 6C The image shows a cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0015] Figure 6E It continues Figure 6D The image shows a cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0016] Figure 6F It continues Figure 6E The image shows a cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0017] Figure 6G It continues Figure 6F The image shows a cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0018] Figure 6H It continues Figure 6G The image shows a cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0019] Figure 6I It continues Figure 6H The image shows a cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0020] Figure 6J It continues Figure 6I The image shows a cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0021] Figure 7A This is a cross-sectional view of an example of the plating growth of a columnar electrode according to the first embodiment.

[0022] Figure 7B It continues Figure 7A The image shows a cross-sectional view of an example of the plating growth of a columnar electrode.

[0023] Figure 7C It continues Figure 7B The image shows a cross-sectional view of an example of the plating growth of a columnar electrode.

[0024] Figure 8 This is a cross-sectional view showing an example of the structure of the semiconductor chip and its surroundings involved in the first comparative example.

[0025] Figure 9 This is a top view showing an example of the structure of the semiconductor device according to the second embodiment.

[0026] Figure 10 This is a cross-sectional view showing an example of the structure of the semiconductor chip and its surroundings according to the third embodiment.

[0027] Figure 11 This is a top view showing an example of the structure of the semiconductor device according to the third embodiment.

[0028] Figure 12 This is a cross-sectional view showing an example of the structure of the semiconductor chip and its surroundings according to the fourth embodiment.

[0029] Figure 13 This is a top view showing an example of the structure of the semiconductor device according to the fourth embodiment.

[0030] Figure 14 This is a graph showing the relationship between the width of the columnar electrode and the thickness of the conductive connection.

[0031] Figure 15 This is a cross-sectional view showing an example of the structure of the semiconductor chip and its surroundings according to the fifth embodiment.

[0032] Label Explanation

[0033] 1 Semiconductor device, 10 Wiring substrate, 11 Wiring layer, 111 Conductive connection, 111a Conductive connection, 111b Conductive connection, 16 Pillar electrode, 16a Pillar electrode, 16b Pillar electrode, 20 Semiconductor chip, 21 Electrode pillar, F1 surface, F2 surface, F3 surface, H1 hole, H2 hole, 102L1 wiring layer, 103L2 wiring layer, 104L3 wiring layer, 105L4 wiring layer, R1 chip area, R11 area, R12 area, R13 area, R14 area, S-layer stack. Detailed Implementation

[0034] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the invention. In the following embodiments, the vertical direction of the wiring substrate refers to the relative direction when the surface on which the semiconductor chip is disposed is up, and may sometimes differ from the vertical direction following gravitational acceleration. The drawings are schematic or conceptual, and the proportions of the parts are not required to be identical to reality. In the specification and drawings, the same reference numerals are used for elements that have been described with respect to the preceding drawings, and detailed descriptions are omitted where appropriate.

[0035] (First Embodiment)

[0036] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a wiring substrate 10, semiconductor chips 20, 30-33, adhesive layers 40-43, spacers 50, adhesive layers 60, a metal material 70, a resin layer 80, bonding wires 90, and a sealing resin 91. The semiconductor device 1 is, for example, a package of NAND flash memory.

[0037] The wiring substrate 10 can be a printed circuit board or interposer that includes a wiring layer 11 and an insulating layer 15. For the wiring layer 11, a low-resistance metal such as copper (Cu), nickel (Ni), or an alloy thereof can be used. For the insulating layer 15, an insulating material such as glass epoxy resin can be used. In the accompanying drawings, the wiring layer 11 is provided only on the surface and back side of the insulating layer 15. However, the wiring substrate 10 may also have a multilayer wiring structure consisting of multiple wiring layers 11 and multiple insulating layers 15 stacked together. The wiring substrate 10 may also have a through electrode 12 (pillar electrode 16) extending through its surface and back side, for example, like an interposer.

[0038] A solder resist layer 14 is provided on the surface (surface F1) of the wiring substrate 10 and disposed on the wiring layer 11. The solder resist layer 14 is also used as an insulating layer to protect the wiring layer 11 from the influence of the metal material 70 and suppress short circuits.

[0039] A solder resist layer 14 is also provided on the back side (side F2) of the wiring substrate 10, which is provided on the wiring layer 11. Metal bumps 13 are provided on the wiring layer 11 exposed from the solder resist layer 14. The metal bumps 13 are provided for electrically connecting other components (not shown) to the wiring substrate 10.

[0040] The semiconductor chip 20 is, for example, a control chip that controls the memory chip. A semiconductor element (not shown) is disposed on the surface F3 of the semiconductor chip 20 facing the wiring substrate 10. The semiconductor element can be, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit that constitutes the controller. Electrode posts 21, electrically connected to the semiconductor element, are disposed on the back side (lower surface) of the semiconductor chip 20, on the surface F3. The electrode posts 21 can be made of, for example, a low-resistance metal material such as copper, nickel, or alloys thereof.

[0041] A metal material 70 is disposed around the electrode post 21, which serves as a connecting bump. The electrode post 21 is electrically connected to the wiring layer 11 exposed at the opening of the solder resist layer 14 via the metal material 70. For example, a low-resistance metal material such as solder, silver, or copper can be used for the metal material 70. The metal material 70 covers a portion of the wiring layer 11 of the wiring substrate 10 within the opening, and also covers a portion of the side surface of the electrode post 21 of the semiconductor chip 20. Thus, the metal material 70 electrically connects the electrode post 21 of the semiconductor chip 20 to the wiring layer 11 of the wiring substrate 10.

[0042] A resin layer 80 is provided in the area surrounding the metal material 70 and in the area between the semiconductor chip 20 and the wiring substrate 10. The resin layer 80 is, for example, a layer obtained by curing an underfill resin, and covers the area around the semiconductor chip 20 for protection.

[0043] Semiconductor chip 30 is, for example, a memory chip including NAND flash memory. Semiconductor chip 30 has semiconductor elements (not shown) on its surface (upper surface). These semiconductor elements can be, for example, a memory cell array and its peripheral circuitry (CMOS circuitry). The memory cell array can also be a three-dimensional memory cell array with multiple memory cells arranged in a three-dimensional manner. Furthermore, semiconductor chip 31 is bonded to semiconductor chip 30 via adhesive layer 41. Semiconductor chip 32 is bonded to semiconductor chip 31 via adhesive layer 42. Semiconductor chip 33 is bonded to semiconductor chip 32 via adhesive layer 43. Semiconductor chips 31-33 are, for example, memory chips including NAND flash memory, similar to semiconductor chip 30. Semiconductor chips 30-33 can also be the same type of memory chip. In the figure, in addition to semiconductor chip 20, which serves as a control chip, four semiconductor chips 30-33, which serve as memory chips, are stacked. However, the number of stacked semiconductor chips can be 3 or less, or 5 or more.

[0044] Spacer portion 50 is provided, for example, on the side of semiconductor chip 20. Spacer portion 50 is bonded to the surface (upper surface) of wiring substrate 10 via adhesive layer 60. Adhesive layer 60 is provided between wiring substrate 10 and spacer portion 50. Semiconductor chips 30 to 33 are disposed above spacer portion 50. The material of spacer portion 50 is, for example, silicon (Si) or polyimide.

[0045] Bonding lines 90 connect to any pads of the wiring substrate 10 and the semiconductor chips 30-33. For connection using bonding lines 90, the semiconductor chips 30-33 are stacked with offsets corresponding to the pads. Furthermore, the semiconductor chip 20 is connected via electrode posts 21 in a flip-chip manner; therefore, no wire bonding is performed. However, the semiconductor chip 20 can also be wire bonded based on the connection via electrode posts 21.

[0046] Furthermore, the sealing resin 91 seals the semiconductor chips 20, 30-33, adhesive layers 40-43, 60, spacer portion 50, bonding wire 90, etc. Thus, the semiconductor device 1 comprises multiple semiconductor chips 20, 30-33 forming a semiconductor package on the wiring substrate 10. When the resin layer 80 is absent, the sealing resin 91 can be used instead of the resin layer 80 to seal the area surrounding the metal material 70 and the area between the semiconductor chip 20 and the wiring substrate 10.

[0047] Next, the connection between the wiring substrate 10 and the semiconductor chip 20 will be described in detail.

[0048] Figure 2 This is a cross-sectional view showing an example of the structure of the semiconductor chip 20 and its surroundings according to the first embodiment. Furthermore, Figure 2 This is a cross-sectional view showing the timing of connecting the semiconductor chip 20 to the wiring substrate 10. The timing of connecting the wiring substrate 10 to the semiconductor chip 20 is, for example, a reflow process, which is the period during which the metal material 70 is heated to a temperature above the melting point.

[0049] The uppermost wiring layer 11, located on the F1 side, includes multiple conductive connections 111.

[0050] A conductive connection portion 111 is disposed on surface F1. The conductive connection portion 111 is disposed on chip region R1 on surface F1 where semiconductor chip 20 is disposed. At least a portion of the conductive connection portion 111 is exposed from solder resist layer 14. The conductive connection portion 111 electrically connects wiring substrate 10 and semiconductor chip 20 by contacting metal material 70. A plurality of electrode posts 21 disposed on surface F3 are electrically connected to the plurality of conductive connections 111 disposed on surface F1, respectively.

[0051] The conductive connection portion 111 includes a conductive connection portion 111a and a conductive connection portion 111b.

[0052] The conductive connection portion 111a is disposed in region R11 of the chip region R1. Region R11 is, for example, the central region of the chip.

[0053] The conductive connection portion 111b is disposed in region R12 within chip region R1. Region R12 is, for example, the outer periphery region of the chip.

[0054] Chip region R1 is, for example, divided into region R11 and region R12 outside of region R11. The area of ​​region R11, which is the central region of the chip, is, for example, less than half the chip size, while the area of ​​region R12, which is the outer peripheral region of the chip, is, for example, more than half the chip size (see reference). Figure 3 However, the area ratio is not limited to this and can be changed.

[0055] Here, Figure 2 The semiconductor chip 20 shown warps downwards during the reflow process. This warping of the semiconductor chip 20 is caused, for example, by the difference in the coefficients of thermal expansion between the semiconductor substrate material (e.g., silicon (Si)) and the metal of the semiconductor element. For example, the thinner the semiconductor chip 20 becomes in relation to the thinner package, the more prone it is to warping.

[0056] like Figure 2 As shown, the conductive connection portion 111b disposed in region R12 has a different thickness than the conductive connection portion 111a disposed in region R11. Therefore, even if the semiconductor chip 20 warps, the wiring substrate 10 can be connected to the semiconductor chip 20 more appropriately.

[0057] More specifically, the conductive connection portion 111b disposed in region R12 is thicker than the conductive connection portion 111a disposed in region R11. Therefore, even if the semiconductor chip 20 is warped into an under-convex shape, the wiring substrate 10 in region R12, which is the outer peripheral region of the chip, can be properly connected to the semiconductor chip 20.

[0058] Thus, the conductive connections 111a and 111b preferably have a thickness corresponding to the warping of the semiconductor chip 20 during the timing of their connection with the semiconductor chip 20. That is, it is preferable to vary the thickness of the conductive connections 111a and 111b to follow the warping of the semiconductor chip 20.

[0059] Furthermore, the difference between the thickness of the conductive connection portion 111b disposed in region R12 and the thickness of the conductive connection portion 111a disposed in region R11 preferably corresponds to the warpage of the semiconductor chip 20 during the timing of connection with the wiring substrate 10. The amount of warpage of the semiconductor chip 20 is, for example, the height difference between the center portion and the outer peripheral end of the semiconductor chip 20.

[0060] The difference in thickness between conductive connection portion 111a and conductive connection portion 111b is caused by the columnar electrode 16 extending from conductive connection portions 111a and 111b.

[0061] Multiple columnar electrodes 16 are configured to extend from multiple conductive connection portions 111 toward surface F2. Surface F2 is the surface of the wiring substrate 10 opposite to surface F1. The columnar electrodes 16 have a tapered shape.

[0062] The columnar electrode 16 includes columnar electrode 16a and columnar electrode 16b.

[0063] Viewed from the normal direction of surface F1, the pillar electrode 16a is disposed in region R11 of chip region R1. The pillar electrode 16a electrically connects L1 wiring layer 102 to any one of L2 wiring layer 103 to L4 wiring layer 105 (e.g., L2 wiring layer 103).

[0064] exist Figure 2 In the example shown, the columnar electrode 16a disposed in region R11 has a tapered shape in which the width (diameter) increases from face F1 toward face F2. The columnar electrode 16a (VIA) is an inverted via.

[0065] Viewed from the normal direction of surface F1, the pillar electrode 16b is disposed in region R12 of chip region R1. The pillar electrode 16b electrically connects L1 wiring layer 102 to any one of L2 wiring layer 103 to L4 wiring layer 105 (e.g., L2 wiring layer 103).

[0066] exist Figure 2 In the example shown, the columnar electrode 16b disposed in region R12 has a tapered shape whose width decreases from face F1 toward face F2. The columnar electrode 16b is a via (typically a via).

[0067] The columnar electrode 16a disposed in region R11 has a tapered shape in the opposite direction to that of the columnar electrode 16b disposed in region R12. That is, the columnar electrodes 16 extending from a plurality of conductive connection portions 111 connected to the semiconductor chip 20 in a flip-chip manner coexist in a mixed manner, including columnar electrodes 16b as conventional vias and columnar electrodes 16a as flip-chip vias. Furthermore, refer to the following... Figure 5 The relationship between the conductive connection 111 and the columnar electrode 16 will be explained in detail.

[0068] Figure 3 This is a top view showing an example of the structure of the semiconductor device 1 according to the first embodiment. Figure 3 The AA line represents the view as a cross-section. Figure 2 The corresponding cross section. Figure 3 Also for viewing from above the paper Figure 2A diagram showing the wiring substrate 10 and the semiconductor chip 20. Furthermore, in Figure 3 The image shows the periphery of the semiconductor chip 20 in the wiring substrate 10. Furthermore, the number and arrangement of conductive connections 111a and 111b are not limited to... Figure 3 The example shown.

[0069] exist Figure 3 middle, Figure 2 The area R12 shown is the area outside of area R11 in chip area R1.

[0070] exist Figure 3 In the example shown, solder resist layer 14 (SR) is provided on surface F1. Conductive connections 111a and 111b are partially exposed from solder resist layer 14. Figure 3 The conductive connection portions 111a and 111b shown are approximately circular in shape, but are not limited to this (see reference). Figure 4 ).

[0071] Next, the conductive connection portions 111a and 111b and the columnar electrodes 16a and 16b will be described in detail.

[0072] Figure 4 This is a diagram showing an example of the structure of the conductive connection portion 111 and the columnar electrode 16 according to the first embodiment. Figure 4 The top view and cross-sectional view show the conductive connection 111 and the columnar electrode 16.

[0073] The conductive connection portion 111 has, for example, a pad shape. Figure 4 The conductive connection portion 111 shown in the top view is generally elliptical in shape, but it can also be rectangular or generally circular, etc. The upper surface of the conductive connection portion 111 is exposed from the solder resist layer 14.

[0074] like Figure 4 As shown in the top view, the conductive connection portion 111 is configured to overlap with the columnar electrode 16 when viewed from the normal direction of surface F1. Figure 4 As shown in the cross-sectional view, the columnar electrode 16 is configured to extend from the conductive connection 111 toward the surface F2. The conductive connection 111 and the columnar electrode 16 have, for example, a pad-on-via configuration.

[0075] Figure 5 This is an enlarged cross-sectional view showing an example of the structure of the columnar electrodes 16a, 16b and the conductive connection portions 111a, 111b according to the first embodiment.

[0076] The conductive connection portion 111b connected to the columnar electrode 16b, which is a normal via, is thicker than the conductive connection portion 111a connected to the columnar electrode 16a, which is a reverse via. Figure 5In the example shown, the upper surface of the conductive connection 111a disposed in region R11 has a generally flat shape. The upper surface of the conductive connection 111b disposed in region R12 has a convex shape (protrusion). The pad height (thickness) of the conductive connection 111b is correspondingly higher than the pad height of the conductive connection 111a due to the convex shape. Furthermore, refer to the following... Figures 7A to 7C The differences between conductive connection portion 111a and conductive connection portion 111b are explained in detail.

[0077] Next, the manufacturing method of semiconductor device 1 will be described.

[0078] Figures 6A to 6J This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device 1 according to the first embodiment.

[0079] First, such as Figure 6A As shown, a dummy core 100 is prepared. The dummy core 100 has a support substrate 101 and an L1 wiring layer 102. The support substrate 101 is provided, for example, to facilitate the transport of the wiring substrate 10 by improving mechanical strength. A temporary adhesive layer (not shown) is provided between the L1 wiring layer 102 and the support substrate 101.

[0080] Next, as Figure 6B As shown, an insulating layer 151 and an L2 wiring layer 103 are formed on the dummy core 100. Thus, a laminate S is formed in which the L1 wiring layer 102 and the L2 wiring layer 103 are stacked in a manner that sandwiches the insulating layer 151 (e.g., prepreg, PP). More specifically, the laminate S is stacked on the support substrate 101 such that the L1 wiring layer 102 is in contact with the support substrate 101.

[0081] Next, as Figure 6C As shown, a hole H1 is formed in region R13 on the laminate S. Region R13 and Figure 2 and Figure 3 The area R11 shown corresponds to this. Hole H1 is formed to penetrate the L2 wiring layer 103 and the insulating layer 151 from the L2 wiring layer 103 side to reach the L1 wiring layer 102.

[0082] The aperture H1 is formed, for example, by laser or the like. Thus, the aperture H1 has a tapered shape in which the width decreases from the L2 wiring layer 103 toward the L1 wiring layer 102.

[0083] Next, as Figure 6D As shown, a columnar electrode 16a is formed within the hole H1. The columnar electrode 16a is formed, for example, by plating. Corresponding to the shape of the hole H1, the columnar electrode 16a has a tapered shape in which the width decreases from the L2 wiring layer 103 toward the L1 wiring layer 102.

[0084] Next, as Figure 6E As shown, a circuit (wiring) is formed on the L2 wiring layer 103. The circuit is formed, for example, by etching a mask.

[0085] Next, as Figure 6F As shown, L3 wiring layer 104, L4 wiring layer 105, and insulating layers 152 and 153 are stacked. First, for example, insulating layer 152 and L3 wiring layer 104 are stacked on L2 wiring layer 103. Next, a hole is formed that penetrates L3 wiring layer 104 and insulating layer 152 to reach L2 wiring layer 103. Next, a pillar electrode 16 is formed in the hole. Next, a circuit is formed on L3 wiring layer 104. Next, insulating layer 153 and L4 wiring layer 105 are formed. In this way, wiring substrate 10 is formed, which is a four-layer substrate having four layers of L1 wiring layer 102 to L4 wiring layer 105 and three layers of insulating layers 151 to 153.

[0086] Insulation layers 151-153 and Figure 2 The insulating layer 15 is shown. Insulating layer 151 is disposed between L1 wiring layer 102 and L2 wiring layer 103. Insulating layer 152 is disposed between L2 wiring layer 103 and L3 wiring layer 104. Insulating layer 153 is disposed between L3 wiring layer 104 and L4 wiring layer 105.

[0087] In addition, Figure 6F Alternatively, a stacked body including an L3 wiring layer 104 with pre-formed circuitry can be stacked on the L2 wiring layer 103 to form a [structure / structure]. Figure 6F The wiring substrate 10 shown.

[0088] Next, as Figure 6G As shown, the support substrate 101, including the temporary adhesive, is peeled off from the L1 wiring layer 102. Furthermore, Figure 6G The wiring substrate 10 shown is located at the top and bottom. Figure 6F The wiring substrate 10 shown is reversed. Therefore, Figure 6G The outermost wiring layer shown is L1 wiring layer 102.

[0089] Next, as Figure 6H As shown, a hole H2 is formed in region R14 on the laminate S, which is different from region R13. Region R14 and Figure 2 The area R12 shown corresponds to this. The hole H2 is formed to penetrate the L1 wiring layer 102 and the insulating layer 151 from the L1 wiring layer 102 side to reach the L2 wiring layer 103.

[0090] Hole H2 is formed, for example, by means of laser or the like, in the same manner as hole H1. Thus, hole H2 has a tapered shape in which the width decreases from the L1 wiring layer 102 toward the L2 wiring layer 103.

[0091] Next, as Figure 6I As shown, a hole H3 is formed. The hole H3 is formed to penetrate the L4 wiring layer 105 and the insulating layer 153 from the L4 wiring layer 105 side to reach the L3 wiring layer 104.

[0092] The hole H3 is formed, for example, by laser or the like. Thus, the hole H3 has a tapered shape in which the width decreases from the L4 wiring layer 105 toward the L3 wiring layer 104.

[0093] Next, as Figure 6J As shown, columnar electrodes 16b and 16a are formed in holes H2 and H3, respectively. Conductive connection portions 111a connected to columnar electrode 16a and 111b connected to columnar electrode 16b are formed in the L1 wiring layer 102. Furthermore, a solder resist layer 14 is formed by patterning a circuit in the L1 wiring layer 102.

[0094] exist Figure 6J In the process, the columnar electrodes 16 and 16b are formed in parallel (simultaneously), for example, by plating. The columnar electrode 16b has a tapered shape, corresponding to the shape of the hole H2, with its width decreasing from the L1 wiring layer 102 towards the L2 wiring layer 103. The columnar electrode 16 has a tapered shape, corresponding to the shape of the hole H3, with its width decreasing from the L4 wiring layer 105 towards the L3 wiring layer 104.

[0095] Here, as Figure 6C As shown, via H1 is formed from L2 wiring layer 103 toward L1 wiring layer 102. Figure 6I As shown, hole H2 is formed from L1 wiring layer 102 toward L2 wiring layer 103. That is, holes H1 and H2 are formed from opposite directions and have conical shapes in opposite directions. Thus, columnar electrodes 16a and 16b have conical shapes in opposite directions. Furthermore, the conical shape of the columnar electrodes 16 that are not connected to the conductive connections 111a and 111b, i.e., the columnar electrodes 16 disposed in the insulating layers 152 and 153, can also be in any direction.

[0096] Next, a semiconductor chip 20 is disposed on a wiring substrate 10 having a laminate S in such a way that it is electrically connected to conductive connection portions 111a and 111b. Then, for example, by forming a resin layer 80, semiconductor chips 30-33 are disposed, bonding lines 90 and sealing resin 91 are formed, thereby completing the process. Figure 1 Semiconductor device 1 is shown.

[0097] Next, the differences in pad height and upper surface shape between conductive connection portion 111a and conductive connection portion 111b will be explained.

[0098] Figures 7A to 7CThis is a cross-sectional view showing an example of the plating growth of the columnar electrode 16b according to the first embodiment. Figures 7A to 7C For example, it means Figure 6J The columnar electrode 16b is deposited and grown. For example... Figure 6J As shown, the columnar electrode 16b grows from the L2 wiring layer 103 toward the L1 wiring layer 102 within the hole H2.

[0099] The plating solution contains, for example, an inhibitor 201 and an accelerator 202. Inhibitor 201 inhibits plating growth. Accelerator 202 promotes plating growth. Inhibitor 201 and accelerator 202 are adsorbed onto the wiring substrate 10 immersed in the plating solution. Inhibitor 201 is readily adsorbed onto the surface. Accelerator 202 is adsorbed substantially uniformly throughout the substrate.

[0100] like Figure 7A As shown, inhibitor 201 readily adsorbs onto the surface of insulating layer 151 or seed layer, but is difficult to adsorb into pore H2. On the other hand, promoter 202 is also uniformly adsorbed onto the inclined surface of pore H2. Therefore, the density of promoter 202 inside pore H2 becomes higher than the density of promoter on the surface of L1 wiring layer 102.

[0101] like Figure 7B As shown, plating growth preferentially occurs within the via H2 compared to the L1 wiring layer 102. This is because, based on the aforementioned positional relationship between the inhibitor 201 and the promoter 202, plating growth inside the via H2 is faster than plating growth on the surface of the L1 wiring layer 102. Furthermore, the more the plating growth progresses, the higher the bottom of the via H2 becomes, and the higher the density of the promoter 202 at the bottom of the via H2. Consequently, plating growth inside the via H2 is further accelerated.

[0102] As the plating growth further develops, such as Figure 7C As shown, the columnar electrode 16 inside the hole H2 grows to a height exceeding that of the L1 wiring layer 102. Therefore, as referenced... Figure 5 As explained, the upper surface of the conductive connection portion 111b has a convex shape.

[0103] Furthermore, the direction of plating growth of the columnar electrode 16a is opposite to the direction of plating growth of the columnar electrode 16b. That is, as... Figure 6D As shown, the columnar electrode 16a is formed by plating growth from the L1 wiring layer 102 toward the L2 wiring layer 103. Therefore, Figure 5 The upper surface of the conductive connection portion 111a shown is not convex, but rather generally flat.

[0104] As described above, according to the first embodiment, when viewed from the normal direction of surface F1, the columnar electrode 16a disposed in region R11 has a conical shape in the opposite direction to that of the columnar electrode 16b disposed in region R12. That is, the hole H1 embedded in the columnar electrode 16a and the hole H2 embedded in the columnar electrode 16b are formed from different directions. As a result, the shapes of the upper surfaces are different between the conductive connection portion 111a and the conductive connection portion 111b. That is, the thickness of the conductive connection portion 111 varies accordingly with the position of the wiring substrate 10. As a result, even if the semiconductor chip 20 warps, the semiconductor chip 20 can be more properly connected to the wiring substrate 10.

[0105] Furthermore, the number of wiring layers 11 in the wiring substrate 10 is not limited to four layers; two or more layers are acceptable. That is, the wiring substrate 10 includes at least two L1 wiring layers 102 and L2 wiring layers 103. The conical electrodes 16a and 16b, with their tapered shapes facing opposite directions, are disposed on the same insulating layer 151.

[0106] In addition, the thickness of the conductive connecting parts 111a and 111b can also be set as the height of the upper surface.

[0107] Alternatively, it can be omitted. Figure 6D The formation of the columnar electrode 16a in the process shown is in Figure 6J In the process shown, columnar electrodes 16, 16a, and 16b are formed in parallel.

[0108] Next, as a first comparative example, the case where the taper direction of the cylindrical electrode 16 is exactly the same will be described.

[0109] Figure 8 This is a cross-sectional view showing an example of the structure of the semiconductor chip 20 and its surroundings involved in the first comparative example. Furthermore, Figure 8 This is a cross-sectional view showing the timing of connecting the semiconductor chip 20 to the wiring substrate 10.

[0110] The columnar electrode 16 connected to the conductive connection portion 111 is, for example, a typical via. In this case, the height of the upper surface of all conductive connections 111 is approximately the same. Therefore, due to the warping of the semiconductor chip 20, the connection between the semiconductor chip 20 and the wiring substrate 10 may become difficult.

[0111] In contrast, in the first embodiment, columnar electrodes 16a and 16b with different conical shapes are mixed together, and the conductive connection portions 111a and 111b have different thicknesses. As a result, the semiconductor chip 20 can be more appropriately connected to the wiring substrate 10.

[0112] In addition, as a second comparative example, the case of a pad structure with multiple conductive connection portions 111 will be described.

[0113] As a pad structure other than the via pad structure, the conductive connection portion 111 is sometimes led out through the wiring in the L1 wiring layer 102 and is disposed in a position away from the columnar electrode 16 when viewed from above. In addition, the conductive connection portion 111 is sometimes exposed from the solder resist layer 14 and has a wiring shape.

[0114] In the case of a pad structure containing multiple conductive connections 111, the pad height of the conductive connections 111 may vary depending on their position on surface F1. If the conductive connections 111 in region R12, which is the outer periphery of the chip, have a pad structure with a low pad height, the connectivity may be easily reduced due to warping of the semiconductor chip 20.

[0115] In contrast, in the first embodiment, all conductive connections 111a and 111b have the same via-pad structure. This suppresses thickness variations in the conductive connections 111a and 111b, thereby increasing the connection margin against warping of the semiconductor chip 20. Consequently, the connectivity between the semiconductor chip 20 and the wiring substrate 10 is improved.

[0116] (Second Implementation)

[0117] Figure 9 This is a top view showing an example of the structure of the semiconductor device 1 according to the second embodiment. Compared with the first embodiment, the positions of region R11 and region R12 are different in the second embodiment. Figure 9 The BB line represents the view as a sectional view. Figure 2 The corresponding cross section.

[0118] Region R12 is, for example, a corner region of the chip. The corner region of the chip corresponds to the region including the four corners of the semiconductor chip 20. Region R11 is the region in chip region R1 other than the corner region of the chip.

[0119] exist Figure 9 The semiconductor chip 20 shown is prone to significant warping along its diagonal. Therefore, the region R12 where the relatively thick conductive connection portion 111b is located can also be a corner region of the chip where connectivity is easily degraded.

[0120] As in the second embodiment, the positions of regions R11 and R12 can also be changed.

[0121] The semiconductor device 1 according to the second embodiment can achieve the same effect as the first embodiment.

[0122] (Third Implementation)

[0123] Figure 10This is a cross-sectional view showing an example of the structure of the semiconductor chip 20 and its surroundings according to the third embodiment. Figure 11 This is a top view showing an example of the structure of the semiconductor device 1 according to the third embodiment. The difference between the third embodiment and the first embodiment is that the positions of region R11 and region R12 are opposite. Figure 11 The CC line is indicated by the cross-sectional view. Figure 10 The corresponding cross section.

[0124] exist Figure 10 and Figure 11 In the example shown, region R12 is, for example, the central region of the chip. Region R11 is, for example, the outer peripheral region of the chip. Therefore, the conductive connection portion 111b disposed in region R12, which is the central region of the chip, is thicker than the conductive connection portion 111a disposed in region R11, which is the outer peripheral region of the chip. As a result, for example, when connecting the semiconductor chip 20 to the wiring substrate 10, if the semiconductor chip 20 is warped into an upward convex shape, the semiconductor chip 20 can be connected to the wiring substrate 10 more appropriately.

[0125] As in the third embodiment, the positions of region R11 and region R12 can also be opposite.

[0126] The semiconductor device 1 according to the third embodiment can achieve the same effect as the first embodiment.

[0127] (Fourth implementation)

[0128] Figure 12 This is a cross-sectional view showing an example of the structure of the semiconductor chip 20 and its surroundings according to the fourth embodiment. Figure 13 This is a top view showing an example of the structure of the semiconductor device 1 according to the fourth embodiment. The difference between the fourth embodiment and the first embodiment is that the thickness of the conductive connection portion 111 is controlled according to the width of the columnar electrode 16. Figure 13 The DD line represents the section view. Figure 12 The corresponding cross section.

[0129] Regions R11 and R12 are arranged in a direction parallel to surface F1. Figure 13 In the example shown, region R11 is positioned to the left of chip region R1. Region R12 is positioned to the right of chip region R1. Therefore, in Figure 13 The thickness variation of conductive connecting parts 111a and 111b in the left-right direction of the paper surface.

[0130] like Figure 12As shown, in region R12, the width of the columnar electrode 16b, which serves as a typical via, and the thickness of the conductive connection portion 111b are not uniform. The width of the columnar electrode 16b gradually (gradually) increases with distance from region R11. The thickness of the conductive connection portion 111b gradually increases with distance from region R11.

[0131] Figure 14 This is a diagram showing the relationship between the width of the columnar electrode 16b and the thickness of the conductive connection portion 111b.

[0132] like Figure 14 As shown, the larger the width (via diameter) of the columnar electrode 16b, the thicker the conductive connection portion 111b. Conversely, the smaller the width of the columnar electrode 16b, the thinner the conductive connection portion 111b. This is because: the larger the width of the columnar electrode 16b, the thinner the conductive connection portion 111b. Figure 7B The higher the density of the promoter 202 in the bottom of the hole H2 shown, the faster the plating growth rate can be varied by changing the width of the hole H2. As a result, the thickness of the convex portion of the conductive connection 111b, i.e., the thickness of the conductive connection 111b, can be controlled in the columnar electrode 16b, which is a typical via. Therefore, the thickness of the conductive connections 111a and 111b can be adjusted according to the warpage of the semiconductor chip 20. As a result, the semiconductor chip 20 can be more easily connected to the wiring substrate 10.

[0133] That is, the conductive connection portion 111b has a thickness corresponding to the width of the columnar electrode 16b, which has a tapered shape in which the width decreases from surface F1 toward surface F2. More specifically, the wider the columnar electrode 16b with the tapered shape in which the width decreases from surface F1 toward surface F2, the thicker the conductive connection portion 111b becomes.

[0134] In addition, such as Figure 12 As shown, the thickness of the conductive connections 111a and 111b gradually changes from region R11 to region R12. That is, the thickness of the conductive connections 111a and 111b does not change drastically at the boundary between region R11 and region R12, but changes gradually.

[0135] As in the fourth embodiment, the thickness of the conductive connection portion 111 can also be controlled according to the width of the columnar electrode 16.

[0136] The semiconductor device 1 according to the fourth embodiment can achieve the same effects as the first embodiment. Furthermore, for example, in the first embodiment, the thickness of the conductive connections 111a and 111b can gradually change from the center of the chip to the outer periphery. More specifically, Figure 2The conductive connection portion 111b shown may also gradually thicken from the center of the chip to the outer periphery. In this case, the width of the columnar electrode 16b gradually increases from the center of the chip to the outer periphery.

[0137] (Fifth Implementation)

[0138] Figure 15 This is a cross-sectional view showing an example of the structure of the semiconductor chip 20 and its surroundings according to the fifth embodiment. The fifth embodiment differs from the first embodiment in that the tapered shapes of the columnar electrodes 16a and 16b are opposite.

[0139] exist Figure 15 In the example shown, the columnar electrode 16a disposed in region R11 has a tapered shape whose width decreases from face F1 toward face F2. The columnar electrode 16a is a typical via.

[0140] exist Figure 15 In the example shown, the columnar electrode 16b disposed in region R12 has a tapered shape whose width increases from face F1 toward face F2. The columnar electrode 16b is an inverted via.

[0141] Furthermore, in the fifth embodiment, Figure 15 The upper surface of the conductive connection portion 111a disposed in region R11 is generally flat. The upper surface of the conductive connection portion 111b disposed in region R12 is convex.

[0142] Similar to the first embodiment, the conductive connection portion 111b disposed in region R12 is thicker than the conductive connection portion 111a disposed in region R11. Therefore, in Figure 15 In the example shown, the conductive connection portion 111b connected to the columnar electrode 16b, which is a reverse via, is thicker than the conductive connection portion 111a connected to the columnar electrode 16a, which is a normal via. Thus, in the fifth embodiment, the relationship between the tapered shape of the columnar electrodes 16a and 16b and the thickness of the conductive connections 111a and 111b is reversed compared to the first embodiment.

[0143] Depending on the plating composition or the plating solution used in forming the columnar electrodes 16a and 16b, the thickness tendency of the conductive connections 111a and 111b may sometimes vary. For example, when the ratio or composition of the inhibitor 201 and the promoter 202 changes, even under the same plating conditions, the columnar electrode 16b, as a reverse via, may grow faster than the columnar electrode 16a, as a normal via. Furthermore, the columnar electrodes 16a and 16b may be formed simultaneously. Alternatively, they may be formed together... Figures 6C to 6D Correspondingly, one of the columnar electrodes 16a and 16b is formed first, such as with Figures 6H to 6JThe other party forms columnar electrodes 16a and 16b in the same manner. When forming one of the columnar electrodes 16a and 16b first, the plating conditions such as the plating solution used can also be different.

[0144] As in the fifth embodiment, the conical shapes of the columnar electrode 16a and columnar electrode 16b can also be opposite.

[0145] The semiconductor device 1 according to the fifth embodiment can achieve the same effect as the first embodiment.

[0146] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and likewise within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: A substrate having a first surface, a second surface opposite to the first surface, a plurality of conductive connections disposed on the first surface, and a plurality of columnar electrodes, wherein the plurality of columnar electrodes are respectively configured to extend from the plurality of conductive connections toward the second surface and have a tapered shape; and A semiconductor chip has a third surface opposite to the first surface and a plurality of connecting bumps, the plurality of connecting bumps being disposed on the third surface and electrically connected to a plurality of conductive connecting portions, respectively. The columnar electrode disposed in a first region of the chip region on the first surface for which the semiconductor chip is disposed has a tapered shape in the opposite direction to the columnar electrode disposed in the second region of the chip region. The upper surface of the conductive connection portion disposed in the first region has a flat shape. The upper surface of the conductive connection portion disposed in the second region has a convex shape.

2. A semiconductor device comprising: A substrate having a first surface, a second surface opposite to the first surface, a plurality of conductive connections disposed on the first surface, and a plurality of columnar electrodes, wherein the plurality of columnar electrodes are respectively configured to extend from the plurality of conductive connections toward the second surface and have a tapered shape; and A semiconductor chip has a third surface opposite to the first surface and a plurality of connecting bumps, the plurality of connecting bumps being disposed on the third surface and electrically connected to a plurality of conductive connecting portions, respectively. The columnar electrode disposed in a first region of the chip region on the first surface for which the semiconductor chip is disposed has a tapered shape in the opposite direction to the columnar electrode disposed in the second region of the chip region. The conductive connection portion disposed in the second region has a different thickness than the conductive connection portion disposed in the first region.

3. The semiconductor device according to claim 2, The conductive connection portion disposed in the second region is thicker than the conductive connection portion disposed in the first region.

4. A semiconductor device comprising: A substrate having a first surface, a second surface opposite to the first surface, a plurality of conductive connections disposed on the first surface, and a plurality of columnar electrodes, wherein the plurality of columnar electrodes are respectively configured to extend from the plurality of conductive connections toward the second surface and have a tapered shape; and A semiconductor chip has a third surface opposite to the first surface and a plurality of connecting bumps, the plurality of connecting bumps being disposed on the third surface and electrically connected to a plurality of conductive connecting portions, respectively. The columnar electrode disposed in a first region of the chip region on the first surface for which the semiconductor chip is disposed has a tapered shape in the opposite direction to the columnar electrode disposed in the second region of the chip region. The thickness of the conductive connection varies from the first region toward the second region.

5. The semiconductor device according to any one of claims 1 to 4, The conductive connection portion has a thickness corresponding to the width of the columnar electrode, which has a tapered shape with a width that decreases from the first surface toward the second surface.

6. The semiconductor device according to any one of claims 1 to 4, The columnar electrode disposed in the first region has a tapered shape in which the width increases from the first surface toward the second surface. The columnar electrode disposed in the second region has a tapered shape in which the width decreases from the first surface toward the second surface.

7. The semiconductor device according to any one of claims 1 to 4, The columnar electrode disposed in the first region has a tapered shape in which the width decreases from the first surface toward the second surface. The columnar electrode disposed in the second region has a tapered shape in which the width increases from the first surface toward the second surface.

8. The semiconductor device according to any one of claims 1 to 4, The first region is the central region of the chip. The second region is the outer periphery of the chip.

9. The semiconductor device according to any one of claims 1 to 4, The second region is the corner region of the chip. The first region is the region outside the corner region of the chip in the chip region.

10. The semiconductor device according to any one of claims 1 to 4, The first region is the outer periphery of the chip. The second region is the central region of the chip.

11. The semiconductor device according to any one of claims 1 to 4, The first region and the second region are arranged in a direction parallel to the first surface.

12. A substrate comprising: Page 1; The second surface, opposite to the first surface; Multiple conductive connection portions are provided on the first surface; and Multiple columnar electrodes are configured to extend from the multiple conductive connections toward the second surface, and have a tapered shape. The columnar electrode disposed in a first region of the chip region on the first surface for which the semiconductor chip is disposed has a tapered shape in the opposite direction to the columnar electrode disposed in the second region of the chip region. The upper surface of the conductive connection portion disposed in the first region has a flat shape. The upper surface of the conductive connection portion disposed in the second region has a convex shape.

13. A substrate comprising: Page 1; The second surface, opposite to the first surface; Multiple conductive connection portions are provided on the first surface; and Multiple columnar electrodes are configured to extend from the multiple conductive connections toward the second surface, and have a tapered shape. The columnar electrode disposed in a first region of the chip region on the first surface for which the semiconductor chip is disposed has a tapered shape in the opposite direction to the columnar electrode disposed in the second region of the chip region. The conductive connection portion disposed in the second region has a different thickness than the conductive connection portion disposed in the first region.

14. A substrate comprising: Page 1; The second surface, opposite to the first surface; Multiple conductive connection portions are provided on the first surface; and Multiple columnar electrodes are configured to extend from the multiple conductive connections toward the second surface, and have a tapered shape. The columnar electrode disposed in a first region of the chip region on the first surface for which the semiconductor chip is disposed has a tapered shape in the opposite direction to the columnar electrode disposed in the second region of the chip region. The thickness of the conductive connection varies from the first region toward the second region.

15. A method for manufacturing a semiconductor device, comprising: For a laminate in which the first wiring layer and the second wiring layer are stacked with an insulating layer sandwiched between them, A first hole is formed in a third region on the laminate as viewed along the stacking direction, penetrating the insulating layer from the second wiring layer side to the first wiring layer. A second hole, different from the third region, is formed in a fourth region on the stack, viewed along the stacking direction, penetrating the insulating layer from the first wiring layer side to the second wiring layer. The first hole has a tapered shape in which the width decreases from the second wiring layer toward the first wiring layer. The second hole has a tapered shape in which the width decreases from the first wiring layer toward the second wiring layer.

Images