Semiconductor structure and method of manufacturing the same

Abstract

The present application is a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a dielectric layer, a bonding layer, a ground metal layer and a plurality of circuit layers. The dielectric layer is disposed on a surface of the substrate, a plurality of openings of the dielectric layer expose the surface, the bonding layer is disposed on the dielectric layer, a first bonding part of the bonding layer is located in the openings and connects the surface, a second bonding part of the bonding layer connects the dielectric layer, a first ground layer of the ground metal layer connects the first bonding part of the bonding layer, a second ground layer of the ground metal layer connects the second bonding part of the bonding layer, each of the circuit layers is disposed on the second bonding part of the bonding layer, and the second ground layer is arranged between two adjacent circuit layers.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a grounded metal layer and a method for manufacturing the same. Background Technology

[0002] Please see Figure 1 and Figure 2 The image shows cross-sectional views of a conventional semiconductor structure 200 from different perspectives. The semiconductor structure 200 has a substrate 210, a plurality of conductive pads 220, a first dielectric layer 230, a first bonding layer 240, a first circuit layer 250, a ground metal layer 260, a second dielectric layer 270, a second bonding layer 280, and a second circuit layer 290. The conductive pads 220 are located on the surface 211 of the substrate 210. The first dielectric layer 230 is disposed on the surface 211 of the substrate 210 and has a plurality of openings 231. Some of the openings 231 expose each of the conductive pads 220, and some of the openings 231 expose the surface 211 of the substrate 210. The first bonding layer 240 is disposed in the opening 231. The first bonding portion 241 of the first bonding layer 240 is located in the opening 231 and connects to each of the conductive pads 220. The second bonding portion 242 of the first bonding layer 240 is located in the opening 231 and connects to the surface 211 of the substrate 210. The first circuit layer 250 is connected to the first bonding portion 241, and the ground metal layer 260 is connected to the second bonding portion 242. The ground metal layer 260 is disposed in the center of the semiconductor structure 200 to block electromagnetic interference. Since the two conductive pads 220 need to transmit current signals, but are blocked by the ground metal layer 260, the second dielectric layer 270 must cover the ground metal layer 260 so that the second bonding layer 280 and the second circuit layer 290 are disposed on the second dielectric layer 270 without contacting the ground metal layer 260. This makes the semiconductor structure 200 a 2P2M (2-Poly 2-Metal) structure, resulting in a more complex manufacturing process and an increased overall size. Summary of the Invention

[0003] The main objective of this invention is to divide the grounding metal layer into a first metal layer and a second metal layer, so that the circuit layer can pass through the second metal layer without the need to set up a dielectric layer to cover the grounding metal layer, thus achieving a 1P2M structure.

[0004] A semiconductor structure according to the present invention includes a substrate, a dielectric layer, a bonding layer, a ground metal layer, and a plurality of circuit layers. The substrate has a surface, the dielectric layer is disposed on the surface, the dielectric layer has a plurality of openings, each opening exposing the surface, the bonding layer is disposed on the dielectric layer, a first bonding portion of the bonding layer is located in the opening and the first bonding portion is connected to the surface, a second bonding portion of the bonding layer is connected to the dielectric layer, the ground metal layer is disposed on the bonding layer, a first ground layer of the ground metal layer is connected to the first bonding portion of the bonding layer, a second ground layer of the ground metal layer is connected to the second bonding portion of the bonding layer, each circuit layer is disposed on the second bonding portion of the bonding layer, and a second ground layer is provided between two adjacent circuit layers.

[0005] Preferably, the dielectric layer, the first junction and the first ground layer are located at the same first horizontal height, and the second junction, the second ground layer and the line layer are located at the same second horizontal height, which is higher than the first horizontal height.

[0006] Preferably, the substrate has a plurality of conductive pads disposed on the surface of the substrate, the opening of the dielectric layer exposes each of the conductive pads, and the bonding layer connects the conductive pads through the opening, so that each of the circuit layers connects each of the conductive pads through the bonding layer.

[0007] Preferably, the first grounding layer is connected to the second grounding layer via the bonding layer.

[0008] Preferably, the grounding metal layer does not carry any current signal.

[0009] A method of manufacturing a semiconductor structure includes: providing a substrate having a surface; forming a dielectric layer on the surface of the substrate, the dielectric layer having a plurality of openings exposing the surface; forming a bonding layer on the dielectric layer, wherein a portion of the bonding layer is located in the openings and connects to the surface, and a portion of the bonding layer is connected to the dielectric layer; forming a patterned photoresist layer on the bonding layer, the patterned photoresist layer having a plurality of openings exposing the bonding layer; forming a metal layer in the openings of the patterned photoresist layer, the metal layer connecting to the bonding layer exposed by the openings, and a portion of the metal layer being located in the openings of the dielectric layer; and peeling off the patterned photoresist layer. A photoresist layer is used to expose the bonding layer covered by the patterned photoresist layer; and the bonding layer is etched with the metal layer as a mask to form a first bonding portion and a second bonding portion, the first bonding portion being located in the opening and connected to the surface, the second bonding portion being connected to the dielectric layer, wherein the metal layer includes a ground metal layer and a plurality of line layers, the first ground layer of the ground metal layer is connected to the first bonding portion of the bonding layer, the second ground layer of the ground metal layer is connected to the second bonding portion of the bonding layer, each of the line layers is disposed on the second bonding portion of the bonding layer, and a second ground layer is provided between two adjacent line layers.

[0010] Preferably, the dielectric layer, the first junction and the first ground layer are located at the same first horizontal height, and the second junction, the second ground layer and the line layer are located at the same second horizontal height, which is higher than the first horizontal height.

[0011] Preferably, the substrate has a plurality of conductive pads disposed on the surface of the substrate, the opening of the dielectric layer exposes each of the conductive pads, and the bonding layer connects the conductive pads through the opening, so that each of the circuit layers connects each of the conductive pads through the bonding layer.

[0012] Preferably, the first grounding layer is connected to the second grounding layer via the bonding layer.

[0013] Preferably, the grounding metal layer does not carry any current signal.

[0014] This invention divides the ground metal layer of the semiconductor structure into a first ground layer and a second ground layer, allowing the circuit layers to be directly disposed on the dielectric layer, thus achieving a 1P2M structure, reducing process complexity and the size of the semiconductor structure. Furthermore, since the second ground layer is also disposed on the dielectric layer, it can shield the electromagnetic interference between the circuit layers, thereby improving the electromagnetic shielding capability of the semiconductor structure. Attached Figure Description

[0015] Figure 1 : A cross-sectional view of a known semiconductor structure.

[0016] Figure 2 : A cross-sectional view of the existing known semiconductor structure.

[0017] Figure 3 According to an embodiment of the present invention, a top view of a semiconductor structure is provided.

[0018] Figure 4 : Figure 3 A cross-sectional view of line segment AA.

[0019] Figure 5 : Figure 3 A cross-sectional view of line segment BB.

[0020] Figure 6 According to an embodiment of the present invention, a flowchart of a method for manufacturing a semiconductor structure is provided.

[0021] Figures 7A-7G : Figure 3 The AA line segment is a cross-sectional view of each step in the manufacturing process of this semiconductor structure.

[0022] Figures 8A-8G : Figure 3 The BB line segment is a cross-sectional view of each step in the manufacturing process of the semiconductor structure.

[0023] [Explanation of Key Component Symbols]

[0024]

[0025]

[0026]

[0027] Detailed Implementation

[0028] Please see Figure 3 , Figure 4 and Figure 5 , Figure 3 As an embodiment of the present invention, a top view of a semiconductor structure 100 is provided. Figure 4 and Figure 5 Then it is Figure 3 The cross-sectional view of line segments AA and BB in this embodiment shows that the semiconductor structure 100 has a substrate 110, a dielectric layer 120, a bonding layer 130, a ground metal layer 140, and multiple circuit layers 150. The substrate 110 has a surface 111 and multiple conductive pads 112, which are disposed on the surface 111 of the substrate 110. The conductive pads 112 serve as output / input terminals or ground terminals for internal electronic components of the substrate 110.

[0029] Please see Figure 4 and Figure 5 The dielectric layer 120 is disposed on the surface 111 of the substrate 110. The dielectric layer 120 has a plurality of openings 121, each opening 121 exposing the surface 111 or each conductive pad 112. The dielectric layer 120 is used as a protective layer for the surface 111 of the substrate 110 and as an insulating barrier between various circuit elements. The dielectric layer 120 may be BCB or Polyimide.

[0030] The bonding layer 130 is disposed on the dielectric layer 120. The bonding layer 130 has a first bonding portion 131 and a second bonding portion 132. The first bonding portion 131 is located in the opening 121 and connects to the surface 111 of the substrate 110 or the conductive pad 112. The second bonding portion 132 is located on the dielectric layer 120 and connects to the dielectric layer 120. The bonding layer 130 may be composed of a stack of titanium-tungsten alloy layers and copper layers to provide a bonding interface between the metal layer and the surface 111 of the substrate 110 or between the metal layer and the dielectric layer 120.

[0031] The grounding metal layer 140 is disposed on the bonding layer 130. The grounding metal layer 140 has a first grounding layer 141 and a second grounding layer 142. The first grounding layer 141 is located in the opening 121 of the dielectric layer 120 and is connected to the first bonding portion 131 of the bonding layer 130. The second grounding layer 142 is located on the dielectric layer 120 and is connected to the second bonding portion 132 of the bonding layer 130. Preferably, the grounding metal layer 140 does not carry any current signal and can serve as electromagnetic wave shielding. The first grounding layer 141 is electrically connected to the second grounding layer 142 via the bonding layer 130, so that the first grounding layer 141 and the second grounding layer 142 are electrically connected as a whole conductive layer with good electromagnetic wave shielding capability. The grounding metal layer 140 may be composed of pure copper or a stack of copper / nickel / copper layers.

[0032] The circuit layer 150 is disposed on and connected to the second bonding portion 132 of the bonding layer 130. Both ends of each circuit layer 150 extend into the opening 121 of each dielectric layer 120 and are connected to each conductive pad 112 via the first bonding portion 131, providing the conductive pads 112 connected at both ends for current signal transmission. Since the electrical signals transmitted by each circuit layer 150 may operate at radio frequency and generate electromagnetic waves, in this embodiment, a second ground layer 142 is provided between two adjacent circuit layers 150 to reduce electromagnetic interference generated by other circuit layers 150. The circuit layer 150 may be composed of pure copper or a stack of copper / nickel / copper layers.

[0033] Please see Figure 4 and Figure 5 The dielectric layer 120, the first junction 131, and the first ground layer 141 are located at the same first horizontal height H1, and the second junction 132, the second ground layer 142, and the circuit layer 150 are located at the same second horizontal height H2, which is higher than the first horizontal height H1. Since the second ground layer 142 and the circuit layer 150 are located at the same level, it is possible to avoid the electromagnetic waves generated by each circuit layer 150 from affecting the signal transmission of other circuit layers 150. Furthermore, the circuit layer 150 can be directly disposed on the dielectric layer 120 without the need for another dielectric layer, allowing the semiconductor structure 100 to achieve a 1P2M structure, reducing the complexity of the semiconductor structure 100 fabrication and its overall size.

[0034] Please see Figure 6 The flowchart shows a method 10 for manufacturing a semiconductor structure, which includes: providing a substrate 11, forming a dielectric layer 12, forming a bonding layer 13, forming a patterned photoresist layer 14, forming a metal layer 15, removing the patterned photoresist layer 16, and etching the bonding layer 17.

[0035] Please see Figures 7A-7G and Figures 8A-8G , it is Figure 3 For the sectional views of line segments AA and BB at each step, please refer to [link / reference]. Figure 6 , Figure 7A and Figure 8A In step 11, a substrate 110 is provided, the substrate having a surface 111 and a plurality of conductive pads 112 located on the surface 111 of the substrate 110.

[0036] Please see Figure 6 , Figure 7B and Figure 8B In step 12, a dielectric layer 120 is formed on the surface 111 of the substrate 110. The dielectric layer 120 has a plurality of openings 121, each of which exposes the surface 111 or the conductive pad 112. The dielectric layer 120 can generate the openings 121 through an exposure and development process.

[0037] Please see Figure 6 , Figure 7C and Figure 8C In step 13, a bonding layer 130 is formed on the dielectric layer 120. A portion of the bonding layer 130 is located in the opening 121 and connects to the surface 111 or each of the conductive pads 112. A portion of the bonding layer 130 is connected to the dielectric layer 120. The bonding layer 130 can be formed on the dielectric layer 120 by chemical plating or sputtering processes.

[0038] Please see Figure 6 , Figure 7D and Figure 8D In step 14, a patterned photoresist layer PR is formed on the bonding layer 130. The patterned photoresist layer PR has a plurality of openings O, which expose the bonding layer 130 to define the position for subsequent metal layer deposition. The patterned photoresist layer PR is formed on the bonding layer 130 through coating, exposure and development processes.

[0039] Please see Figure 6 , Figure 7E and Figure 8E In step 15, a metal layer M is formed in the opening O of the patterned photoresist layer PR. The metal layer M connects to the bonding layer 130 exposed by the opening O, and a portion of the metal layer M is located in the opening 121 of the dielectric layer 120. The metal layer M can be formed on the bonding layer 130 by electroplating.

[0040] Please see Figure 6 , Figure 7F and Figure 8F In step 16, the patterned photoresist layer PR is peeled off to expose the bonding layer 130 covered by the patterned photoresist layer PR. Finally, please refer to Figure 6 , Figure 7G and Figure 8G In step 17, the metal layer M is used as a mask to etch the bonding layer 130, so that the bonding layer 130 becomes the first bonding portion 131 and the second bonding portion 132, thereby completing the semiconductor structure 100.

[0041] This invention divides the ground metal layer 140 of the semiconductor structure 100 into a first ground layer 141 and a second ground layer 142, allowing the circuit layer 150 to be directly disposed on the dielectric layer 120, thus achieving a 1P2M structure, reducing process complexity and the size of the semiconductor structure 100. Furthermore, since the second ground layer 142 is also disposed on the dielectric layer 120, it can shield the electromagnetic interference between the circuit layers 150, thereby improving the electromagnetic shielding capability of the semiconductor structure 100.

[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, Include: Substrate, having a surface; A dielectric layer is disposed on the surface, the dielectric layer having a plurality of openings, each of the openings exposing the surface; A bonding layer is disposed on the dielectric layer, a first bonding portion of the bonding layer is located in the opening and the first bonding portion is connected to the surface, and a second bonding portion of the bonding layer is connected to the dielectric layer; A grounding metal layer is disposed on the bonding layer, wherein a first grounding layer of the grounding metal layer is connected to the first bonding portion of the bonding layer, and a second grounding layer of the grounding metal layer is connected to the second bonding portion of the bonding layer; as well as Multiple line layers are provided, each line layer is disposed on the second joint portion of the joint layer, and a second ground layer is provided between two adjacent line layers.

2. The semiconductor structure according to claim 1, characterized in that, The dielectric layer and the first ground layer are located at the same first horizontal height, and the second ground layer and the line layer are located at the same second horizontal height, which is higher than the first horizontal height.

3. The semiconductor structure according to claim 2, characterized in that, The substrate has a plurality of conductive pads disposed on the surface of the substrate. The opening of the dielectric layer exposes each conductive pad. The bonding layer connects the conductive pads through the opening, so that each circuit layer connects each conductive pad through the bonding layer.

4. The semiconductor structure according to claim 2, characterized in that, The first grounding layer is connected to the second grounding layer via the bonding layer.

5. The semiconductor structure according to claim 4, characterized in that, No current signal passed through the grounded metal layer.

6. A method for manufacturing a semiconductor structure, characterized in that, Include: A substrate is provided, the substrate having a surface; A dielectric layer is formed on the surface of the substrate, the dielectric layer having a plurality of openings that expose the surface; A bonding layer is formed on the dielectric layer, wherein a portion of the bonding layer is located in the opening and connects to the surface, and a portion of the bonding layer is connected to the dielectric layer; A patterned photoresist layer is formed on the bonding layer, the patterned photoresist layer having a plurality of openings that expose the bonding layer; A metal layer is formed in the opening of the patterned photoresist layer, the metal layer is connected to the bonding layer exposed by the opening, and a portion of the metal layer is located in the opening of the dielectric layer; Peel off the patterned photoresist layer to expose the bonding layer covered by the patterned photoresist layer; as well as The bonding layer is etched using the metal layer as a mask to form a first bonding portion and a second bonding portion. The first bonding portion is located in the opening and is connected to the surface. The second bonding portion is connected to the dielectric layer. The metal layer includes a ground metal layer and a plurality of line layers. The first ground layer of the ground metal layer is connected to the first bonding portion of the bonding layer. The second ground layer of the ground metal layer is connected to the second bonding portion of the bonding layer. Each line layer is disposed on the second bonding portion of the bonding layer, and a second ground layer is provided between two adjacent line layers.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The dielectric layer and the first ground layer are located at the same first horizontal height, and the second ground layer and the line layer are located at the same second horizontal height, which is higher than the first horizontal height.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The substrate has a plurality of conductive pads disposed on the surface of the substrate. The opening of the dielectric layer exposes each conductive pad. The bonding layer connects the conductive pads through the opening, so that each circuit layer connects each conductive pad through the bonding layer.

9. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The first grounding layer is connected to the second grounding layer via the bonding layer.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, No current signal passed through the grounded metal layer.

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