A diode and a method of manufacturing the same

Abstract

The application belongs to the field of electrical elements, and particularly relates to a diode and a manufacturing method thereof. The diode comprises a first electrode layer, a drift region, a cathode region and a second electrode layer which are sequentially stacked. The drift region is provided with an isolation layer. The isolation layer comprises a plurality of isolation regions and a plurality of isolation windows. The plurality of isolation regions are arranged at intervals, and the isolation windows are formed between two adjacent isolation regions. The isolation regions can isolate electrons so that the electrons pass through the isolation windows. In the embodiment of the application, the isolation regions play a role of current limiting, form a blocking structure, and make the current at the end of reverse blocking only pass through the isolation windows, so as to slow down the disappearance speed of the charge in the reverse extraction process, play a role of current limiting in the reverse blocking recovery process, lengthen the end of reverse recovery, and thus improve the softness of blocking.

Description

Technical Field

[0001] This invention belongs to the field of electrical components, and specifically relates to a diode and its manufacturing method. Background Technology

[0002] In high-frequency power switching applications, the main switching element often requires an anti-parallel freewheeling fast recovery diode (FRD). The switching parameters and performance of the FRD affect the reliability of the main switching application and the system. Poor turn-off softness of the diode can lead to severe waveform oscillations during application, especially in high-frequency applications, which can generate electromagnetic oscillations that interfere with the normal operation of other chips in the system, causing electromagnetic compatibility (EMC) problems.

[0003] In existing IGBT switching system applications, in order to improve the turn-off softness of diodes, high-energy helium implantation or hydrogen implantation is usually used to inject the hydrogen into the anode region of the diode substrate within a range of a few micrometers to tens of micrometers. Using this method to improve softness requires high-energy helium implantation or hydrogen implantation equipment, which makes the cost high, the process difficult, and the implantation depth limited. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a diode and its manufacturing method, addressing the issue of low switching softness in existing diodes.

[0005] To solve the above-mentioned technical problems, on the one hand, the present invention provides a diode, comprising a first electrode layer, a P-type anode region, a drift region, a cathode region and a second electrode layer stacked sequentially;

[0006] An isolation layer is provided within the drift region. The isolation layer includes multiple isolation zones and multiple isolation windows. The multiple isolation zones are spaced apart, and an isolation window is formed between two adjacent isolation zones. The isolation zones can isolate electrons so that electrons can pass through the isolation windows.

[0007] Optionally, the isolation zone is made of a wide bandgap material, and the bandgap width of the isolation zone is greater than 8 eV.

[0008] Optionally, the isolation region is an oxide or a nitride.

[0009] Optionally, the oxide is silicon oxide, and the nitride is silicon nitride.

[0010] Optionally, the thickness of the isolation layer is 0.2 to 1 μm, the ratio of the width of the isolation window to the width of the isolation area is 1 to 3, and the width of the isolation area is 3 to 10 μm.

[0011] Optionally, the junction depth of the P-type anode region is 2–20 μm.

[0012] Optionally, the first electrode layer is an aluminum layer or a copper layer, and the thickness of the first electrode layer is 1 to 6 μm; the second electrode layer is a Ti / Ni / Ag structure, and the thickness of the second electrode layer is 1 to 4 μm.

[0013] Optionally, the drift region includes an N-epitaxial layer and an N-type epitaxial transition layer stacked together, the N-type epitaxial transition layer being formed on the cathode region, and a plurality of isolation regions being spaced apart between the N-epitaxial layer and the N-type epitaxial transition layer, wherein the N-epitaxial layer and the N-type epitaxial transition layer are in direct contact at the isolation window.

[0014] Optionally, the isolation zones are arranged in parallel intervals side by side on the N-type epitaxial transition layer.

[0015] Optionally, the isolation regions are distributed in a matrix-like pattern or randomly spaced on the N-type epitaxial transition layer.

[0016] Optionally, the doping concentration of the cathode region is 1e. 18 ~1e 19 cm -3 The thickness is 300–500 μm; the doping concentration of the N-type epitaxial transition layer is 5e⁻¹. 14 ~1e 17 cm -3 The thickness is 10–50 μm; the doping concentration of the N-epitaxial layer is 1e. 13 ~1e 14 cm -3 The thickness is 10-150 μm.

[0017] On the other hand, the present invention provides a method for fabricating a diode, comprising:

[0018] A cathode region is provided, a drift region is formed on the upper surface of the cathode region, and an isolation layer is formed within the drift region;

[0019] P-type ion implantation is performed on the upper surface of the drift region, and annealing drives the ions to the designated junction depth to form a P-type anode region.

[0020] A first electrode layer is formed on the upper surface of the P-type anode region;

[0021] A second electrode layer is formed on the lower surface of the cathode region.

[0022] Optionally, the "forming a drift region on the upper surface of the cathode region" includes:

[0023] An N-type epitaxial transition layer is epitaxially grown on the upper surface of the cathode region;

[0024] An N-epitaxial layer is epitaxially grown on the upper surface of the cathode region.

[0025] Optionally, after the N-type epitaxial transition layer is epitaxially grown on the upper surface of the cathode region, the preparation method further includes:

[0026] The isolation layer is epitaxially grown on the upper surface of the N-type epitaxial transition layer;

[0027] After the isolation layer is formed on the N-type epitaxial transition layer, the preparation method further includes:

[0028] An N-epitaxial layer is epitaxially grown on the upper surface of the isolation layer.

[0029] Optionally, after the isolation layer is epitaxially grown on the surface of the N-type epitaxial transition layer to form the isolation layer, the preparation method includes:

[0030] The isolation layer is photolithographically etched to remove part of the isolation layer to form multiple isolation windows. The remaining part of the isolation layer serves as multiple isolation regions. The multiple isolation regions are spaced apart, and the isolation window is formed between two adjacent isolation regions.

[0031] Optionally, before forming the first electrode layer, the P-type anode region of the diode is subjected to electron irradiation or platinum diffusion, so that electrons penetrate the drift region and reach the cathode region.

[0032] Optionally, the cathode region may be subjected to a back-side thinning process before the formation of the second electrode layer.

[0033] Optionally, P-type ion implantation is performed as either B or Al implantation, with an implantation dose of 2e. 12 ~5e 13 cm -2 .

[0034] In this embodiment of the invention, by setting an isolation region within the drift region, the isolation region can block the passage of charge carriers, forming a blocking structure to limit the current. This allows the current at the end of the reverse turn-off period to pass only through the isolation window, slowing down the rate of charge loss during the reverse extraction process. This also limits the current during the reverse turn-off recovery process, lengthening the end of the reverse recovery period and thus improving the turn-off softness. Attached Figure Description

[0035] Figure 1 This is a cross-sectional view of a diode provided by existing technology;

[0036] Figures 2a-2f This is a process diagram of a diode manufacturing method provided in an embodiment of the present invention.

[0037] The reference numerals in the accompanying drawings are as follows:

[0038] 101. Cathode region; 102. N-type epitaxial transition layer; 103. Isolation layer; 104. N-epitaxial layer; 105. P-type anode region; 106. First electrode layer; 107. Second electrode layer; 108. Isolation region; 109. Isolation window;

[0039] 01. Anode metal layer; 02. P-type local lifetime control layer; 03. N-substrate layer; 04. N-type transition layer; 05. N+ layer; 06. Backside metal layer. Detailed Implementation

[0040] To make the technical problems solved, the technical solutions, and the beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0041] like Figures 2a to 2f As shown, an embodiment of the present invention provides a diode comprising a first electrode layer 106, a P-type anode region 105, a drift region, a cathode region 101, and a second electrode layer 107, which are sequentially stacked. The P-type anode region 105 is connected to the first electrode layer 106, and the cathode region 101 is a highly doped region, which is connected to the second electrode layer 107.

[0042] An isolation layer 103 is provided in the drift region. The isolation layer 103 includes a plurality of isolation regions 108 and a plurality of isolation windows 109. The plurality of isolation regions 108 are spaced apart. The isolation windows 109 are formed between two adjacent isolation regions 108. The isolation regions 108 can isolate electrons so that electrons can pass through the isolation windows 109.

[0043] The isolation region 108 is located within the drift region and serves to limit current, forming a blocking structure. Charge carriers cannot pass through the isolation region 108, so that the current at the end of the reverse turn-off can only pass through the isolation window 109, which slows down the rate of charge disappearance during the reverse extraction process and plays a current-limiting role during the reverse turn-off recovery process, thus lengthening the end of the reverse recovery period and improving the turn-off softness.

[0044] like Figure 1 The diagram shows a schematic of a diode structure in the prior art, including an anode metal layer 01, a P-type local lifetime control layer 02, an N-substrate layer 03, an N-type transition layer 04, an N+ layer 05, and a back metal layer 06 arranged sequentially from top to bottom. The dashed lines in the diagram indicate the locations of high-energy hydrogen or helium injection. Using a common local lifetime control process, most of the hydrogen or helium is concentrated at the dashed line location, with the remainder distributed along the injection path.

[0045] A power fast recovery diode (FRD) is a semiconductor device with good switching characteristics and a short reverse recovery time. According to the working principle of a fast recovery diode, when the diode is forward biased, a positive voltage is applied to the anode, and the PN junction composed of the P-type local lifetime control layer and the N-substrate layer conducts. Holes are injected from the P-type local lifetime control layer region into the N-substrate layer, and electrons are injected from the N+ layer into the N-substrate layer. When the diode is turned off, a positive voltage is applied to the cathode, and the PN junction composed of the P-type local lifetime control layer and the N-substrate layer expands mainly into the N-substrate layer under the reverse bias voltage. Carriers located near the PN junction composed of the N-substrate layer and the P-type local lifetime control layer are reverse-biased and extracted. The carrier concentration at this location determines the peak current during reverse recovery, and the level of carrier concentration determines the rate of current decrease during reverse recovery, thus determining the softness of the diode during turn-off.

[0046] Defects are created in the P-type region through hydrogen or helium ion implantation. These defects have energy levels closer to the center of the band gap than impurities, resulting in a greater recombination effect on charge carriers and effectively enhancing the reverse recovery characteristics of fast recovery diodes. However, in local lifetime control processes, proton and helium ion implantation require high-energy ion implantation, which is costly, technically challenging, and has limited implantation depth.

[0047] In this application, a blocking structure is formed by the isolation region 108, which can block the passage of charge carriers. During the reverse turn-off process, electrons can only move to the cathode region 101 through the isolation window 109. By setting the isolation region 108, the current passage area is reduced. The current at the end of the reverse turn-off can only pass through the isolation window 109, thereby slowing down the rate of charge disappearance during the reverse extraction process. It plays a current-limiting role during the reverse turn-off recovery process, which lengthens the end of the reverse recovery period and improves the turn-off softness. This avoids the defects introduced by the existing local lifetime control method of high-energy hydrogen or helium injection.

[0048] In one embodiment, the plurality of isolation regions 108 are spaced apart from each other. The shape and distribution of the isolation regions 108 are not particularly limited, as long as the isolation layer 103 has an isolation window 109 for current to pass through. The shape of the isolation regions 108 includes, but is not limited to, strip, circle, and square. The isolation regions 108 can be arranged in parallel, matrix-like, or irregularly spaced.

[0049] In one embodiment, the isolation region 108 is made of a wide bandgap material, with a bandgap width greater than 8 eV. The large bandgap of the isolation region 108 makes it difficult to excite valence band electrons, resulting in a very low carrier concentration and extremely low conductivity within the isolation region 108. During reverse turn-off, carriers cannot pass through the isolation region 108, forming a blocking structure. Consequently, the current at the end of the reverse turn-off phase can only pass through the isolation window 109.

[0050] In one embodiment, the isolation region 108 of the isolation layer 103 has the function of blocking charge carriers. There is no particular limitation on the specific material used for the isolation layer 103, as long as it can block charge carriers. Those skilled in the art can select according to their needs. Further, the isolation region 108 of the isolation layer 103 is made of oxide or nitride, and can be formed in the drift region by thermal growth or deposition. Preferably, the oxide is silicon oxide and the nitride is Si3N4.

[0051] In one embodiment, the thickness of the isolation layer 103 is 0.2–1 μm, the ratio of the width of the isolation window 109 to the width of the isolation region 108 is 1–3, and the width of the isolation region 108 is 3–10 μm. Within this range, it is beneficial for the reverse extraction process of charge carriers without causing losses in the reverse recovery process. Furthermore, when the ratio of the width of the isolation window 109 to the width of the isolation region 108 exceeds 3, the current passage area is too large, and the charge carrier passage speed is too fast, failing to achieve the current limiting effect in the reverse turn-off recovery process. When the ratio of the width of the isolation window 109 to the width of the isolation region 108 is less than 1, the current passage area is too small, which is not conducive to the reverse extraction process of charge carriers, and the reverse recovery process is too long, increasing reverse recovery losses and affecting the operating frequency of the diode.

[0052] In one embodiment, the junction depth of the P-type anode region 105 based on the N-epitaxial layer 104 is 2–20 μm. The P-type anode region 105 can be formed by ion implantation and high-temperature annealing processes. There are no particular limitations on the specific type and amount of implanted ions; preferably, boron implantation or aluminum implantation is used.

[0053] In one embodiment, the material of the first electrode layer 106 or the second electrode layer 107 is not particularly limited, but mainly has good electrical conductivity. The first electrode layer 106 is an aluminum layer, a silicon layer, or a copper layer, and the thickness of the first electrode layer 106 is 1–6 μm. The first electrode layer 106 is a single-layer metal structure. Preferably, the first electrode layer 106 is mainly an aluminum metal layer, in which silicon and copper are doped.

[0054] The second electrode layer 107 has a Ti / Ni / Ag structure and a thickness of 1–4 μm. Back-gold deposition is a process of depositing metal on the back side of a wafer. Currently, the metal materials used for back-gold evaporation are titanium (TI), nickel (NI), and silver (AG). The deposition order is titanium layer (1KA), nickel layer (2KA), and silver layer (10KA), respectively. Ti and Si can bond well, but the resistivity is high, so the Ti layer is the thinnest. Ni serves as an intermediate bonding layer and cannot be too thin. The outermost layer is an Ag layer to protect the Ni layer.

[0055] The Ti / Ni / Ag structure, as an electrode for power devices, has good thermal performance and electrical reliability. The Ti layer is used for adhesion to the silicon surface. Its thermal expansion coefficient is similar to that of the Si substrate and it has a very strong adhesion to Si. The Ag layer is stable, not easily oxidized, easy to solder to the base, has good electrical and thermal conductivity, and is low in cost. The Ni layer is an intermediate transition layer. Its electrical and thermal conductivity are moderate and its thermal expansion coefficient is between that of Ti and Ag. It can not only prevent Ag from diffusing into the Ti layer, but also achieve thermal matching between the upper and lower layers.

[0056] In one embodiment, the drift region includes an N-epitaxial layer 104 and an N-type epitaxial transition layer 102 stacked together, the isolation layer 103 being located between the N-epitaxial layer 104 and the N-type epitaxial transition layer 102, the N-type epitaxial transition layer 102 being formed on the side of the cathode region 101 away from the second electrode layer 107, and the N-epitaxial layer 104 being formed on the N-type epitaxial transition layer 102.

[0057] Multiple isolation zones 108 are spaced apart between the N-epitaxial layer 104 and the N-type epitaxial transition layer 102, and at the isolation window 109, the N-epitaxial layer 104 and the N-type epitaxial transition layer 102 are in direct contact.

[0058] In one embodiment, the isolation regions 108 are arranged in parallel and spaced side by side on the N-type epitaxial transition layer 102.

[0059] In one embodiment, the isolation region 108 on the N-type epitaxial transition layer may also be distributed in a matrix-like dotted pattern or randomly spaced.

[0060] In one embodiment, the material of the cathode region 101 includes, but is not limited to, SiC and Si materials, and the doping concentration of the cathode region 101 is 1e. 18 ~1e 19 cm -3 The cathode region 101 is a high-doping region with a thickness of 300–500 μm.

[0061] The N-type epitaxial transition layer 102 is formed on the cathode region 101 using an epitaxial process, and the doping concentration of the N-type epitaxial transition layer 102 is 5e. 14 ~1e 17 cm -3 The thickness is 10-50 μm.

[0062] The N-epitaxial layer 104 is formed on the N-type epitaxial transition layer 102 using an epitaxial process, and the doping concentration of the N-epitaxial layer 104 is 1e. 13 ~1e 14 cm -3 The thickness is 10-150 μm. The doping concentration of the N-type epitaxial transition layer 102 is slightly higher than that of the N-epitaxial layer 104. The N-epitaxial layer 104 covers the isolation region 108 of the isolation layer 103 and the N-type epitaxial transition layer 102 at the isolation window 109.

[0063] An embodiment of the present invention also provides a method for fabricating a diode, comprising:

[0064] A cathode region 101 is provided, a drift region is formed on the upper surface of the cathode region 101, and an isolation layer 103 is formed in the drift region;

[0065] P-type ion implantation is performed on the upper surface of the drift region, and annealing drives the ions to the designated junction depth to form a P-type anode region 105.

[0066] A first electrode layer 106 is formed on the upper surface of the P-type anode region 105;

[0067] A second electrode layer 107 is formed on the lower surface of the cathode region 101.

[0068] The isolation zone 103 is located within the drift zone, serving to limit the flow and forming a blocking structure.

[0069] In one embodiment, "forming a drift region on the upper surface of the cathode region" includes: epitaxially growing an N-type epitaxial transition layer 102 on the upper surface of the cathode region 101; and epitaxially growing an N-epitaxial layer 104 on the upper surface of the cathode region 101. The N-epitaxial layer 104 is located above the N-type epitaxial transition layer 102, and the doping concentration of the N-type epitaxial transition layer is 5e. 14 ~1e 17 cm -3 The doping concentration of the N-epitaxial layer is 1e 13 ~1e 14 cm -3 .

[0070] In one embodiment, an isolation layer 103 is formed in the drift region, the isolation layer 103 is epitaxially grown on the upper surface of the N-type epitaxial transition layer 102, and the N-epitaxial layer 104 is epitaxially grown on the upper surface of the isolation layer 103.

[0071] After the isolation layer 103 is epitaxially grown on the upper surface of the N-type epitaxial transition layer 102, the isolation layer 103 is photolithographically etched to remove a portion, forming a plurality of isolation windows 109. The remaining portion of the isolation layer serves as a plurality of isolation regions 108. The plurality of isolation regions 108 are spaced apart, and the isolation window 109 is formed between two adjacent isolation regions 108.

[0072] Specifically, the drift region includes a stacked N-epitaxial layer 104 and an N-type epitaxial transition layer 102. The N-type epitaxial transition layer 102 is formed on the side of the cathode region 101 away from the second electrode layer 107. The isolation layer 103 is located between the N-epitaxial layer 104 and the N-type epitaxial transition layer 102. A plurality of isolation regions 108 are spaced apart between the lower surface of the N-epitaxial layer 104 and the upper surface of the N-type epitaxial transition layer 102. At the isolation window 109, the N-epitaxial layer 104 and the N-type epitaxial transition layer 102 are in direct contact.

[0073] In this embodiment, the isolation layer 103 is deposited on the N-type epitaxial transition layer 102, and the isolation window 109 is obtained by photolithography. The isolation region 108 forms a blocking structure, which reduces the current passage area in the isolation layer 103, so that the current at the end of the reverse turn-off can only pass through the isolation window 109, slowing down the rate of charge disappearance during the reverse extraction process, and playing a current limiting role in the reverse turn-off recovery process, thus lengthening the end of the reverse recovery period and improving the turn-off softness.

[0074] In one embodiment, such as Figure 2a As shown, a highly doped cathode region 101 is provided, and an N-type epitaxial transition layer 102 is formed on the cathode region 101 using an epitaxial process. The doping concentration of the N-type epitaxial transition layer 102 is lower than that of the cathode region 101, and the doping concentration of the cathode region 101 is 1e. 18 ~1e 19 cm -3 The thickness is 300-500 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 5e. 14 ~1e 17 cm -3 The thickness is 10-50 μm.

[0075] As is generally known, epitaxy refers to the growth of a single-crystal material with the same lattice arrangement as the substrate on a single-crystal substrate. The epitaxial layer can be a homoepitaxial layer or a heteroepitaxial layer. There are many methods to achieve epitaxial growth, including molecular beam epitaxy, ultra-high vacuum chemical vapor deposition, atmospheric pressure and depressurization epitaxy, etc. The methods used to achieve epitaxy employ conventional operations and methods in this field, and will not be elaborated here.

[0076] In one embodiment, such as Figure 2b , Figure 2c As shown, the isolation layer 103 is formed on the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 0.2–1 μm. At this time, the isolation layer 103 completely covers the upper surface of the N-type epitaxial transition layer 102. Part of the isolation layer 103 is removed by photolithography using a mask, forming the isolation window 109 at the location where part of the isolation layer is removed. This exposes a portion of the N-type epitaxial transition layer 102 below the isolation layer 103. Isolation regions 108 are formed at the locations not removed by photolithography. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 1–3, and the width of the isolation region 108 is 3–10 μm. Multiple isolation regions 108 are distributed on the upper surface of the N-type epitaxial transition layer 102, with the isolation windows 109 located between adjacent isolation regions 108.

[0077] The shape of the isolation region 108 includes, but is not limited to, strip, circle, and square. The N-type epitaxial transition layer 102 at the isolation window 109 is partially exposed and does not obstruct current flow. The isolation region 108 has a blocking effect; during reverse turn-off recovery, the current at the end of the reverse turn-off passes through the isolation window 109. Overall, the isolation region 108 of the isolation layer 103 reduces the current flow area, thus lengthening the reverse recovery period and improving turn-off softness.

[0078] In one embodiment, such as Figure 2d As shown, an N-epitaxial layer 104 is further epitaxially formed on the N-type epitaxial transition layer 102. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 on the isolation region 108 and at the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 13 ~1e 14 cm -3 The thickness is 10-150 μm.

[0079] In one embodiment, such as Figure 2e As shown, P-type ion implantation and annealing are performed on the upper surface of the N-epitaxial layer 104 to form the P-type anode region 105. The P-type ion implantation is boron implantation or aluminum implantation, and the implantation dose is 2e. 12~5e 13 cm -2 After annealing, a region with a junction depth of 2-20 μm is formed.

[0080] The basic principle of ion implantation is as follows: an ion beam of a certain magnitude is incident into the N-epitaxial layer 104. The ion beam undergoes a series of physical and chemical interactions with the atoms or molecules in the N-epitaxial layer 104. The incident ions gradually lose energy and eventually remain in the N-epitaxial layer 104, causing changes in the surface composition, structure, and properties of the N-epitaxial layer 104, thereby optimizing performance or obtaining certain new superior properties. Annealing is a heat treatment process performed in an inert atmosphere such as nitrogen. The methods and operations of ion implantation and annealing are well known in the art and will not be described in detail here.

[0081] In one embodiment, before forming the first electrode layer 106, the P-type anode region 105 of the diode undergoes lifetime control processes such as electron irradiation or platinum expansion. Electron irradiation and platinum expansion are global lifetime control techniques that control the overall lifetime of the fast recovery diode. Electrons can easily penetrate to the cathode region 101 at high energies, resulting in a more uniform distribution of induced defects.

[0082] The essence of lifetime control is to utilize defects formed by electron irradiation or heavy metal diffusion. The energy levels of these defects are closer to the center of the band gap than those of impurities, and have a greater recombination effect on charge carriers, which can effectively enhance the reverse recovery characteristics of fast recovery diodes.

[0083] like Figure 2f As shown, a first electrode layer 106 is formed on the upper surface of the P-type anode region 105, with a metal thickness of 1 to 6 μm.

[0084] Before forming the second electrode layer 107, the cathode region 101 is thinned on the back side by grinding or acid-base etching, which helps to reduce the overall thickness of the diode. After the back side is thinned, the second electrode layer 107 is formed on the lower surface of the cathode region 101. The second electrode layer 107 adopts a Ti / Ni / Ag multilayer metal structure, and the total thickness of the second electrode layer 107 is 1 to 4 μm.

[0085] The present invention will be further illustrated by the following examples.

[0086] Example 1

[0087] S1. Provide a cathode region 101, and form an N-type epitaxial transition layer 102 on the cathode region 101 using an epitaxial process. The doping concentration of the cathode region 101 is 1e. 18 cm -3The thickness is 300 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 5e. 14 cm -3 The thickness is 10um;

[0088] S2. An isolation layer 103 is formed on the upper surface of the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 0.2 μm. Part of the isolation layer 103 is removed by photolithography etching to form an isolation region 108 and an isolation window 109. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 1. The width of the isolation region 108 is 3 μm.

[0089] S3. An N-epitaxial layer 104 is formed above the N-type epitaxial transition layer 102 using an epitaxial process. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 at the isolation region 108 and the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 13 cm -3 The thickness is 10um;

[0090] S4. Perform P-type ion implantation on the upper surface of the N-epitaxial layer 104, with an implantation dose of 2e. 12 cm -2 After annealing, a region with a junction depth of 2 μm is formed.

[0091] S5. Perform lifetime control processes such as electron irradiation or platinum expansion on the diode to form a first electrode layer 106 with a metal thickness of 1µm on the upper surface of the P-type anode region 105.

[0092] S6. The cathode region 101 is thinned on the back side by grinding or acid-base etching to form a second electrode layer 107 on the lower surface of the cathode region 101. The total thickness of the second electrode layer 107 is 1 μm.

[0093] Example 2

[0094] S1. Provide a cathode region 101, and form an N-type epitaxial transition layer 102 on the cathode region 101 using an epitaxial process. The doping concentration of the cathode region 101 is 1e. 19 cm -3 The thickness is 500 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 1e. 17 cm -3 The thickness is 50um;

[0095] S2. An isolation layer 103 is formed on the upper surface of the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 0.6 μm. Part of the isolation layer 103 is removed by photolithography etching to form an isolation region 108 and an isolation window 109. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 3:1. The width of the isolation region 108 is 10 μm.

[0096] S3. An N-epitaxial layer 104 is formed above the N-type epitaxial transition layer 102 using an epitaxial process. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 at the isolation region 108 and the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 14 cm -3 The thickness is 150um;

[0097] S4. Perform P-type ion implantation on the upper surface of the N-epitaxial layer 104, with an implantation dose of 5e. 13 cm -2 After annealing, a region with a junction depth of 20 μm is formed.

[0098] S5. Perform lifetime control processes such as electron irradiation or platinum expansion on the diode to form a first electrode layer 106 with a metal thickness of 3um on the upper surface of the P-type anode region 105.

[0099] S6. The cathode region 101 is thinned on the back side by grinding or acid-base etching to form a second electrode layer 107 on the lower surface of the cathode region 101. The total thickness of the second electrode layer 107 is 2.5 μm.

[0100] Example 3

[0101] S1. Provide a cathode region 101, and form an N-type epitaxial transition layer 102 on the cathode region 101 using an epitaxial process. The doping concentration of the cathode region 101 is 1e. 18 cm -3 The thickness is 400 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 1e. 16 cm -3 The thickness is 28um;

[0102] S2. An isolation layer 103 is formed on the upper surface of the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 1 μm. Part of the isolation layer 103 is removed by photolithography etching to form an isolation region 108 and an isolation window 109. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 2:1. The width of the isolation region 108 is 6 μm.

[0103] S3. An N-epitaxial layer 104 is formed above the N-type epitaxial transition layer 102 using an epitaxial process. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 at the isolation region 108 and the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 14 cm -3 The thickness is 80um;

[0104] S4. Perform P-type ion implantation on the upper surface of the N-epitaxial layer 104, with an implantation dose of 2e. 13 cm -2 After annealing, a region with a junction depth of 11 μm is formed.

[0105] S5. Perform electron irradiation or platinum expansion and other lifetime control processes on the diode to form a first electrode layer 106 with a metal thickness of 6um on the upper surface of the P-type anode region 105.

[0106] S6. The cathode region 101 is thinned on the back side by grinding or acid-base etching to form a second electrode layer 107 on the lower surface of the cathode region 101. The total thickness of the second electrode layer 107 is 4 μm.

[0107] Example 4

[0108] S1. Provide a cathode region 101, and form an N-type epitaxial transition layer 102 on the cathode region 101 using an epitaxial process. The doping concentration of the cathode region 101 is 1e. 19 cm -3 The thickness is 320 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 5e. 15 cm -3 The thickness is 34um;

[0109] S2. An isolation layer 103 is formed on the upper surface of the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 0.3 μm. Part of the isolation layer 103 is removed by photolithography etching to form an isolation region 108 and an isolation window 109. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 1.5:1. The width of the isolation region 108 is 9 μm.

[0110] S3. An N-epitaxial layer 104 is formed above the N-type epitaxial transition layer 102 using an epitaxial process. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 at the isolation region 108 and the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 13 cm -3 The thickness is 140um;

[0111] S4. Perform P-type ion implantation on the upper surface of the N-epitaxial layer 104, with an implantation dose of 5e.12 cm -2 After annealing, a region with a junction depth of 5 μm is formed.

[0112] S5. Perform lifetime control processes such as electron irradiation or platinum expansion on the diode to form a first electrode layer 106 with a metal thickness of 2um on the upper surface of the P-type anode region 105.

[0113] S6. The cathode region 101 is thinned on the back side by grinding or acid-base etching to form a second electrode layer 107 on the lower surface of the cathode region 101. The total thickness of the second electrode layer 107 is 1.5 μm.

[0114] Example 5

[0115] S1. Provide a cathode region 101, and form an N-type epitaxial transition layer 102 on the cathode region 101 using an epitaxial process. The doping concentration of the cathode region 101 is 1e. 18 cm -3 The thickness is 430 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 1e. 15 cm -3 The thickness is 48um;

[0116] S2. An isolation layer 103 is formed on the upper surface of the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 0.9 μm. Part of the isolation layer 103 is removed by photolithography etching to form an isolation region 108 and an isolation window 109. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 2.4:1. The width of the isolation region 108 is 7 μm.

[0117] S3. An N-epitaxial layer 104 is formed above the N-type epitaxial transition layer 102 using an epitaxial process. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 at the isolation region 108 and the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 13 cm -3 The thickness is 40um;

[0118] S4. Perform P-type ion implantation on the upper surface of the N-epitaxial layer 104, with an implantation dose of 4e. 13 cm -2 After annealing, a region with a junction depth of 8 μm is formed.

[0119] S5. Perform electron irradiation or platinum expansion and other lifetime control processes on the diode to form a first electrode layer 106 with a metal thickness of 5um on the upper surface of the P-type anode region 105.

[0120] S6. The cathode region 101 is thinned on the back side by grinding or acid-base etching to form a second electrode layer 107 on the lower surface of the cathode region 101. The total thickness of the second electrode layer 107 is 1.2 μm.

[0121] Example 6

[0122] S1. Provide a cathode region 101, and form an N-type epitaxial transition layer 102 on the cathode region 101 using an epitaxial process. The doping concentration of the cathode region 101 is 1e. 19 cm -3 The thickness is 340 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 1e. 16 cm -3 The thickness is 42um;

[0123] S2. An isolation layer 103 is formed on the upper surface of the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 0.5 μm. Part of the isolation layer 103 is removed by photolithography etching to form an isolation region 108 and an isolation window 109. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 1.8:1. The width of the isolation region 108 is 4 μm.

[0124] S3. An N-epitaxial layer 104 is formed above the N-type epitaxial transition layer 102 using an epitaxial process. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 at the isolation region 108 and the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 14 cm -3 The thickness is 105um;

[0125] S4. Perform P-type ion implantation on the upper surface of the N-epitaxial layer 104, with an implantation dose of 5e. 13 cm -2 After annealing, a region with a junction depth of 13 μm is formed.

[0126] S5. Perform lifetime control processes such as electron irradiation or platinum expansion on the diode to form a first electrode layer 106 with a metal thickness of 1.5um on the upper surface of the P-type anode region 105.

[0127] S6. The cathode region 101 is thinned on the back side by grinding or acid-base etching to form a second electrode layer 107 on the lower surface of the cathode region 101. The total thickness of the second electrode layer 107 is 3.4 μm.

[0128] Example 7

[0129] S1. Provide a cathode region 101, and form an N-type epitaxial transition layer 102 on the cathode region 101 using an epitaxial process. The doping concentration of the cathode region 101 is 1e.18 cm -3 The thickness is 480 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 8e. 15 cm -3 The thickness is 15um;

[0130] S2. An isolation layer 103 is formed on the upper surface of the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 0.7 μm. Part of the isolation layer 103 is removed by photolithography etching to form an isolation region 108 and an isolation window 109. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 2.6:1. The width of the isolation region 108 is 5 μm.

[0131] S3. An N-epitaxial layer 104 is formed above the N-type epitaxial transition layer 102 using an epitaxial process. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 at the isolation region 108 and the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 13 cm -3 The thickness is 65um;

[0132] S4. Perform P-type ion implantation on the upper surface of the N-epitaxial layer 104, with an implantation dose of 6e. 12 cm -2 After annealing, a region with a junction depth of 18 μm is formed.

[0133] S5. Perform electron irradiation or platinum expansion and other lifetime control processes on the diode to form a first electrode layer 106 with a metal thickness of 4um on the upper surface of the P-type anode region 105.

[0134] S6. The cathode region 101 is thinned on the back side by grinding or acid-base etching to form a second electrode layer 107 on the lower surface of the cathode region 101. The total thickness of the second electrode layer 107 is 1.8 μm.

[0135] Example 8

[0136] S1. Provide a cathode region 101, and form an N-type epitaxial transition layer 102 on the cathode region 101 using an epitaxial process. The doping concentration of the cathode region 101 is 1e. 19 cm -3 The thickness is 370 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 1e. 17 cm -3 The thickness is 20um;

[0137] S2. An isolation layer 103 is formed on the upper surface of the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 0.4 μm. Part of the isolation layer 103 is removed by photolithography etching to form an isolation region 108 and an isolation window 109. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 2:1. The width of the isolation region 108 is 8 μm.

[0138] S3. An N-epitaxial layer 104 is formed above the N-type epitaxial transition layer 102 using an epitaxial process. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 at the isolation region 108 and the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 14 cm -3 The thickness is 125um;

[0139] S4. Perform P-type ion implantation on the upper surface of the N-epitaxial layer 104, with an implantation dose of 2e. 12 cm -2 After annealing, a region with a junction depth of 4µm is formed.

[0140] S5. Perform lifetime control processes such as electron irradiation or platinum expansion on the diode to form a first electrode layer 106 with a metal thickness of 3um on the upper surface of the P-type anode region 105.

[0141] S6. The cathode region 101 is thinned on the back side by grinding or acid-base etching to form a second electrode layer 107 on the lower surface of the cathode region 101. The total thickness of the second electrode layer 107 is 2 μm.

[0142] Example 9

[0143] S1. Provide a cathode region 101, and form an N-type epitaxial transition layer 102 on the cathode region 101 using an epitaxial process. The doping concentration of the cathode region 101 is 1e. 18 cm -3 The thickness is 450 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 5e. 16 cm -3 The thickness is 38um;

[0144] S2. An isolation layer 103 is formed on the upper surface of the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 0.8 μm. Part of the isolation layer 103 is removed by photolithography etching to form an isolation region 108 and an isolation window 109. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 3:1. The width of the isolation region 108 is 4.5 μm.

[0145] S3. An N-epitaxial layer 104 is formed above the N-type epitaxial transition layer 102 using an epitaxial process. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 at the isolation region 108 and the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 14 cm -3 The thickness is 25um;

[0146] S4. Perform P-type ion implantation on the upper surface of the N-epitaxial layer 104, with an implantation dose of 2e. 13 cm -2 After annealing, a region with a junction depth of 16 μm is formed.

[0147] S5. Perform lifetime control processes such as electron irradiation or platinum expansion on the diode to form a first electrode layer 106 with a metal thickness of 1µm on the upper surface of the P-type anode region 105.

[0148] S6. The cathode region 101 is thinned on the back side by grinding or acid-base etching to form a second electrode layer 107 on the lower surface of the cathode region 101. The total thickness of the second electrode layer 107 is 2.8 μm.

[0149] Example 10

[0150] S1. Provide a cathode region 101, and form an N-type epitaxial transition layer 102 on the cathode region 101 using an epitaxial process. The doping concentration of the cathode region 101 is 1e. 19 cm -3 The thickness is 410 μm, and the doping concentration of the N-type epitaxial transition layer 102 is 5e. 14 cm -3 The thickness is 24um;

[0151] S2. An isolation layer 103 is formed on the upper surface of the N-type epitaxial transition layer 102 by thermal growth or deposition. The isolation layer 103 has a thickness of 0.2 μm. Part of the isolation layer 103 is removed by photolithography etching to form an isolation region 108 and an isolation window 109. The ratio of the width of the isolation window 109 to the width of the isolation region 108 is 1:1. The width of the isolation region 108 is 6 μm.

[0152] S3. An N-epitaxial layer 104 is formed above the N-type epitaxial transition layer 102 using an epitaxial process. The N-epitaxial layer 104 covers the N-type epitaxial transition layer 102 at the isolation region 108 and the isolation window 109. The doping concentration of the N-epitaxial layer 104 is 1e. 13 cm -3 The thickness is 95um;

[0153] S4. Perform P-type ion implantation on the upper surface of the N-epitaxial layer 104, with an implantation dose of 5e.13 cm -2 After annealing, a region with a junction depth of 12 μm is formed.

[0154] S5. Perform lifetime control processes such as electron irradiation or platinum expansion on the diode to form a first electrode layer 106 with a metal thickness of 2um on the upper surface of the P-type anode region 105.

[0155] S6. The cathode region 101 is thinned on the back side by grinding or acid-base etching to form a second electrode layer 107 on the lower surface of the cathode region 101. The total thickness of the second electrode layer 107 is 3 μm.

[0156] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A diode, characterized in that, It includes a first electrode layer, a P-type anode region, a drift region, a cathode region, and a second electrode layer, which are stacked sequentially. An isolation layer is provided within the drift region. The isolation layer includes multiple isolation zones and multiple isolation windows. The multiple isolation zones are spaced apart, and an isolation window is formed between two adjacent isolation zones. The isolation zones can isolate electrons, allowing electrons to pass through the isolation windows. The isolation zone is made of a wide bandgap material, the bandgap width of the isolation zone is greater than 8 eV, and the ratio of the width of the isolation window to the width of the isolation zone is 1 to 3.

2. The diode as described in claim 1, characterized in that, The isolation zone is an oxide or nitride.

3. The diode as described in claim 2, characterized in that, The oxide is silicon oxide or the nitride is silicon nitride.

4. The diode as claimed in claim 1, characterized in that, The thickness of the isolation layer is 0.2 to 1 μm, the ratio of the width of the isolation window to the width of the isolation area is 1 to 3, and the width of the isolation area is 3 to 10 μm.

5. The diode as claimed in claim 1, characterized in that, The junction depth of the P-type anode region is 2–20 μm.

6. The diode as claimed in claim 1, characterized in that, The first electrode layer is an aluminum layer or a copper layer, and the thickness of the first electrode layer is 1 to 6 μm; the second electrode layer is a Ti / Ni / Ag structure, and the thickness of the second electrode layer is 1 to 4 μm.

7. The diode as claimed in claim 1, characterized in that, The drift region includes an N-epitaxial layer and an N-type epitaxial transition layer stacked together. The N-type epitaxial transition layer is formed on the cathode region. The isolation layer is located between the N-epitaxial layer and the N-type epitaxial transition layer. At the isolation window, the N-epitaxial layer and the N-type epitaxial transition layer are in direct contact.

8. The diode as claimed in claim 7, characterized in that, The isolation zones are arranged in parallel and spaced-apart rows on the N-type epitaxial transition layer.

9. The diode as claimed in claim 7, characterized in that, The isolation regions are distributed in a matrix-like pattern or randomly spaced on the N-type epitaxial transition layer.

10. The diode as claimed in claim 7, characterized in that, The doping concentration of the cathode region is 1e. 18 ~1e 19 cm -3 The thickness is 300–500 μm; the doping concentration of the N-type epitaxial transition layer is 5e⁻¹. 14 ~1e 17 cm -3 The thickness is 10–50 μm; the doping concentration of the N-epitaxial layer is 1e. 13 ~1e 14 cm -3 The thickness is 10-150 μm.

11. A method for fabricating a diode, characterized in that, include: A cathode region is provided, a drift region is formed on the upper surface of the cathode region, and an isolation layer is formed within the drift region; The isolation layer is photolithographically etched to remove part of the isolation layer to form multiple isolation windows. The remaining part of the isolation layer serves as multiple isolation regions. The multiple isolation regions are spaced apart, and the isolation window is formed between two adjacent isolation regions. P-type ion implantation is performed on the upper surface of the drift region, and annealing drives the ions to the designated junction depth to form a P-type anode region. A first electrode layer is formed on the upper surface of the P-type anode region; A second electrode layer is formed on the lower surface of the cathode region; The isolation zone is made of a wide bandgap material, the bandgap width of the isolation zone is greater than 8 eV, and the ratio of the width of the isolation window to the width of the isolation zone is 1 to 3.

12. The method for fabricating a diode as described in claim 11, characterized in that, The phrase "forming a drift region on the upper surface of the cathode region" includes: An N-type epitaxial transition layer is epitaxially grown on the upper surface of the cathode region; An N-epitaxial layer is epitaxially grown on the upper surface of the N-type epitaxial transition layer.

13. The method for fabricating a diode as described in claim 12, characterized in that, After the N-type epitaxial transition layer is epitaxially grown on the upper surface of the cathode region, the preparation method further includes: The isolation layer is epitaxially grown on the upper surface of the N-type epitaxial transition layer; After the isolation layer is formed on the N-type epitaxial transition layer, the preparation method further includes: An N-epitaxial layer is epitaxially grown on the upper surface of the isolation layer.

14. The method for fabricating a diode as described in claim 11, characterized in that, Before forming the first electrode layer, the P-type anode region of the diode is subjected to electron irradiation or platinum diffusion, so that electrons penetrate the drift region and reach the cathode region.

15. The method for fabricating a diode as described in claim 11, characterized in that, Before forming the second electrode layer, the cathode region undergoes a back-side thinning process.

16. The method for fabricating a diode as described in claim 11, characterized in that, P-type ion implantation is performed using either beta (B) or al (Al) implantation, with an implantation dose of 2e⁻¹. 12 ~5e 13 cm -2 .

Images