Short channel double-gate igzo thin film transistor and preparation method thereof

Abstract

This invention relates to a short-channel dual-gate IGZO thin-film transistor and its fabrication method, addressing the problems of large top contact length and high contact resistance in existing dual-gate IGZO thin-film transistors. The transistor, from bottom to top, comprises a back gate, a back gate dielectric layer, an a-IGZO layer, a top gate dielectric layer, and a top gate, stacked sequentially. A source layer is disposed between the upper surface of the left end of the a-IGZO layer and the top gate dielectric layer, and a drain layer is disposed between the upper surface of the right end of the a-IGZO layer and the top gate dielectric layer. A channel is formed between the source layer and the drain layer, and the length of the channel is L. CH The top contact length L between the drain and source layers is 30-36 nm. C All are 40-44nm. The dual-gate IGZO thin-film transistor of the present invention achieves high-density integration through the combined effect of each layer, and also has excellent electrical performance. The transistor has an on-state current ≥56.3μA / μm and a contact resistance ≤500Ω·μm.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a short-channel dual-gate IGZO thin-film transistor and its fabrication method. Background Technology

[0002] Very large-scale IGZO transistors (VLSIs) show great promise in 2T0C DRAM applications due to their extremely low off-state current, high on / off ratio, and back-end compatible manufacturing processes. For VLSI field-effect transistors (FETs), the area they occupy is determined by the contact pitch (CP), which is equal to the channel length (L). CH ) and top contact length (L) C ) and.

[0003] Currently, the scalability of channel length has been extensively studied, while existing dual-gate IGZO thin-film transistors have a limited top contact length (L). C Problems include large size, high contact resistance, and relatively large transistor size. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide a short-channel dual-gate IGZO thin-film transistor and its fabrication method, in order to solve the problems of large top contact length, large contact resistance and large transistor ratio in the prior art of dual-gate IGZO thin-film transistors.

[0005] On one hand, the present invention provides a short-channel dual-gate IGZO thin film transistor, wherein the transistor comprises, from bottom to top, a back gate, a back gate dielectric layer, an a-IGZO layer, a top gate dielectric layer and a top gate, which are sequentially stacked.

[0006] A source layer is disposed between the upper surface of the left end of the a-IGZO layer and the top gate dielectric layer, and a drain layer is disposed between the upper surface of the right end of the a-IGZO layer and the top gate dielectric layer.

[0007] A channel is provided between the source layer and the drain layer, and the length of the channel is L. CH The top contact length L between the drain and source layers is 30-36 nm. C Both are 40-44nm.

[0008] Furthermore, the back gate material is molybdenum with a thickness of 20-30 nm.

[0009] Furthermore, the back gate dielectric layer is made of hafnium oxide and has a thickness of 5-10 nm.

[0010] Furthermore, both the source layer and the drain layer are made of Ni / Au, with Ni having a thickness of 18-22 nm and Au having a thickness of 13-17 nm.

[0011] Furthermore, the top gate dielectric layer is made of Al2O3 / HfO2, with the Al2O3 having a thickness of 1-3 nm and the HfO2 having a thickness of 6-10 nm.

[0012] Furthermore, the top gate material is Ni / Au, with Ni having a thickness of 15-25nm and Au having a thickness of 10-20nm.

[0013] Furthermore, the transistor has an on-state current of 49.67-56.3 μA / μm and a contact resistance of ≤500 Ω·μm.

[0014] Secondly, the present invention provides a method for fabricating the aforementioned short-channel dual-gate IGZO thin-film transistor, comprising the following steps:

[0015] (1) Fabrication of a back gate on a silicon oxide substrate;

[0016] (2) A back gate dielectric layer is prepared on the back gate;

[0017] (3) An a-IGZO layer is prepared on the back gate dielectric layer;

[0018] (4) A source layer and a drain layer are prepared on the a-IGZO layer;

[0019] (5) A top gate dielectric layer is prepared on the source layer, drain layer and a-IGZO layer;

[0020] (6) A top gate is fabricated on the top gate dielectric layer.

[0021] Furthermore, in step (4), the source layer and drain layer are prepared by electron beam evaporation, and the vacuum degree during electron beam evaporation is 0.9 × 10⁻⁶. -9 ~1.1×10 -9 torr.

[0022] Furthermore, in step (5), both the source layer and the drain layer are made of Ni / Au.

[0023] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0024] (1) The top contact length L of the drain layer and source layer of the dual-gate IGZO thin film transistor of the present invention C The channel is relatively short, reaching 40-44nm, with a channel length L. CHThe transistor is relatively short, reaching 30-36nm. Through the combined effect of each layer, high-density integration is achieved. At the same time, it has good electrical performance, with high on-state current and low contact resistance. The on-state current of the transistor is 49.67-56.3μA / μm, and the contact resistance is ≤500Ω·μm.

[0025] (2) The transistor of the present invention uses Al2O3 / HfO2 double stack as the top gate dielectric layer, so that the prepared IGTO thin film transistor has an ultra-clean channel interface, is not doped by impurities and defects, and has good electrical performance.

[0026] (3) In the method of the present invention, the source layer and drain layer adopt vacuum nickel-gold growth technology, which optimizes the contact spacing between transistors and reduces the contact resistance. Moreover, the method of the present invention is simple and can be mass-produced.

[0027] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0028] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0029] Figure 1 This is a schematic diagram of a short-channel dual-gate IGZO thin-film transistor provided by the present invention.

[0030] 1-Back gate, 2-Back gate dielectric layer, 3-a-IGZO layer, 4-Top gate dielectric layer, 5-Top gate, 6-Source layer, 7-Drain layer. Detailed Implementation

[0031] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which constitute a part of the present invention and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0032] A specific embodiment of the present invention, such as Figure 1 As shown, a short-channel dual-gate IGZO thin-film transistor is disclosed. The transistor includes, from bottom to top, a back gate 1, a back gate dielectric layer 2, an a-IGZO layer 3, a top gate dielectric layer 4, and a top gate 5, which are stacked sequentially.

[0033] A source layer 6 is disposed between the upper surface of the left end of the a-IGZO layer 3 and the top gate dielectric layer 4, and a drain layer 6 is disposed between the upper surface of the right end of the a-IGZO layer 3 and the top gate dielectric layer 4.

[0034] A channel is provided between the source layer 6 and the drain layer 7, and the length of the channel is L. CH The top contact length L between the drain layer 6 and the source layer 7 is 30-36nm. C Both are 40-44nm.

[0035] Compared with the prior art, the transistor prepared by the present invention, through the combined effect of each layer, increases the top contact length L between the drain layer 6 and the source layer 7. C The channel is relatively short, reaching 40-44nm, with a channel length L. CH The transistor is relatively short, reaching 30-36 nm, and also has excellent electrical performance. The on-state current of the transistor is 49.67-56.3 μA / μm, and the contact resistance is ≤500 Ω·μm.

[0036] For example, the channel length is 30nm, 31nm, 32nm, 33nm, 34nm, 35nm, 36nm, and the top contact length is 40nm, 41nm, 42nm, 43nm, 44nm.

[0037] Specifically, the back gate 1 is made of molybdenum and has a thickness of 20-30nm, for example, 20nm, 22nm, 24nm, 26nm, 28nm, or 30nm.

[0038] It should be noted that excessively thick molybdenum (Mo) will make it difficult to make the device thin, while excessively thin molybdenum will easily cause over-etching during the dry etching process.

[0039] Specifically, the back gate dielectric layer 2 is made of hafnium oxide with a thickness of 5-10 nm. For example, 3 nm, 45 nm, 6 nm, 7 nm, and 8 nm.

[0040] It should be noted that hafnium oxide is a high-k dielectric material, which allows the back gate dielectric layer 2 to be thinner while having the same effect. An excessively thin back gate dielectric layer 2 will cause transistor breakdown, while an excessively thick back gate dielectric layer 2 will cause a significant decrease in gate control capability.

[0041] Specifically, the source layer 6 and drain layer 7 are both made of Ni / Au, with Ni thickness of 18-22nm, for example, 18nm, 19nm, 20nm, 21nm, 22nm, and Au thickness of 13-17nm, for example, 13nm, 14nm, 15nm, 16nm, 17nm.

[0042] It should be noted that if the source layer 6 and drain layer 7 are too thin, it will affect their contact performance with the a-IGZO layer 3; if they are too thick, they will have a greater shielding effect on the electric field of the top gate 5.

[0043] Specifically, the top gate dielectric layer is made of Al2O3 / HfO2, with the Al2O3 having a thickness of 1-3nm, for example, 1nm, 2nm, or 3nm, and the HfO2 having a thickness of 6-10nm, for example, 6nm, 7nm, 8nm, 9nm, or 10nm.

[0044] It should be noted that alumina plays a transitional role, primarily responsible for adhering hafnium oxide. If the alumina layer is too thin, the hafnium oxide will not grow sufficiently. Since the dielectric constant of alumina is lower than that of hafnium oxide, the primary focus is on growing hafnium oxide. If the hafnium oxide layer is too thin, the device will be prone to breakdown; if it is too thick, the gate control capability will be significantly reduced.

[0045] Specifically, the top gate material is Ni / Au, with Ni having a thickness of 15-25nm and Au having a thickness of 10-20nm.

[0046] It should be noted that if the top gate 5 is too thin, it cannot be guaranteed that the metal can adhere to the surface of the top gate dielectric layer 4 and form a film; if it is too thick, it will hinder the device from being made thin.

[0047] Specifically, the transistor's on-state current is 49.67-56.3 μA / μm, for example, 49.67 μA / μm, 51.0 μA / μm, 52.0 μA / μm, 53.0 μA / μm, 54.0 μA / μm, 55.0 μA / μm, 56.0 μA / μm, 56.3 μA / μm, and the contact resistance is ≤500 Ω·μm, for example, 500 Ω·μm, 490 Ω·μm, 495 Ω·μm, 480 Ω·μm.

[0048] Specifically, such as Figure 1 As shown, the back gate dielectric layer 2 covers the upper surface and the left and right sides of the back gate 1, and the bottom surface of the back gate dielectric layer 2 is flush with the bottom surface of the back gate 1. The a-IGZO layer 3 covers part of the upper surface of the back gate dielectric layer 2. The upper surface of the left end of the a-IGZO layer 3 is covered by the source layer 6, and the upper surface of the right end of the a-IGZO layer 3 is covered by the drain layer 7. The source layer 6 and the drain layer 7 have the same structure and are arranged symmetrically on the left and right. The upper surface of the back gate dielectric layer 2 that is not covered by the a-IGZO layer 3 is covered by the source layer 6 and the drain layer 7. The source layer 6 and the drain layer 7 are both structures with a small thickness at the left and right ends and a large thickness in the middle. The source layer 6 and the drain layer 7 are divided into two cuboid structures by the plane where the upper surface of the a-IGZO layer 3 is located. In addition, a channel is provided between the source layer 6 and the drain layer 7. The channel and the upper surfaces of the source layer 6 and the drain layer 7 are all covered by the top gate dielectric layer 4, and the upper surface of the top gate dielectric layer 4 is partially covered by the top gate 5.

[0049] It should be noted that the top contact length L C It is the length of the contact between the source layer 6 or the drain layer 7 and the upper surface of the a-IGZO layer 3.

[0050] Secondly, the present invention provides a method for fabricating the aforementioned short-channel dual-gate IGZO thin-film transistor, comprising the following steps:

[0051] (1) Back gate 1 is fabricated on a silicon oxide substrate;

[0052] (2) A back gate dielectric layer 2 is prepared on the back gate 1;

[0053] (3) An a-IGZO layer 3 is prepared on the back gate dielectric layer 2;

[0054] (4) A source layer 6 and a drain layer 7 are prepared on the a-IGZO layer 3;

[0055] (5) A top gate dielectric layer 4 is prepared on the source layer 6, drain layer 7 and a-IGZO layer 3;

[0056] (6) A top gate 5 is fabricated on the top gate dielectric layer 4.

[0057] Specifically, in step (1), molybdenum is magnetron sputtered on a silicon oxide substrate, and a negative photoresist is coated on the molybdenum. The coating speed is 500 rpm for 5 seconds and then 4000 rpm for 60 seconds. The substrate is then baked at 145-155℃ for 2-4 minutes. After exposure, the substrate is baked at 115-125℃ for 1-3 minutes. The substrate is then immersed in a developer for 40-50 seconds, removed, rinsed with deionized water, and dried. The substrate is then etched using a dry etching method for 7-13 seconds to remove the molybdenum that is not protected by the photoresist. The substrate is then heated and immersed in RR41 photoresist remover at 65-75℃ for 35-45 minutes. The substrate is then removed, sonicated for 5-15 minutes, rinsed with deionized water, and dried to obtain the back gate.

[0058] It should be noted that the conditions for magnetron sputtering are: the gas is a mixture of Ar and O2, the flow rates are 10 sccm and 1.5 sccm respectively, and the power is 110 W.

[0059] Specifically, in step (2), at a temperature of 290-310℃, water is passed through 5 times, followed by TEMAH (tetra(methylethylamino)hafnium) and H2O, and hafnium oxide is atomically deposited on the back gate 1 as the bottom gate dielectric layer 2.

[0060] Specifically, in step (3), an a-IGZO thin film is first grown on the back gate dielectric layer 2 at room temperature by magnetron sputtering, and a negative resist is coated. The coating speed is 500 rpm for 5 seconds and then 4000 rpm for 60 seconds. The film is then baked at 145-155℃ for 2-4 minutes. After exposure, it is baked at 115-125℃ for 1-3 minutes. The film is then immersed in the developer for 40-50 seconds, removed, rinsed with deionized water, and dried to obtain a wafer for later use. Wet etching is then used. The wafer is immersed in 5% dilute nitric acid for 5-9 seconds to etch away the a-IGZO that is not protected by the photoresist. The wafer is then removed, rinsed with deionized water, and dried. The wafer is then immersed in acetone solution for 0.9-1.1 hours to remove the photoresist. Finally, the wafer is removed, rinsed three times with acetone, then rinsed twice with ethanol, and finally dried and stored to obtain the a-IGZO layer 3.

[0061] It should be noted that the conditions for magnetron sputtering are: the gas is a mixture of Ar and O2, the flow rates are 10 sccm and 1.5 sccm respectively, and the power is 110 W.

[0062] Specifically, in step (4), PMMA adhesive is coated on the a-IGZO layer 3. The coating speed is first 500 rpm for 5 seconds, then 5000 rpm for 60 seconds, so that the adhesive thickness is 110-130 nm. After baking at 175-185℃ for 1-3 minutes, electron beam lithography is used to obtain the lithographic wafer. Ni / Au is then grown directly on both sides of the lithographic wafer by electron beam evaporation. The electron beam evaporation conditions are: vacuum degree of 0.9 × 10⁻⁶. -9 -1.1×10 -9 The electron gun voltage was 10 kV and the evaporation rate was 0.7 Å / s. The substrate temperature was less than or equal to 35 degrees Celsius. After the metal was grown, the substrate was immersed in acetone solution for 5-7 hours. After the stripped area floated slightly, the surface was gently blown off with a dropper to strip the nickel and gold. The washing was repeated 2-3 times until there were no more nickel and gold debris floating in the acetone. The substrate was then washed twice with ethanol, dried and stored to obtain the drain layer 6 and the source layer 7.

[0063] Specifically, in step (4), the source layer 7 and the drain layer 6 are prepared by electron beam evaporation, and the vacuum degree in the electron beam evaporation is 0.9 × 10⁻⁶. -9 ~1.1×10 -9 torr.

[0064] Specifically, in step (5), the preparation of the top gate dielectric layer 4 on the source layer 6, drain layer 7 and a-IGZO layer 3 is as follows: first, TMA is passed through 5 times and then water is passed through to grow alumina, then water is passed through 5 times and then TMAH is passed through to grow hafnium oxide, and the top gate dielectric layer 4 is atomically deposited on the source layer 6, drain layer 7 and a-IGZO layer 3.

[0065] Specifically, in step (6), a negative photoresist is first coated on the top gate dielectric layer 4. The coating speed is 500 rpm for 5 seconds, then 4000 rpm for 60 seconds. The substrate is then baked at 140-160℃ for 2-4 minutes. After exposure, it is baked at 115-125℃ for 1-3 minutes. The substrate is then immersed in developer for 40-50 minutes, removed, rinsed with deionized water, and dried to obtain a wafer partially uncovered by photoresist. Ni / Au is then grown on the wafer partially uncovered by photoresist through electron beam evaporation. The electron beam evaporation conditions are: vacuum degree: 4×10 -7 Torr, evaporation rate 0.7 Å / s, electron gun voltage 10 kV, substrate temperature less than or equal to 35 degrees Celsius, soak in acetone solution for 1 hour until the entire stripped area floats up, gently blow the surface with a dropper to strip the titanium, repeat the cleaning 2-3 times until no titanium fragments float in the acetone, then clean with ethanol twice, blow dry, and store.

[0066] The dual-gate IGZO thin-film transistor prepared by the method of the present invention has a top contact length L between the drain layer 6 and the source layer 7. C The channel is relatively short, reaching 40-44nm, with a channel length L. CH It is relatively short, reaching 30-36nm, with an on-state current of 49.67-56.3μA / μm and a contact resistance ≤500Ω·μm.

[0067] Example 1

[0068] like Figure 1 As shown, this embodiment of a short-channel dual-gate IGZO thin-film transistor includes, from bottom to top, a back gate 1, a back gate dielectric layer 2, an a-IGZO layer 3, a top gate dielectric layer 4, and a top gate 5, which are stacked sequentially.

[0069] A source layer 6 is disposed between the upper surface of the left end of the a-IGZO layer 3 and the top gate dielectric layer 4, and a drain layer 6 is disposed between the upper surface of the right end of the a-IGZO layer 3 and the top gate dielectric layer 4.

[0070] A channel is provided between the source layer 6 and the drain layer 7, and the length of the channel is L. CH The top contact length L between the drain layer 6 and the source layer 7 is 30nm. C Both are 40nm;

[0071] The back gate 1 is made of molybdenum and has a thickness of 25nm.

[0072] The back gate dielectric layer 2 is made of hafnium oxide and has a thickness of 7 nm;

[0073] The source and drain layers are both made of Ni / Au, with a Ni thickness of 18nm and an Au thickness of 13nm.

[0074] The top gate dielectric layer is made of Al2O3 / HfO2, with the Al2O3 layer having a thickness of 1 nm and the HfO2 layer having a thickness of 6 nm.

[0075] The top gate material is Ni / Au, with Ni having a thickness of 15nm and Au having a thickness of 10nm.

[0076] The transistor fabrication method in this embodiment is as follows:

[0077] (1) Fabrication of back gate 1 on silicon oxide substrate

[0078] Molybdenum was magnetron sputtered onto a silicon oxide substrate. The magnetron sputtering conditions were as follows: the gas was a mixture of Ar and O2, with flow rates of 10 sccm and 1.5 sccm, respectively, and the power was 110 W. A negative photoresist of 1500 was coated on the molybdenum at a rotation speed of 500 rpm for 5 seconds and then 4000 rpm for 60 seconds. The substrate was then baked at 145 °C for 2 minutes, exposed, baked at 115 °C for 1 minute, immersed in developer for 40 seconds, removed, rinsed with deionized water, and dried. Dry etching was performed for 7 seconds to etch away the molybdenum that was not protected by the photoresist. The substrate was then heated and immersed in RR41 photoresist remover at 65 °C for 35 minutes, removed, sonicated for 5 minutes, rinsed with deionized water, and dried to obtain the back gate.

[0079] (2) Fabricate a back gate dielectric layer 2 on the back gate 1.

[0080] At a temperature of 290℃, water is passed through 5 times, followed by TEMAH and H2O, and hafnium oxide is atomically deposited on the back gate 1 as the bottom gate dielectric layer 2.

[0081] (3) Prepare an a-IGZO layer 3 on the back gate dielectric layer 2.

[0082] First, an a-IGZO thin film is grown on the back gate dielectric layer 2 at room temperature by magnetron sputtering. A negative resist is then coated at a rotation speed of 500 rpm for 5 seconds, followed by 4000 rpm for 60 seconds. The film is then baked at 145°C for 2 minutes, exposed, and baked at 115°C for 1 minute. It is then immersed in a developer for 40 seconds, removed, rinsed with deionized water, and dried to obtain a wafer for later use. Next, a wet etching process is used. The wafer is immersed in 5% dilute nitric acid for 5 seconds to etch away the a-IGZO layer not protected by the photoresist. It is then removed, rinsed with deionized water, and dried. Finally, it is immersed in acetone solution for 0.9 hours to remove the photoresist. The wafer is then rinsed three times with acetone, then twice with ethanol, and finally dried and stored to obtain a-IGZO layer 3.

[0083] (4) The source layer 6 and drain layer 7 are fabricated on the a-IGZO layer 3.

[0084] PMMA adhesive was coated onto the a-IGZO layer 3. The coating speed was first 500 rpm for 5 seconds, then 5000 rpm for 60 seconds, resulting in an adhesive thickness of 110 nm. After baking at 175 °C for 1 minute, electron beam lithography was performed to obtain the lithographic wafer. Ni / Au was then grown directly on both sides of the lithographic wafer using electron beam evaporation. The electron beam evaporation conditions were: vacuum degree of 0.9 × 10⁻⁶. -9 The electron gun voltage was 10 kV and the substrate temperature was less than or equal to 35 degrees Celsius. After the metal was grown, the substrate was immersed in acetone solution for 5 hours. After the stripped area floated slightly, the surface was gently blown with a dropper to strip the nickel and gold. The washing was repeated 2-3 times until there were no more nickel and gold debris floating in the acetone. The substrate was then washed twice with ethanol, dried and stored to obtain the drain layer 6 and the source layer 7.

[0085] (5) A top gate dielectric layer 4 is fabricated on the source layer 6, drain layer 7 and a-IGZO layer 3.

[0086] The preparation of the top gate dielectric layer 4 on the source layer 6, drain layer 7 and a-IGZO layer 3 is specifically as follows: first, TMA is passed through 5 times and then water is passed through to grow alumina; then, water is passed through 5 times and then TMAH is passed through to grow hafnium oxide; and the top gate dielectric layer 4 is atomically deposited on the source layer 6, drain layer 7 and a-IGZO layer 3.

[0087] (6) Fabricate the top gate 5 on the top gate dielectric layer 4.

[0088] First, a negative photoresist 1500 is coated onto the top gate dielectric layer 4. The coating speed is 500 rpm for 5 seconds, then 4000 rpm for 60 seconds. The substrate is then baked at 140℃ for 2 minutes, exposed, and baked at 115℃ for 1 minute. It is then immersed in developer for 40 minutes, removed, rinsed with deionized water, and dried to obtain a wafer partially uncovered by photoresist. Ni / Au is then grown on this partially uncovered wafer using electron beam evaporation. The electron beam evaporation conditions are: vacuum degree: 4 × 10⁻⁶. -7 Torr, evaporation rate 0.7 Å / s, electron gun voltage 10 kV, substrate temperature less than or equal to 35 degrees Celsius, soak in acetone solution for 1 hour until the entire stripped area floats up, gently blow the surface with a dropper to strip the titanium, repeat the cleaning 2-3 times until no titanium fragments float in the acetone, then clean with ethanol twice, blow dry, and store.

[0089] Example 2

[0090] This embodiment provides a short-channel dual-gate IGZO thin-film transistor, which includes, from bottom to top, a back gate 1, a back gate dielectric layer 2, an a-IGZO layer 3, a top gate dielectric layer 4, and a top gate 5, which are sequentially stacked.

[0091] A source layer 6 is disposed between the upper surface of the left end of the a-IGZO layer 3 and the top gate dielectric layer 4, and a drain layer 6 is disposed between the upper surface of the right end of the a-IGZO layer 3 and the top gate dielectric layer 4.

[0092] A channel is provided between the source layer 6 and the drain layer 7, and the length of the channel is L. CH The top contact length L between the drain layer 6 and the source layer 7 is 36nm. C Both are 44nm.

[0093] The back gate 1 is made of molybdenum and has a thickness of 20nm.

[0094] The back gate dielectric layer 2 is made of hafnium oxide and has a thickness of 5 nm;

[0095] The source and drain layers are both made of Ni / Au, with a Ni thickness of 20nm and an Au thickness of 15nm.

[0096] The top gate dielectric layer is made of Al2O3 / HfO2, with Al2O3 having a thickness of 2nm and HfO2 having a thickness of 8nm.

[0097] The top gate material is Ni / Au, with Ni having a thickness of 20nm and Au having a thickness of 15nm.

[0098] The transistor fabrication method in this embodiment is as follows:

[0099] (1) Fabrication of back gate 1 on silicon oxide substrate

[0100] Molybdenum was magnetron sputtered onto a silicon oxide substrate. The magnetron sputtering conditions were as follows: the gas was a mixture of Ar and O2, with flow rates of 10 sccm and 1.5 sccm, respectively, and the power was 110 W. A negative photoresist of 1500 was coated on the molybdenum at a rotation speed of 500 rpm for 5 seconds and then 4000 rpm for 60 seconds. The substrate was then baked at 150°C for 3 minutes, exposed, and baked at 120°C for 2 minutes. The substrate was then immersed in a developer for 45 seconds, removed, rinsed with deionized water, and dried. Dry etching was performed for 10 seconds to etch away the molybdenum that was not protected by the photoresist. The substrate was then heated and immersed in RR41 photoresist remover at 70°C for 40 minutes, removed, sonicated for 5 minutes, rinsed with deionized water, and dried to obtain the back gate.

[0101] (2) Fabricate a back gate dielectric layer 2 on the back gate 1.

[0102] At a temperature of 300℃, water is passed through 5 times, followed by TEMAH and H2O, and hafnium oxide is atomically deposited on the back gate 1 as the bottom gate dielectric layer 2.

[0103] (3) Prepare an a-IGZO layer 3 on the back gate dielectric layer 2.

[0104] First, an a-IGZO thin film is grown on the back gate dielectric layer 2 at room temperature by magnetron sputtering. A negative resist is then coated at 500 rpm for 5 seconds, followed by 4000 rpm for 60 seconds. The film is then baked at 150°C for 3 minutes, exposed, and then baked at 120°C for 2 minutes. It is then immersed in a developer for 45 seconds, removed, rinsed with deionized water, and dried to obtain a wafer for later use. Next, a wet etching process is used. The wafer is immersed in 5% dilute nitric acid for 7 seconds to etch away the a-IGZO layer not protected by the photoresist. It is then removed, rinsed with deionized water, and dried. Finally, it is immersed in acetone solution for 1 hour to remove the photoresist. The wafer is then rinsed three times with acetone, then twice with ethanol, and finally dried and stored to obtain the a-IGZO layer 3.

[0105] (4) The source layer 6 and drain layer 7 are fabricated on the a-IGZO layer 3.

[0106] PMMA adhesive was coated onto the a-IGZO layer 3. The coating speed was first 500 rpm for 5 seconds, then 5000 rpm for 60 seconds, resulting in an adhesive thickness of 120 nm. After baking at 180 °C for 2 minutes, electron beam lithography was performed to obtain the lithographic wafer. Ni / Au was then grown directly on both sides of the lithographic wafer using electron beam evaporation. The electron beam evaporation conditions were: vacuum degree 1 × 10⁻⁶. -9 The electron gun voltage was 10 kV and the substrate temperature was less than or equal to 35 degrees Celsius. After the metal was grown, the substrate was immersed in acetone solution for 6 hours. After the stripped area floated slightly, the surface was gently blown with a dropper to strip the nickel and gold. The washing was repeated 2-3 times until there were no more nickel and gold debris floating in the acetone. The substrate was then washed twice with ethanol, dried and stored to obtain the drain layer 6 and the source layer 7.

[0107] (5) A top gate dielectric layer 4 is fabricated on the source layer 6, drain layer 7 and a-IGZO layer 3.

[0108] The preparation of the top gate dielectric layer 4 on the source layer 6, drain layer 7 and a-IGZO layer 3 is specifically as follows: first, TMA is passed through 5 times and then water is passed through to grow alumina; then, water is passed through 5 times and then TMAH is passed through to grow hafnium oxide; and the top gate dielectric layer 4 is atomically deposited on the source layer 6, drain layer 7 and a-IGZO layer 3.

[0109] (6) Fabricate the top gate 5 on the top gate dielectric layer 4.

[0110] First, a negative photoresist layer 1500 was coated onto the top gate dielectric layer 4. The coating speed was initially 500 rpm for 5 seconds, then 4000 rpm for 60 seconds. The layer was then baked at 150°C for 3 minutes, exposed, and then baked at 120°C for 2 minutes. After immersion in developer for 45 minutes, the layer was removed, rinsed with deionized water, and dried to obtain a wafer partially uncovered by photoresist. Ni / Au was then grown on this partially uncovered wafer using electron beam evaporation. The electron beam evaporation conditions were: vacuum degree: 4 × 10⁻⁶. -7 Torr, evaporation rate 0.7 Å / s, electron gun voltage 10 kV, substrate temperature less than or equal to 35 degrees Celsius, soak in acetone solution for 1 hour until the entire stripped area floats up, gently blow the surface with a dropper to strip the titanium, repeat the cleaning 2-3 times until no titanium fragments float in the acetone, then clean with ethanol twice, blow dry, and store.

[0111] Example 3

[0112] This embodiment provides a short-channel dual-gate IGZO thin-film transistor, which includes, from bottom to top, a back gate 1, a back gate dielectric layer 2, an a-IGZO layer 3, a top gate dielectric layer 4, and a top gate 5, which are sequentially stacked.

[0113] A source layer 6 is disposed between the upper surface of the left end of the a-IGZO layer 3 and the top gate dielectric layer 4, and a drain layer 6 is disposed between the upper surface of the right end of the a-IGZO layer 3 and the top gate dielectric layer 4.

[0114] A channel is provided between the source layer 6 and the drain layer 7, and the length of the channel is L. CH The top contact length L between the drain layer 6 and the source layer 7 is 33nm. C Both are 42nm.

[0115] The back gate 1 is made of molybdenum and has a thickness of 30nm.

[0116] The back gate dielectric layer 2 is made of hafnium oxide and has a thickness of 10 nm;

[0117] The source and drain layers are both made of Ni / Au, with a Ni thickness of 22nm and an Au thickness of 17nm.

[0118] The top gate dielectric layer is made of Al2O3 / HfO2, with Al2O3 having a thickness of 3nm and HfO2 having a thickness of 10nm.

[0119] The top gate material is Ni / Au, with Ni having a thickness of 25nm and Au having a thickness of 20nm.

[0120] The transistor fabrication method in this embodiment is as follows:

[0121] (1) Fabrication of back gate 1 on silicon oxide substrate

[0122] Molybdenum was magnetron sputtered onto a silicon oxide substrate. The magnetron sputtering conditions were as follows: the gas was a mixture of Ar and O2, with flow rates of 10 sccm and 1.5 sccm, respectively, and the power was 110 W. A negative photoresist of 1500 was coated on the molybdenum at a rotation speed of 500 rpm for 5 seconds and then 4000 rpm for 60 seconds. The substrate was then baked at 155°C for 3 minutes, exposed, and then baked at 125°C for 3 minutes. After exposure, the substrate was immersed in a developer for 50 seconds, removed, rinsed with deionized water, and dried. Dry etching was performed for 13 seconds to etch away the molybdenum that was not protected by the photoresist. The substrate was then heated and immersed in RR41 photoresist remover at 75°C for 45 minutes, removed, sonicated for 15 minutes, rinsed with deionized water, and dried to obtain the back gate.

[0123] (2) Fabricate a back gate dielectric layer 2 on the back gate 1.

[0124] At a temperature of 310℃, water is passed through 5 times, followed by TEMAH and H2O, and hafnium oxide is atomically deposited on the back gate 1 as the bottom gate dielectric layer 2.

[0125] (3) Prepare an a-IGZO layer 3 on the back gate dielectric layer 2.

[0126] First, an a-IGZO thin film is grown on the back gate dielectric layer 2 at room temperature by magnetron sputtering. A negative resist is then coated at 500 rpm for 5 seconds, followed by 4000 rpm for 60 seconds. The film is then baked at 155°C for 4 minutes, exposed, and then baked at 125°C for 1-3 minutes. It is then immersed in a developer for 50 seconds, removed, rinsed with deionized water, and dried to obtain a wafer for later use. Next, a wet etching process is used. The wafer is immersed in 5% dilute nitric acid for 9 seconds to etch away the a-IGZO layer not protected by the photoresist. It is then removed, rinsed with deionized water, and dried. Finally, it is immersed in acetone solution for 1.1 hours to remove the photoresist. The wafer is then rinsed three times with acetone, then twice with ethanol, and finally dried and stored to obtain the a-IGZO layer 3.

[0127] (4) The source layer 6 and drain layer 7 are fabricated on the a-IGZO layer 3.

[0128] PMMA adhesive was coated onto the a-IGZO layer 3. The coating speed was first 500 rpm for 5 seconds, then 5000 rpm for 60 seconds, resulting in an adhesive thickness of 130 nm. After baking at 185 °C for 3 minutes, electron beam lithography was performed to obtain the lithographic wafer. Ni / Au was then grown directly on both sides of the lithographic wafer using electron beam evaporation. The electron beam evaporation conditions were: vacuum degree of 1.1 × 10⁻⁶. -9The electron gun voltage was 10 kV and the substrate temperature was less than or equal to 35 degrees Celsius. After the metal was grown, the substrate was immersed in acetone solution for 7 hours. After the stripped area floated slightly, the surface was gently blown with a dropper to strip the nickel and gold. The washing was repeated 2-3 times until there were no more nickel and gold debris floating in the acetone. The substrate was then washed twice with ethanol, dried and stored to obtain the drain layer 6 and the source layer 7.

[0129] (5) A top gate dielectric layer 4 is fabricated on the source layer 6, drain layer 7 and a-IGZO layer 3.

[0130] The preparation of the top gate dielectric layer 4 on the source layer 6, drain layer 7 and a-IGZO layer 3 is specifically as follows: first, TMA is passed through 5 times and then water is passed through to grow alumina; then, water is passed through 5 times and then TMAH is passed through to grow hafnium oxide; and the top gate dielectric layer 4 is atomically deposited on the source layer 6, drain layer 7 and a-IGZO layer 3.

[0131] (6) Fabricate the top gate 5 on the top gate dielectric layer 4.

[0132] First, a negative photoresist layer 1500 was coated on the top gate dielectric layer 4. The coating speed was initially 500 rpm for 5 seconds, then 4000 rpm for 60 seconds. The layer was then baked at 160℃ for 4 minutes, exposed, and then baked at 125℃ for 3 minutes. After immersion in developer for 50 minutes, the layer was removed, rinsed with deionized water, and dried to obtain a wafer partially uncovered by photoresist. Ni / Au was then grown on this partially uncovered wafer using electron beam evaporation. The electron beam evaporation conditions were: vacuum degree: 4 × 10⁻⁶. -7 Torr, evaporation rate 0.7 Å / s, electron gun voltage 10 kV, substrate temperature less than or equal to 35 degrees Celsius, soak in acetone solution for 1 hour until the entire stripped area floats up, gently blow the surface with a dropper to strip the titanium, repeat the cleaning 2-3 times until no titanium fragments float in the acetone, then clean with ethanol twice, blow dry, and store.

[0133] Comparative Example 1

[0134] The transistor structure and fabrication method of this comparative example are the same as those of Example 2, except that the top contact length L of the drain layer 6 and the source layer 7 is different. C Both are 39nm.

[0135] Comparative Example 2

[0136] The transistor structure and fabrication method of this comparative example are the same as those of Example 2, except that the top contact length L of the drain layer 6 and the source layer 7 is different. C Both are 35nm.

[0137] Comparative Example 3

[0138] The transistor structure and fabrication method of this comparative example are the same as those of Example 2, except that the source layer 6 and drain layer 7 are replaced with Ti / Au.

[0139] Comparative Example 4

[0140] The transistor structure and fabrication method of this comparative example are the same as those of Example 2, except that the electron beam evaporation vacuum degree is 4 × 10⁻⁶ during the fabrication of the source layer 6 and drain layer 7. -7 torr.

[0141] Experimental Example 1

[0142] The electrical performance of the transistors prepared in Examples 1-3 and Comparative Examples 1-3 was tested, and the results are shown in Table 1.

[0143] Table 1

[0144]

[0145] As can be seen from the results in Table 1, the top contact length L of the present invention... C At 40-44 nm, it is already close to the limit of miniaturization. Comparing Comparative Examples 1-2 with Example 2, it can be seen that when the top contact length L... C As the size continues to shrink, the performance of the transistors degrades significantly.

[0146] Compared with Example 2, Comparative Example 3 shows that the source layer 6 and drain layer 7 of the present invention have the best matching nickel work function, while other materials will significantly increase the contact resistance.

[0147] Compared with Example 2, Comparative Example 4 shows that the high vacuum growth of nickel-gold required by the present invention can reduce contact resistance and increase on-state current.

[0148] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A short-channel dual-gate IGZO thin-film transistor, characterized in that, The transistor comprises, from bottom to top, a back gate, a back gate dielectric layer, an a-IGZO layer, a top gate dielectric layer, and a top gate, which are stacked sequentially. A source layer is disposed between the upper surface of the left end of the a-IGZO layer and the top gate dielectric layer, and a drain layer is disposed between the upper surface of the right end of the a-IGZO layer and the top gate dielectric layer. A channel is provided between the source layer and the drain layer, and the length of the channel is L. CH The top contact length L between the drain and source layers is 31-36 nm. C All are 40-44nm; The upper surface of the back gate dielectric layer covered by the a-IGZO layer, the upper surface of the left end of the a-IGZO layer is covered by the source layer, the upper surface of the right end of the a-IGZO layer is covered by the drain layer, the source layer and drain layer have the same structure and are arranged symmetrically on the left and right, and the upper surfaces of the channel, source layer and drain layer are all covered by the top gate dielectric layer. The source and drain layers were prepared by electron beam evaporation, with a vacuum level of 0.9 × 10⁻⁶ during the evaporation process. -9 ~1.1×10 -9 torr; The transistor has an on-state current of 49.67-56.3 μA / μm and a contact resistance of ≤500 Ω·μm.

2. The short-channel dual-gate IGZO thin-film transistor according to claim 1, characterized in that, The back gate material is molybdenum with a thickness of 20-30 nm.

3. A short-channel dual-gate IGZO thin-film transistor according to claim 1 or 2, characterized in that, The back gate dielectric layer is made of hafnium oxide and has a thickness of 5-10 nm.

4. A short-channel dual-gate IGZO thin-film transistor according to claim 1 or 2, characterized in that, The source and drain layers are both made of Ni / Au, with Ni thickness of 18-22nm and Au thickness of 13-17nm.

5. A short-channel dual-gate IGZO thin-film transistor according to claim 1, characterized in that, The top gate dielectric layer is made of Al2O3 / HfO2, with the Al2O3 having a thickness of 1-3 nm and the HfO2 having a thickness of 6-10 nm.

6. A short-channel dual-gate IGZO thin-film transistor according to claim 1, characterized in that, The top gate material is Ni / Au, with Ni having a thickness of 15-25nm and Au having a thickness of 10-20nm.

7. A method for fabricating a short-channel dual-gate IGZO thin-film transistor according to any one of claims 1-6, characterized in that, Includes the following steps: (1) Fabrication of a back gate on a silicon oxide substrate; (2) A back-gate dielectric layer is prepared on the back gate; (3) An a-IGZO layer is prepared on the back gate dielectric layer; (4) A source layer and a drain layer are fabricated on the a-IGZO layer; (5) A top gate dielectric layer is prepared on the source layer, drain layer and a-IGZO layer; (6) A top gate is fabricated on the top gate dielectric layer.

8. The preparation method according to claim 7, characterized in that, In step (4), the source layer and drain layer are prepared by electron beam evaporation, and the vacuum degree during electron beam evaporation is 0.9 × 10⁻⁶. -9 ~1.1×10 -9 torr.

9. The preparation method according to claim 7, characterized in that, In step (5), the source layer and drain layer are both made of Ni / Au.

Images