Low power high electron mobility transistor and method of making the same

Abstract

The embodiment of the present application provides a kind of low-energy HEMT and its manufacturing method, wherein, low-energy HEMT includes at least one transistor unit, at least one transistor unit includes: gate (22);Source (4);Drain (3);First P-type gallium nitride area (51) adjoining source (4);First N-type gallium nitride area (61) is arranged between first P-type gallium nitride area (51) and gate (22);Second N-type gallium nitride area (62) adjoining drain (3);Second P-type gallium nitride area (52) is arranged between second N-type gallium nitride area (62) and gate (22). The low-energy HEMT and its manufacturing method provided by the embodiment of the present application can control the on-resistance and off-resistance of gate by controlling gate voltage, can well control switching speed in operation process, and can reduce switching loss of device by reducing electromagnetic interference, and threshold voltage is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a low-power high electron mobility transistor (HEMT) and its fabrication method. Background Technology

[0002] Traditional gallium nitride high electron mobility transistors (GaN HEMTs) are known for their ultra-high electron mobility, but in their applications, if the gate voltage changes too quickly (dv / dt), they will be subject to electromagnetic interference (EMI), leading to increased switching losses in the device. Summary of the Invention

[0003] This invention provides a low-power HEMT and its manufacturing method to solve the technical problem of high switching losses in existing HEMTs.

[0004] In a first aspect, embodiments of the present invention provide a low-power HEMT, comprising at least one transistor unit, the at least one transistor unit comprising:

[0005] Gate;

[0006] Source pole;

[0007] Drain;

[0008] The first p-type gallium nitride region adjacent to the source;

[0009] A first N-type gallium nitride region disposed between a first P-type gallium nitride region and a gate;

[0010] The second N-type gallium nitride region adjacent to the drain;

[0011] A second P-type gallium nitride region is arranged between the second N-type gallium nitride region and the gate.

[0012] In some embodiments, the first P-type gallium nitride region, the first N-type gallium nitride region, and the gate constitute a normally open P-channel.

[0013] In some embodiments, the second N-type gallium nitride region, the second P-type gallium nitride region, and the gate constitute a normally off N-channel junction field-effect transistor.

[0014] In some embodiments, the doping concentration of the junction field-effect transistor is greater than 0.5E13cm. -3 And less than 7.5E13cm -3 .

[0015] In some embodiments, the first P-type gallium nitride region has a thickness between 5 nanometers and 100 nanometers, particularly between 10 nanometers and 50 nanometers;

[0016] The second N-type gallium nitride region has a thickness between 5 nanometers and 100 nanometers, and particularly between 10 nanometers and 50 nanometers;

[0017] The first N-type gallium nitride region has a thickness between 7 nanometers and 100 nanometers, and particularly between 12 nanometers and 50 nanometers;

[0018] The second P-type gallium nitride region has a thickness between 7 nanometers and 100 nanometers, and particularly between 12 nanometers and 50 nanometers.

[0019] Secondly, embodiments of the present invention provide a method for manufacturing a low-power HEMT, comprising:

[0020] A first trench is formed on the first surface of the first passivation layer;

[0021] P-type gallium nitride is filled in the first trench, and a layer of P-type gallium nitride is deposited on the first surface of the first passivation layer to form a first P-type gallium nitride region;

[0022] A passivation layer is deposited on the first surface of the first P-type gallium nitride region to form a second passivation layer;

[0023] A second trench and a third trench are formed on the first surface of the second passivation layer, respectively;

[0024] N-type gallium nitride is filled in the second trench to form a first N-type gallium nitride region; a layer of N-type gallium nitride is deposited at the bottom of the third trench to form a second N-type gallium nitride region. The thickness of the second N-type gallium nitride region is suitable for the third trench, so that the first remaining trench is retained after the second N-type gallium nitride region is formed.

[0025] Fill the first remaining trench with passivation material;

[0026] A fourth trench is formed on the first surface of the second passivation layer;

[0027] P-type gallium nitride is filled into the fourth trench to form a second P-type gallium nitride region;

[0028] A fifth trench and a sixth trench are formed on the first surface of the second passivation layer, respectively;

[0029] The source electrode is formed in the fifth trench; the drain electrode is formed in the sixth trench.

[0030] A passivation material is deposited on the first surface of the second passivation layer to form a third passivation layer;

[0031] A seventh trench is formed on the first surface of the third passivation layer;

[0032] The gate is formed in the seventh trench.

[0033] Thirdly, embodiments of the present invention provide a low-power HEMT, comprising at least one transistor unit, wherein the at least one transistor unit includes:

[0034] Gate;

[0035] Source pole;

[0036] Drain;

[0037] The second N-type gallium nitride region adjacent to the source;

[0038] A second P-type gallium nitride region is disposed between the second N-type gallium nitride region and the gate;

[0039] The first P-type gallium nitride region adjacent to the drain;

[0040] A first N-type gallium nitride region is disposed between a first P-type gallium nitride region and a gate.

[0041] In some embodiments, the first P-type gallium nitride region, the first N-type gallium nitride region, and the gate constitute a normally open P-channel junction field-effect transistor.

[0042] In some embodiments, the second N-type gallium nitride region, the second P-type gallium nitride region, and the gate constitute a normally off N-channel junction field-effect transistor.

[0043] Fourthly, embodiments of the present invention provide a method for manufacturing a low-power HEMT, comprising:

[0044] A first trench is formed on the first surface of the first passivation layer;

[0045] N-type gallium nitride is filled in the first trench, and an N-type gallium nitride layer is deposited on the first surface of the first passivation layer to form a second N-type gallium nitride region;

[0046] A passivation layer is deposited on the first surface of the second N-type gallium nitride region to form a second passivation layer;

[0047] A second trench and a third trench are formed on the first surface of the second passivation layer, respectively;

[0048] P-type gallium nitride is filled in the second trench to form a second P-type gallium nitride region; a layer of P-type gallium nitride is deposited at the bottom of the third trench to form a first P-type gallium nitride region. The thickness of the first P-type gallium nitride region is suitable for the third trench, so that after the first P-type gallium nitride region is formed, the first remaining trench is retained.

[0049] Fill the first remaining trench with passivation material;

[0050] A fourth trench is formed on the first surface of the second passivation layer;

[0051] N-type gallium nitride is filled into the fourth trench to form the first N-type gallium nitride region;

[0052] A fifth trench and a sixth trench are formed on the first surface of the second passivation layer, respectively;

[0053] The source electrode is formed in the fifth trench; the drain electrode is formed in the sixth trench.

[0054] A passivation material is deposited on the first surface of the second passivation layer to form a third passivation layer;

[0055] A seventh trench is formed on the first surface of the third passivation layer;

[0056] The gate is formed in the seventh trench.

[0057] The low-power HEMT and its fabrication method provided in this invention can control the gate's on-resistance and off-resistance by controlling the gate voltage. During operation, the switching rate can be well controlled, and the switching losses of the device can be reduced by reducing electromagnetic interference, thereby increasing the threshold voltage. Attached Figure Description

[0058] Figure 1 This is one of the structural schematic diagrams of a low-power HEMT provided in an embodiment of the present invention;

[0059] Figure 2 This is one of the structural schematic diagrams of a low-energy HEMT during the fabrication process of a low-energy HEMT, provided by an embodiment of the present invention;

[0060] Figure 3 This is a second schematic diagram of the structure of a low-energy HEMT during the fabrication process of a low-energy HEMT, provided by an embodiment of the present invention.

[0061] Figure 4 This is the third schematic diagram of the structure of a low-energy HEMT in the process of manufacturing a low-energy HEMT, as provided in an embodiment of the present invention.

[0062] Figure 5 This is the fourth schematic diagram of the structure of a low-energy HEMT in the process of manufacturing a low-energy HEMT, as provided in an embodiment of the present invention.

[0063] Figure 6 Fifth schematic diagram of the structure of a low-energy HEMT in the process of manufacturing a low-energy HEMT, provided by an embodiment of the present invention;

[0064] Figure 7 This is the sixth schematic diagram of the structure of a low-energy HEMT in the process of manufacturing a low-energy HEMT, as provided in an embodiment of the present invention.

[0065] Figure 8This is the seventh schematic diagram of the structure of a low-energy HEMT in the process of manufacturing a low-energy HEMT, as provided in an embodiment of the present invention.

[0066] Figure 9 This is the eighth schematic diagram of the structure of a low-energy HEMT in the process of manufacturing a low-energy HEMT, provided by an embodiment of the present invention.

[0067] Figure 10 This is the ninth schematic diagram of the structure of a low-energy HEMT in the process of manufacturing a low-energy HEMT, as provided in an embodiment of the present invention.

[0068] Figure 11 This is the tenth schematic diagram of the structure of a low-energy HEMT in the process of manufacturing a low-energy HEMT, as provided in an embodiment of the present invention.

[0069] Figure 12 This is eleventh of the structural schematic diagrams of a low-energy HEMT in the process of manufacturing a low-energy HEMT according to an embodiment of the present invention;

[0070] Figure 13 This is the twelfth schematic diagram of the structure of a low-energy HEMT in the process of manufacturing a low-energy HEMT, provided by an embodiment of the present invention;

[0071] Figure 14 A schematic diagram of the equivalent circuit of a low-power HEMT provided in an embodiment of the present invention;

[0072] Figure 15 This is a second schematic diagram of a low-energy HEMT provided in an embodiment of the present invention. Detailed Implementation

[0073] Traditional gallium nitride high electron mobility transistors (GaN HEMTs) are known for their ultra-high electron mobility, but in their applications, if the gate voltage changes too quickly (dv / dt), they will be subject to electromagnetic interference (EMI), leading to increased switching losses in the device.

[0074] P-gate HEMT devices are currently the most mainstream HEMT structure, but their large gate leakage current has limited their application in the power device market.

[0075] A common method to control the rate of change of the gate voltage is to increase the gate resistance, but this cannot be adjusted during operation.

[0076] Based on the above-mentioned technical problems, this invention proposes a novel low-power HEMT that controls the rate of change of gate voltage while reducing gate leakage current.

[0077] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0078] Figure 1 This is one of the structural schematic diagrams of a low-power HEMT provided in an embodiment of the present invention, such as... Figure 1 As shown, an embodiment of the present invention provides a low-power HEMT including at least one transistor unit, the at least one transistor unit comprising:

[0079] Gate 22;

[0080] Source 4;

[0081] Drain 3;

[0082] The first P-type gallium nitride region 51 adjacent to source 4;

[0083] A first N-type gallium nitride region 61 is disposed between a first P-type gallium nitride region 51 and a gate 22;

[0084] The second N-type gallium nitride region 62 adjacent to drain 3;

[0085] A second P-type gallium nitride region 52 is disposed between the second N-type gallium nitride region 62 and the gate 22.

[0086] Specifically, the gate 22 can be formed by deposition, and its thickness is between 5 nanometers (nm) and 100 nanometers, particularly between 10 nanometers and 50 nanometers. The gate 22 can comprise a metal, a metal alloy, a metal nitride, or a metal carbide. The metal can be titanium (Ti), molybdenum (Mo), or tantalum (Ta). The metal alloy can be TiAl or TiW. The metal nitride can be titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or molybdenum nitride (MoN). The carbide can be titanium carbide (TiC).

[0087] In some embodiments, the first P-type gallium nitride region 51, the first N-type gallium nitride region 61, and the gate 22 constitute a normally open P-channel.

[0088] In some embodiments, the second N-type gallium nitride region 62, the second P-type gallium nitride region 52, and the gate 22 constitute a normally off N-channel junction field-effect transistor.

[0089] In some embodiments, the doping concentration of the junction field-effect transistor is greater than 0.5E13cm. -3And less than 7.5E13cm -3 .

[0090] In some embodiments, the first p-type gallium nitride region 51 has a thickness between 5 nanometers and 100 nanometers, particularly between 10 nanometers and 50 nanometers;

[0091] The second N-type gallium nitride region 62 has a thickness between 5 nanometers and 100 nanometers, and particularly between 10 nanometers and 50 nanometers;

[0092] The first N-type gallium nitride region 61 has a thickness between 7 nanometers and 100 nanometers, and particularly between 12 nanometers and 50 nanometers;

[0093] The second P-type gallium nitride region 52 has a thickness between 7 nanometers and 100 nanometers, and particularly between 12 nanometers and 50 nanometers.

[0094] In some embodiments, the at least one transistor unit further includes:

[0095] Substrate 14;

[0096] nucleation7;

[0097] Buffer layer 9;

[0098] Barrier layer 20;

[0099] Nucleation 7 is arranged between substrate 14 and buffer layer 9;

[0100] Buffer layer 9 is arranged between nucleation layer 7 and barrier layer 20;

[0101] The barrier layer 20 is disposed between the buffer layer 9 and the first passivation layer 81.

[0102] Specifically, nucleation layer 7 may include aluminum nitride (AlN), buffer layer 9 may include gallium nitride (GaN), and barrier layer 20 may include aluminum gallium nitride (AlGaN).

[0103] The turn-on process of the low-power HEMT provided in this embodiment of the invention is as follows: A positive bias voltage is applied to the gate. After the gate bias reaches its turn-off voltage, the D-type junction field-effect transistor (JFET) is completely turned off. After the gate bias reaches the threshold voltage, the E-type JFET is turned on. Its N-region and P-type GaN (this P-type GaN is P-type GaN in contact with AlGaN) form a depletion region until the P-type GaN is depleted to the recovery of the two-dimensional electron gas (2DEG), and the low-power HEMT is turned on. The turn-off voltage of the D-type JFET is less than the turn-on voltage of the E-type JFET.

[0104] The turn-off process of the low-power HEMT provided in this embodiment of the invention is as follows: the gate voltage is zero, the E-type JFET is gradually turned off, the D-type JFET is gradually turned on, the P-type GaN potential is connected to the zero point of the source, and the low-power HEMT is turned off.

[0105] The low-power HEMT provided in this invention can control the gate's on-resistance and off-resistance by controlling the gate voltage. During operation, it can effectively control the switching rate, reduce device switching losses by reducing electromagnetic interference, and improve the threshold voltage.

[0106] The low-power HEMT provided in this invention eliminates the Schottky junction between the gate and P-type GaN in the traditional P-type gate structure, thereby significantly reducing the gate leakage current, increasing the gate withstand voltage, and improving the saturation current.

[0107] The low-power HEMT provided in this invention can achieve optimal loss reduction by controlling the changes in parameters such as the structural size, position, and doping concentration of D-type JFETs and E-type JFETs.

[0108] This invention also provides a method for manufacturing a low-power HEMT, the method comprising:

[0109] Step 01 Figure 2 This is one of the structural schematic diagrams of a low-energy HEMT during the fabrication process of a low-energy HEMT, as provided in an embodiment of the present invention. Figure 2 As shown, a first trench 8110 is formed on the first surface 8101 of the first passivation layer 81;

[0110] Step 02 Figure 3 This is a second schematic diagram of the structure of a low-energy HEMT during the fabrication process of a low-energy HEMT, as provided in an embodiment of the present invention. Figure 3 As shown, P-type gallium nitride is filled in the first trench 8110, and a layer of P-type gallium nitride is deposited on the first surface 8101 of the first passivation layer 81 to form the first P-type gallium nitride region 51.

[0111] Step 03 Figure 4 This is the third schematic diagram of the structure of a low-energy HEMT in the process of fabricating a low-energy HEMT, as provided in this embodiment of the invention. Figure 4 As shown, a passivation layer is deposited on the first surface 5101 of the first P-type gallium nitride region 51 to form a second passivation layer 82.

[0112] Step 04 Figure 5 This is the fourth schematic diagram of the structure of a low-energy HEMT in the process of fabricating a low-energy HEMT, as provided in this embodiment of the invention. Figure 5As shown, a second trench 8210 and a third trench 8220 are formed on the first surface 8201 of the second passivation layer 82, respectively;

[0113] Step 05 Figure 6 This is the fifth schematic diagram of the structure of a low-energy HEMT in the process of fabricating a low-energy HEMT according to an embodiment of the present invention, as shown in Figure 5. Figure 6 As shown, N-type gallium nitride is filled in the second trench 8210 to form a first N-type gallium nitride region 61; a layer of N-type gallium nitride is deposited at the bottom of the third trench 8220 to form a second N-type gallium nitride region 62. The thickness of the second N-type gallium nitride region 62 is suitable for the third trench 8220, so that after the second N-type gallium nitride region 62 is formed, the first remaining trench 8220' is retained.

[0114] Step 06 Figure 7 This is the sixth schematic diagram of the structure of a low-energy HEMT in the process of fabricating a low-energy HEMT, as provided in this embodiment of the invention. Figure 7 As shown, passivation material is filled in the first remaining trench 8220';

[0115] Step 07 Figure 8 This is the seventh schematic diagram of the structure of a low-energy HEMT in the process of fabricating a low-energy HEMT according to an embodiment of the present invention, as shown in Figure 7. Figure 8 As shown, a fourth trench 8230 is formed on the first surface 8201 of the second passivation layer 82;

[0116] Step 08 Figure 9 This is the eighth schematic diagram of the structure of a low-energy HEMT in the process of fabricating a low-energy HEMT, as provided in this embodiment of the invention. Figure 9 As shown, P-type gallium nitride is filled in the fourth trench 8230 to form a second P-type gallium nitride region 52;

[0117] Step 09 Figure 10 This is the ninth schematic diagram of the structure of a low-energy HEMT in the process of fabricating a low-energy HEMT, as provided in this embodiment of the invention. Figure 10 As shown, a fifth trench 8240 and a sixth trench 8250 are formed on the first surface 8201 of the second passivation layer 82, respectively;

[0118] Step 10 Figure 11 This is the tenth schematic diagram of the structure of a low-energy HEMT in the process of fabricating a low-energy HEMT according to an embodiment of the present invention. Figure 11 As shown, source 4 is formed in the fifth trench 8240; drain 3 is formed in the sixth trench 8250;

[0119] Step 11 Figure 12This is eleventh of the structural schematic diagrams of a low-energy HEMT in the process of fabricating a low-energy HEMT according to an embodiment of the present invention, as shown in the figure. Figure 12 As shown, a passivation material is deposited on the first surface 8201 of the second passivation layer 82 to form the third passivation layer 83;

[0120] Step 12 Figure 13 This is the twelfth schematic diagram of the structure of a low-energy HEMT in the process of fabricating a low-energy HEMT according to an embodiment of the present invention. Figure 13 As shown, a seventh trench 8310 is formed on the first surface 8301 of the third passivation layer 83;

[0121] Step 13: Form gate 22 in the seventh trench 8310 to obtain the following result. Figure 1 HEMT shown.

[0122] Figure 14 The equivalent circuit diagram of the low-power HEMT provided in the embodiments of the present invention is shown below. Figure 14 As shown, a normally-on (D-model) P-channel JFET is introduced between the gate and source, and a normally-off (E-model) N-channel JFET is introduced between the gate and drain. The method for fabricating a low-power HEMT provided in this embodiment of the invention produces a low-power HEMT that can control the gate's on-resistance and turn-off resistance by controlling the gate voltage. During operation, the switching rate can be well controlled, and the switching losses of the device are reduced by decreasing electromagnetic interference, thereby improving the threshold voltage.

[0123] This low-power HEMT eliminates the Schottky junction between the gate and P-type GaN in the traditional P-type gate structure, thereby significantly reducing the gate leakage current, increasing the gate breakdown voltage, and improving the saturation current.

[0124] This low-power HEMT can achieve optimal loss reduction by controlling the changes in parameters such as the structural size, position, and doping concentration of D-type JFETs and E-type JFETs.

[0125] The above embodiments of the present invention provide a normally-off low-power HEMT. By interchanged between the D-type JFET and the E-type JFET, the device can be converted into a normally-on low-power HEMT.

[0126] The structure and manufacturing method of a normally open low-power HEMT are described below:

[0127] Figure 15 This is a second schematic diagram of a low-power HEMT provided in an embodiment of the present invention, as shown below. Figure 15As shown, an embodiment of the present invention provides a low-power HEMT including at least one transistor unit, the at least one transistor unit comprising:

[0128] Gate 22;

[0129] Source 4;

[0130] Drain 3;

[0131] The second N-type gallium nitride region 62 adjacent to source 4;

[0132] A second P-type gallium nitride region 52 is disposed between the second N-type gallium nitride region 62 and the gate 22;

[0133] The first P-type gallium nitride region 51 adjacent to the drain 3;

[0134] A first N-type gallium nitride region 61 is arranged between a first P-type gallium nitride region 51 and a gate 22.

[0135] In some embodiments, the first P-type gallium nitride region 51, the first N-type gallium nitride region 61, and the gate 22 constitute a normally open P-channel junction field-effect transistor.

[0136] In some embodiments, the second N-type gallium nitride region 62, the second P-type gallium nitride region 52, and the gate 22 constitute a normally off N-channel junction field-effect transistor.

[0137] Specifically, the normally open low-energy HEMT provided in this embodiment of the invention can refer to the above-described normally closed low-energy HEMT embodiment and can achieve the same technical effect. Here, the parts and beneficial effects that are the same as those in the corresponding embodiments described above will not be described in detail.

[0138] This invention also provides a method for manufacturing a normally open low-power HEMT, the method comprising:

[0139] Step 01: A first trench 8110 is formed on the first surface 8101 of the first passivation layer 81;

[0140] Step 02: Fill the first trench 8110 with N-type gallium nitride and deposit a layer of N-type gallium nitride on the first surface 8101 of the first passivation layer 81 to form the second N-type gallium nitride region 62;

[0141] Step 03: Deposit a passivation layer on the first surface of the second N-type gallium nitride region 62 to form a second passivation layer 82;

[0142] Step 04: A second trench 8210 and a third trench 8220 are formed on the first surface 8201 of the second passivation layer 82, respectively;

[0143] Step 05: Fill the second trench 8210 with P-type gallium nitride to form a second P-type gallium nitride region 52; deposit a layer of P-type gallium nitride at the bottom of the third trench 8220 to form a first P-type gallium nitride region 51. The thickness of the first P-type gallium nitride region 51 is suitable for the third trench 8220, so that after the first P-type gallium nitride region 51 is formed, the first remaining trench 8220' is retained.

[0144] Step 06: Fill the first remaining trench 8220' with passivation material;

[0145] Step 07: A fourth trench 8230 is formed on the first surface 8201 of the second passivation layer 82;

[0146] Step 08: Fill the fourth trench 8230 with N-type gallium nitride to form the first N-type gallium nitride region 61;

[0147] Step 09: A fifth trench 8240 and a sixth trench 8250 are formed on the first surface 8201 of the second passivation layer 82, respectively;

[0148] Step 10: Form source 4 in the fifth trench 8240; form drain 3 in the sixth trench 8250;

[0149] Step 11: Deposit a passivation layer on the first surface 8201 of the second passivation layer 82 to form the third passivation layer 83;

[0150] Step 12: Form a seventh trench 8310 on the first surface 8301 of the third passivation layer 83;

[0151] Step 13: Form gate 22 in the seventh trench 8310.

[0152] Specifically, the method for manufacturing a normally open low-power HEMT provided in this embodiment of the invention can refer to the embodiment of the method for manufacturing a normally closed low-power HEMT described above, and can achieve the same technical effect. Here, the parts and beneficial effects that are the same as those in the corresponding embodiments described above will not be described in detail.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-power, high-electron-mobility transistor, characterized in that, Includes at least one transistor unit, said at least one transistor unit comprising: Gate (22); Source (4); Drain (3); The first P-type gallium nitride region (51) of the contact source electrode (4); A first N-type gallium nitride region (61) is arranged between a first P-type gallium nitride region (51) and a gate (22); The second N-type gallium nitride region (62) of the contact drain (3); A second P-type gallium nitride region (52) is arranged between the second N-type gallium nitride region (62) and the gate (22); The first P-type gallium nitride region (51), the first N-type gallium nitride region (61), and the gate (22) constitute a normally open P-channel junction field-effect transistor; The second N-type gallium nitride region (62), the second P-type gallium nitride region (52), and the gate (22) constitute a normally off N-channel junction field-effect transistor.

2. The low-energy-consumption, high-electron-mobility transistor according to claim 1, characterized in that, The doping concentration of a junction field-effect transistor is greater than 0.5E13cm. -3 And less than 7.5E13cm -3 .

3. The low-energy-consumption, high-electron-mobility transistor according to claim 1, characterized in that, The first P-type gallium nitride region (51) has a thickness between 5 nanometers and 100 nanometers; The second N-type gallium nitride region (62) has a thickness between 5 nanometers and 100 nanometers; The first N-type gallium nitride region (61) has a thickness between 7 nanometers and 100 nanometers; The second P-type gallium nitride region (52) has a thickness between 7 nanometers and 100 nanometers.

4. A method for fabricating a low-power, high-electron-mobility transistor, characterized in that, include: A first trench (8110) is formed on the first surface (8101) of the first passivation layer (81). P-type gallium nitride is filled in the first trench (8110), and a layer of P-type gallium nitride is deposited on the first surface (8101) of the first passivation layer (81) to form the first P-type gallium nitride region (51). A passivation layer is deposited on the first surface (5101) of the first P-type gallium nitride region (51) to form a second passivation layer (82). A second trench (8210) and a third trench (8220) are formed on the first surface (8201) of the second passivation layer (82), respectively. N-type gallium nitride is filled in the second trench (8210) to form a first N-type gallium nitride region (61); a layer of N-type gallium nitride is deposited at the bottom of the third trench (8220) to form a second N-type gallium nitride region (62), the thickness of the second N-type gallium nitride region (62) being suitable for the third trench (8220) so that after the second N-type gallium nitride region (62) is formed, the first remaining trench (8220') is retained; The first remaining trench (8220') is filled with passivation material; A fourth trench (8230) is formed on the first surface (8201) of the second passivation layer (82); P-type gallium nitride is filled in the fourth trench (8230) to form a second P-type gallium nitride region (52); A fifth trench (8240) and a sixth trench (8250) are formed on the first surface (8201) of the second passivation layer (82), respectively. The source electrode (4) is formed in the fifth trench (8240); the drain electrode (3) is formed in the sixth trench (8250); A passivation layer is deposited on the first surface (8201) of the second passivation layer (82) to form a third passivation layer (83); A seventh trench (8310) is formed on the first surface (8301) of the third passivation layer (83); A gate (22) is formed in the seventh trench (8310).

5. A low-power, high-electron-mobility transistor, characterized in that, Includes at least one transistor unit, said at least one transistor unit comprising: Gate (22); Source (4); Drain (3); The second N-type gallium nitride region (62) of the contact source electrode (4); A second P-type gallium nitride region (52) is arranged between the second N-type gallium nitride region (62) and the gate (22); The first P-type gallium nitride region (51) of the contact drain (3); A first N-type gallium nitride region (61) is arranged between a first P-type gallium nitride region (51) and a gate (22); The first P-type gallium nitride region (51), the first N-type gallium nitride region (61), and the gate (22) constitute a normally open P-channel junction field-effect transistor; The second N-type gallium nitride region (62), the second P-type gallium nitride region (52), and the gate (22) constitute a normally off N-channel junction field-effect transistor.

6. A method for fabricating a low-power, high-electron-mobility transistor, characterized in that, include: A first trench (8110) is formed on the first surface (8101) of the first passivation layer (81). N-type gallium nitride is filled in the first trench (8110), and an N-type gallium nitride layer is deposited on the first surface (8101) of the first passivation layer (81) to form a second N-type gallium nitride region (62). A passivation layer is deposited on the first surface of the second N-type gallium nitride region (62) to form a second passivation layer (82). A second trench (8210) and a third trench (8220) are formed on the first surface (8201) of the second passivation layer (82), respectively. P-type gallium nitride is filled in the second trench (8210) to form a second P-type gallium nitride region (52); a layer of P-type gallium nitride is deposited at the bottom of the third trench (8220) to form a first P-type gallium nitride region (51), the thickness of the first P-type gallium nitride region (51) being suitable for the third trench (8220), so that after the first P-type gallium nitride region (51) is formed, the first remaining trench (8220') is retained; The first remaining trench (8220') is filled with passivation material; A fourth trench (8230) is formed on the first surface (8201) of the second passivation layer (82); N-type gallium nitride is filled in the fourth trench (8230) to form the first N-type gallium nitride region (61). A fifth trench (8240) and a sixth trench (8250) are formed on the first surface (8201) of the second passivation layer (82), respectively. The source electrode (4) is formed in the fifth trench (8240); the drain electrode (3) is formed in the sixth trench (8250); A passivation layer is deposited on the first surface (8201) of the second passivation layer (82) to form a third passivation layer (83); A seventh trench (8310) is formed on the first surface (8301) of the third passivation layer (83); A gate (22) is formed in the seventh trench (8310).

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