SOI MOS devices and their fabrication methods

Abstract

The present application provides a kind of SOI MOS device and its manufacturing method, the device includes: SOI substrate;Gate structure on SOI substrate;Lightly doped region in SOI substrate on both sides of gate structure;Source region and drain region in lightly doped region, the surface of drain region coincides with the surface of lightly doped region, the surface of source region is less than the surface of lightly doped region, and the surface of lightly doped region is exposed on the side of source region away from gate structure;And silicide at least on the surface of exposed lightly doped region.The present application forms ohmic contact by silicide and underlying lightly doped region, releases the hole accumulated in body region of SOI MOS device, thereby inhibits the floating body effect of SOI MOS device, improves device reliability;And the method is simple, will not increase the area of device, and can be compatible with conventional CMOS process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to an SOI MOS device and its fabrication method. Background Technology

[0002] The core component of semiconductor integrated circuits is the silicon-based MOSFET device. The rapid development of the integrated circuit industry is based on the continuous proportional reduction in the size of MOSFET devices. The continuous reduction in their feature size can not only greatly improve the integration density of integrated circuits, but also improve circuit performance. However, as the size of MOSFET devices shrinks to the submicron scale, it is increasingly approaching various physical limits, and the traditional MOSFET device structure is facing more and more challenges.

[0003] Silicon-on-insulator (SOI) structures hold promise as a replacement for traditional MOSFET devices in integrated circuit manufacturing. SOI structures not only significantly reduce parasitic capacitance but are also particularly well-suited for low-voltage / low-power applications. Furthermore, SOI devices exhibit excellent radiation immunity. Two types of devices have been developed using SOI structures: partially depleted SOI devices and fully depleted SOI devices. In partially depleted SOI devices, the silicon film in the channel region is sufficiently thick, and the width of the channel depletion region is smaller than the thickness of the silicon film. The advantage of this structure is that its design and operating principle are very similar to traditional bulk silicon MOSFET devices. However, its channel region may experience a substrate floating effect due to excessive hole accumulation, which can negatively impact device performance.

[0004] To address the floating body effect of partially depleted SOI MOS, a body contact method is typically used to connect the body region to a fixed potential (e.g., source or ground). Figure 1a This is a top view of the contact between a traditional T-shaped grid structure. Figure 1b This is a cross-sectional view of the contact of a traditional T-shaped grid structure. Please refer to it. Figure 1a and Figure 1b As shown, the P+ body contact formed at one end of the T-gate is connected to the P-type body region below the T-gate. When the MOS device is working, the carriers accumulated in the P-type body region are discharged through the P+ body contact, thereby reducing the potential of the P-type body region.

[0005] However, the negative effects include increased process complexity, parasitic effects, reduced electrical performance, and increased device area. Summary of the Invention

[0006] The purpose of this invention is to provide an SOI MOS device and its fabrication method, which has a simple fabrication process, does not increase the device area, and can reduce the floating body effect of the device.

[0007] To address the aforementioned technical problems, according to a first aspect of the present invention, an SOI MOS device is provided, comprising:

[0008] SOI substrate;

[0009] Gate structure located on the SOI substrate;

[0010] Lightly doped regions located in the SOI substrate on both sides of the gate structure;

[0011] The source and drain regions are located in the lightly doped regions on both sides of the gate structure. The surface of the drain region coincides with the surface of the lightly doped region. The surface of the source region is smaller than the surface of the lightly doped region, and the source region is close to the gate structure. A portion of the surface of the lightly doped region is exposed on the side of the source region away from the gate structure.

[0012] At least the silicide located on the surface of the exposed lightly doped region.

[0013] Optionally, the drain region includes a first drain region and a second drain region, wherein the first drain region is located in the lightly doped region on the side closer to the gate structure, and the second drain region is located in the lightly doped region on the side farther away from the gate structure.

[0014] Optionally, the doping depth of the source region, the first drain region, and the second drain region is all less than the doping depth of the lightly doped region.

[0015] Optionally, an isolation structure is formed on the SOI substrate, and the gate structure, the lightly doped region, the source region, and the drain region are all located between adjacent isolation structures; the lightly doped region is in contact with the isolation structure, and the bottom of the lightly doped region is in contact with the buried oxide layer in the SOI substrate.

[0016] To solve the above-mentioned technical problems, according to a second aspect of the present invention, a method for fabricating an SOI MOS device is provided, comprising:

[0017] An SOI substrate is provided, and a gate structure is formed on the SOI substrate;

[0018] Lightly doped regions are formed in the SOI substrates on both sides of the gate structure. Source and drain regions are formed in the SOI substrates on both sides of the gate structure. The source and drain regions are located within the lightly doped regions, and the surface of the drain region coincides with the surface of the lightly doped region. The surface of the source region is smaller than the surface of the lightly doped region, and the source region is close to the gate structure. A portion of the surface of the lightly doped region is exposed on the side of the source region away from the gate structure.

[0019] At least on the surface of the exposed lightly doped region, silicide is formed.

[0020] Optionally, the method for forming lightly doped regions in the SOI substrate on both sides of the gate structure includes: performing a first ion implantation to form lightly doped regions in the SOI substrate on both sides of the gate structure.

[0021] Optionally, the method of forming source and drain regions in the SOI substrate on both sides of the gate structure includes: performing a second ion implantation to form the source region and the first drain region in the lightly doped region on both sides of the gate structure, wherein the source region and the first drain region are close to the gate structure, so that the lightly doped region exposes a portion of its surface on the side away from the gate structure.

[0022] Optionally, the method for forming the source and drain regions further includes: performing a third ion implantation to form a second drain region in the lightly doped region on one side of the gate structure, wherein the first drain region and the second drain region together constitute the drain region.

[0023] Optionally, the doping depth of the source region, the first drain region, and the second drain region is all less than the doping depth of the lightly doped region.

[0024] Optionally, after providing the SOI substrate and before forming the gate structure, the fabrication method further includes: forming an isolation structure, wherein the gate structure, the lightly doped region, and the source region and the drain region are all located between adjacent isolation structures;

[0025] The lightly doped region is in contact with the isolation structure, and the bottom of the lightly doped region is in contact with the buried oxide layer in the SOI substrate.

[0026] Optionally, methods for forming silicide at least on the surface of the exposed lightly doped regions include:

[0027] A metal layer is formed at least on the surface of the exposed lightly doped region;

[0028] The silicide is formed by heat treatment.

[0029] In summary, the SOI MOS device and its fabrication method provided by this invention firstly provide an SOI substrate, on which a gate structure is formed. Then, lightly doped regions are formed in the SOI substrate on both sides of the gate structure. Source and drain regions are formed in the SOI substrate on both sides of the gate structure, located within the lightly doped regions. The surface of the drain region coincides with the surface of the lightly doped region, and the surface of the source region is smaller than the surface of the lightly doped region. The source region is close to the gate structure, and a portion of the surface of the lightly doped region is exposed on the side of the source region away from the gate structure. Then, silicide is formed at least on the exposed surface of the lightly doped region. This invention forms an ohmic contact between the silicide and the underlying lightly doped region, releasing holes accumulated in the body region of the SOI MOS device, thereby suppressing the floating body effect of the SOI MOS device and improving device reliability. Furthermore, the fabrication method of the SOI MOS device provided by this invention is simple, does not increase the device area, and is compatible with conventional CMOS processes.

[0030] Furthermore, the lightly doped regions are located within the SOI substrate on both sides of the gate structure. The side of the lightly doped region away from the gate structure is in contact with the isolation structure. The bottom of the lightly doped region is in contact with the buried oxide layer in the SOI substrate. The lightly doped region forms a halo-like region at the bottom of the SOI MOS device, which can prevent punch-through of small-sized devices and thus improve device performance. Attached Figure Description

[0031] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0032] Figure 1a This is a top view of the contact of a traditional T-shaped grid structure.

[0033] Figure 1b This is a cross-sectional view of the contact of a traditional T-shaped grid structure.

[0034] Figure 2 This is a flowchart of a method for fabricating an SOI MOS device according to an embodiment of the present invention.

[0035] Figure 3 This is a schematic diagram of a structure for forming a gate structure according to an embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram of the structure for forming a lightly doped region according to an embodiment of the present invention.

[0037] Figure 5 This is a schematic diagram of the structure for forming a source region and a first drain region according to an embodiment of the present invention.

[0038] Figure 6 This is a schematic diagram of the structure for forming the second leak region provided in an embodiment of the present invention.

[0039] Figure 7 This is a schematic diagram of the structure for forming silicides provided in an embodiment of the present invention.

[0040] In the attached image:

[0041] 10 - SOI substrate; 11 - Bottom silicon layer; 12 - Buried oxide layer; 13 - Top silicon layer; 14 - Isolation structure; 15 - Body region; 20 - Gate structure; 21 - Gate; 22 - Gate oxide layer; 23 - Sidewall; 31 - Lightly doped region; 32 - Source region; 33 - Drain region; 331 - First drain region; 332 - Second drain region; 41 - Patterned first mask; 42 - Patterned second mask; 43 - Patterned third mask; 50 - Silicate. Detailed Implementation

[0042] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0043] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0044] The core idea of ​​this invention is to provide an SOI MOS device and its fabrication method, which has a simple fabrication process, does not increase the device area, and can reduce the floating body effect of the device.

[0045] The method for fabricating the SOI MOS device includes: providing an SOI substrate; forming a gate structure on the SOI substrate; forming lightly doped regions in the SOI substrate on both sides of the gate structure; forming a source region and a drain region in the SOI substrate on both sides of the gate structure, wherein the source region and the drain region are located within the lightly doped regions, and the surface of the drain region coincides with the surface of the lightly doped region, the surface of the source region is smaller than the surface of the lightly doped region, exposing a portion of the surface of the lightly doped region on the side of the source region away from the gate structure; and forming silicide at least on the surface of the exposed lightly doped region.

[0046] The SOI MOS device includes: an SOI substrate; a gate structure located on the SOI substrate; lightly doped regions located on both sides of the gate structure within the SOI substrate; a source region and a drain region located on both sides of the gate structure within the lightly doped regions, wherein the surface of the drain region coincides with the surface of the lightly doped region, the surface of the source region is smaller than the surface of the lightly doped region, and the source region is close to the gate structure, exposing a portion of the surface of the lightly doped region on the side of the source region away from the gate structure; and silicide located at least on the surface of the exposed lightly doped region.

[0047] This invention forms an ohmic contact between silicide and the underlying lightly doped region, releasing holes accumulated in the body region of the SOI MOS device, thereby suppressing the floating body effect of the SOI MOS device and improving the reliability of the device. Furthermore, the fabrication method of the SOI MOS device provided by this invention is simple, does not increase the device area, and is compatible with conventional CMOS processes.

[0048] Figure 2 This is a flowchart of a method for fabricating an SOI MOS device according to an embodiment of the present invention. Figure 2 As shown, the fabrication method of the SOI MOS device includes the following steps:

[0049] Step S1: Provide an SOI substrate and form a gate structure on the SOI substrate;

[0050] Step S2: A lightly doped region is formed in the SOI substrate on both sides of the gate structure. A source region and a drain region are formed in the SOI substrate on both sides of the gate structure. The source region and the drain region are located in the lightly doped region. The surface of the drain region coincides with the surface of the lightly doped region. The surface of the source region is smaller than the surface of the lightly doped region. A portion of the surface of the lightly doped region is exposed on the side of the source region away from the gate structure.

[0051] Step S3: Form silicide at least on the surface of the exposed lightly doped region.

[0052] Figures 3 to 7 This is a schematic diagram illustrating the steps of a method for fabricating an SOI MOS device according to an embodiment of the present invention. Next, we will combine... Figure 2 and Figures 3 to 7 The fabrication method of the SOI MOS device provided by this invention will be described in detail.

[0053] In step S1, please refer to Figure 3 As shown, an SOI substrate 10 is provided, on which a gate structure 20 is formed.

[0054] In this embodiment, the SOI substrate 10 includes a bottom silicon layer 11, a buried oxide layer 12 on the bottom silicon layer 11, and a top silicon layer 13 on the buried oxide layer 12. The bottom silicon layer 11 and the top silicon layer 13 are made of monocrystalline silicon. In other embodiments, the bottom silicon layer 11 and the top silicon layer 13 may also be made of monocrystalline germanium or monocrystalline germanium-silicon, group III-V compound, monocrystalline silicon carbide, or other materials. The buried oxide layer 12 is made of silicon oxide. In other embodiments, the buried oxide layer 12 may also be other dielectric layers known to those skilled in the art.

[0055] There are several methods for fabricating the SOI substrate 10. For example, the SOI substrate 10 can be fabricated using the Separation by Implanted Oxygen (SIMOX) technique. The main steps of fabricating the SOI substrate 10 using the SIMOX technique include: providing a single-crystal silicon wafer, implanting oxygen ions into the single-crystal silicon wafer, and annealing at high temperature to form an oxide layer within the single-crystal silicon wafer. This oxide layer separates the original single-crystal silicon wafer into two parts: a bottom silicon layer and a top silicon layer. Alternatively, the SOI substrate 10 formed using the bonding SOI technique will have better quality. The main steps of forming the SOI substrate 10 using the bonding SOI technique include: tightly bonding the surfaces of a first single-crystal silicon wafer and a second single-crystal silicon wafer together, wherein the surface of the first or second single-crystal silicon wafer has an oxide layer formed by oxidation or other methods; annealing the surface to enhance the bonding interface; and then polishing or etching the non-bonded surface of the second single-crystal silicon wafer to leave a thinner top silicon layer on the oxide layer. In addition, other known techniques such as smart cut can be used. Alternatively, trenches and voids can be formed within the single-crystal silicon wafer and filled with an oxide layer to separate the single-crystal silicon wafer into a bottom silicon layer and a top silicon layer. The fabrication method of the SOI substrate 10 can be determined according to the needs of the actual product and the process conditions; this invention does not limit this method.

[0056] The process further includes forming an isolation structure 14 within the SOI substrate 10. This isolation structure 14 serves to isolate the subsequently formed SOI MOS device from other devices. The isolation structure 14 is in contact with the buried oxide layer 12. The subsequently formed gate structure, lightly doped region, and source and drain regions are located between adjacent isolation structures 14.

[0057] Next, a gate structure 20 is formed on the SOI substrate 10. The gate structure 20 includes a gate oxide layer 22 on the SOI substrate 10 and a gate 21 on the gate oxide layer 22. Sidewalls 23 are then formed on both sides of the gate structure 20. In this embodiment, before forming the gate structure 20, ion implantation may be performed on the SOI substrate 10 to form a body region 15. In this embodiment, the body region 15 is a P-type body region.

[0058] In step S2, please refer to Figures 4 to 6 As shown, a lightly doped region 31 is formed in the SOI substrate 10 on both sides of the gate structure 20. A source region 32 and a drain region 33 are formed in the SOI substrate 10 on both sides of the gate structure 20. The source region 32 and the drain region 33 are located in the lightly doped region 31, and the surface of the drain region 33 coincides with the surface of the lightly doped region 31. The surface of the source region 32 is smaller than the surface of the lightly doped region 31, and the source region 32 is close to the gate structure 20. On the side of the source region 32 away from the gate structure 20, a portion of the surface of the lightly doped region 31 is exposed.

[0059] Please refer to Figure 4 As shown, a first ion implantation is performed to form lightly doped regions 31 in the SOI substrate 10 on both sides of the gate structure 20. For example, a patterned first mask 41 is first formed, exposing the predetermined ion implantation area. Then, using the patterned first mask 41 as a mask, ion implantation is performed on the SOI substrate 10 to form the lightly doped regions 31 on both sides of the gate structure 20.

[0060] In this embodiment, the side of the lightly doped region 31 away from the gate structure 20 is in contact with the isolation structure 14, and the bottom of the lightly doped region 31 is in contact with the buried oxide layer 12 in the SOI substrate 10. The lightly doped region 31 forms a halo-like region at the bottom of the SOI MOS device, which can prevent punch-through of small-sized devices, thereby improving device performance.

[0061] In other embodiments, the side of the lightly doped region 31 away from the gate structure 20 may not be in contact with the isolation structure 14, and this invention is not limited thereto. When the lightly doped region 31 can be in contact with the isolation structure 14, its fabrication process is relatively simple and easy to control; that is, when the lightly doped region 31 is formed by the first ion implantation, the ion implantation is relatively easy to control.

[0062] Please refer to the following: Figure 5 As shown, a second ion implantation is performed to form the source region 32 and the first drain region 331 in the lightly doped regions 31 on both sides of the gate structure 20, respectively. The source region 32 and the first drain region 331 are close to the gate structure 20 so that the lightly doped region 31 exposes part of its surface on the side away from the gate structure 20.

[0063] The surfaces of both the source region 32 and the first drain region 331 are smaller than the surface of the lightly doped region 31. It is understood that the "surface" refers to the top surface of the doped region, i.e., the surface during the second ion implantation. For example, the surface of the source region 32 refers to the cross-section of the source region 32 on the plane containing the top surface of the SOI substrate 10; the surface of the first drain region 331 refers to the cross-section of the first drain region 331 on the plane containing the top surface of the SOI substrate 10; and the surface of the lightly doped region 31 refers to the cross-section of the lightly doped region 31 on the plane containing the top surface of the SOI substrate 10. Here, the "top surface" refers to the top surface of the SOI substrate 10 before the second ion implantation. If a material layer is formed on the SOI substrate 10 before the second ion implantation, the top surface refers to the top surface of the material layer; if no material layer is formed on the SOI substrate 10 before the second ion implantation, the top surface refers to the top surface of the SOI substrate 10 itself. In this embodiment, both the source region 32 and the first drain region 331 are located within the lightly doped region 31 on the side closer to the gate structure 20, thereby exposing a portion of the surface of the lightly doped region 31 on the side away from the gate structure 20. Figure 5 As shown.

[0064] For example, firstly, a patterned second mask 42 is formed, which exposes the area to be ion implanted. Then, using the patterned second mask 42 as a mask, ion implantation is performed on the SOI substrate 10, and the source region 32 and the first drain region 331 are formed on both sides of the gate structure 20, respectively.

[0065] Next, please refer to Figure 6As shown, a third ion implantation is performed to form a second drain region 332 in the lightly doped region 31 on the side of the first drain region 331 away from the gate structure 20. The first drain region 331 and the second drain region 332 together constitute the drain region 33.

[0066] For example, firstly, a patterned third mask 43 is formed, which exposes the region to be ion implanted. Then, using the patterned third mask 43 as a mask, ion implantation is performed on the SOI substrate 10 to form a second drain region 332 in the lightly doped region 31.

[0067] The patterned third mask 43 exposes the area within the lightly doped region 31 where the first drain region 331 has not been formed. Ion implantation is performed on this area to form the second drain region 332. The first drain region 331 and the second drain region 332 together constitute the drain region 33, thereby making the surface of the drain region 33 coincide with the surface of the lightly doped region 31 to prevent the subsequently formed silicide from contacting the lightly doped region 31 on one side of the drain region 33.

[0068] However, no third ion implantation was performed on one side of the source region 32. On the side of the source region 32 away from the gate structure 20, part of the surface of the lightly doped region 31 was exposed, so that the silicide formed later came into contact with the lightly doped region 31 to form an ohmic contact. This allowed the holes accumulated in the body region 15 to be discharged from the silicide through the lightly doped region 31, that is, discharged from the source region 32 side.

[0069] The doping depths of the source region 32, the first drain region 331, and the second drain region 332 are all less than the doping depth of the lightly doped region 31. The lightly doped region 31 is P-type doped, and the source region 32 and the drain region 33 are N-type doped.

[0070] It should be noted that in this embodiment, the lightly doped region 31 is formed first, then the source region 32 and the first drain region 331 are formed, and finally the second drain region 332 is formed. In other embodiments, the lightly doped region 31 may be formed first, then the second drain region 332 may be formed, and finally the source region 32 and the first drain region 331 may be formed. Of course, other formation orders can also be used. The present invention does not limit the formation order of the lightly doped region 31, the source region 32, the first drain region 331, and the second drain region 332.

[0071] In step S3, please refer to Figure 7 As shown, silicide 50 is formed at least on the surface of the exposed lightly doped region 31.

[0072] For example, a metal material layer is first formed on the SOI substrate 10, the gate structure 20, and the sidewall 23. Then, the metal material layer is exposed and developed to form a metal layer, which is at least located on the surface of the lightly doped region 31 exposed in the above steps. In this embodiment, the metal layer is located on the surface of the exposed lightly doped region 31, a portion of the surface of the source region 32, and a portion of the surface of the drain region 33, but is not limited thereto. Subsequently, a heat treatment is performed to cause the metal in the metal layer to react with the silicon material in the lightly doped region 31, the source region 32, and the drain region 33 to form silicide 50.

[0073] In the method for fabricating an SOI MOS device provided by the present invention, an SOI substrate 10 is first provided, and a gate structure 20 is formed on the SOI substrate 10. Then, lightly doped regions 31 are formed within the SOI substrate 10 on both sides of the gate structure 20. A source region 32 and a drain region 33 are formed within the SOI substrate 10 on both sides of the gate structure 20. The source region 32 and the drain region 33 are located within the lightly doped region 31, and the surface of the drain region 33 coincides with the surface of the lightly doped region 31. The surface of the source region 32 is smaller than the surface of the lightly doped region 31, and the source region 32 is close to the gate structure 20. A portion of the surface of the lightly doped region 31 is exposed on the side of the source region 32 away from the gate structure 20. Then, a silicide 50 is formed at least on the exposed surface of the lightly doped region 31. The present invention forms an ohmic contact between the silicide 50 and the underlying lightly doped region 31, releasing holes accumulated in the body region 15 of the SOI MOS device, thereby suppressing the floating body effect of the SOI MOS device and improving the reliability of the device. Furthermore, the method for fabricating SOI MOS devices provided by this invention only requires forming a lightly doped region 31 before forming the source 32 and the drain 33, followed by forming a silicide 50. The silicide 50 and the lightly doped region 31 below form an ohmic contact to release holes. The method is simple, does not increase the area of ​​the device, and is compatible with conventional CMOS processes.

[0074] Accordingly, the present invention also provides an SOI MOS device, fabricated using the SOI MOS device fabrication method described above. Please refer to [link / reference]. Figure 7 As shown, the SOI MOS device includes:

[0075] SOI substrate 10;

[0076] Gate structure 20 located on the SOI substrate 10;

[0077] Lightly doped regions 31 located in the SOI substrate 10 on both sides of the gate structure 20;

[0078] The source region 32 and drain region 33 are located in the lightly doped regions 31 on both sides of the gate structure 20. The surface of the drain region 33 coincides with the surface of the lightly doped region 31. The surface of the source region 32 is smaller than the surface of the lightly doped region 31. The source region 32 is close to the gate structure 20, and a portion of the surface of the lightly doped region 31 is exposed on the side of the source region 32 away from the gate structure 20.

[0079] At least the silicide 50 located on the surface of the exposed lightly doped region 31.

[0080] The silicide 50 forms an ohmic contact with the lightly doped region 31 below it, thereby forming a channel to release holes accumulated in the body region 15 of the SOI MOS device. The holes are discharged from the silicide 50 through the lightly doped region 31, that is, discharged from the source region 32 side, thereby suppressing the floating body effect of the SOI MOS device and improving the reliability of the device.

[0081] In this embodiment, the drain region 33 includes a first drain region 331 and a second drain region 332. The first drain region 331 is located in the lightly doped region 31 on the side close to the gate structure 20, and the second drain region 332 is located in the lightly doped region 31 on the side away from the gate structure 20.

[0082] The doping depths of the source region 32, the first drain region 331, and the second drain region 332 are all less than the doping depth of the lightly doped region 31.

[0083] An isolation structure 14 is formed on the SOI substrate 10. The gate structure 20, the lightly doped region 31, and the source region 32 and drain region 33 are all located between adjacent isolation structures 14. The side of the lightly doped region 31 away from the gate structure 20 is in contact with the isolation structure 14, and the bottom of the lightly doped region 31 is in contact with the buried oxide layer 12 in the SOI substrate 10. The lightly doped region 31 forms a halo-like region at the bottom of the SOI MOS device, which can prevent punch-through of small-sized devices, thereby improving device performance.

[0084] In summary, the SOI MOS device and its fabrication method provided by this invention firstly provide an SOI substrate, on which a gate structure is formed. Then, lightly doped regions are formed in the SOI substrate on both sides of the gate structure. Source and drain regions are formed in the SOI substrate on both sides of the gate structure, located within the lightly doped regions. The surface of the drain region coincides with the surface of the lightly doped region, and the surface of the source region is smaller than the surface of the lightly doped region. A portion of the surface of the lightly doped region is exposed on the side of the source region away from the gate structure. Subsequently, silicide is formed at least on the exposed surface of the lightly doped region. This invention forms an ohmic contact between the silicide and the underlying lightly doped region, releasing holes accumulated in the body region of the SOI MOS device, thereby suppressing the floating body effect of the SOI MOS device and improving device reliability. Furthermore, the fabrication method of the SOI MOS device provided by this invention is simple, does not increase the device area, and is compatible with conventional CMOS processes.

[0085] Furthermore, the lightly doped regions are located within the SOI substrate on both sides of the gate structure. The side of the lightly doped region away from the gate structure is in contact with the isolation structure. The bottom of the lightly doped region is in contact with the buried oxide layer in the SOI substrate. The lightly doped region forms a halo-like region at the bottom of the SOI MOS device, which can prevent punch-through of small-sized devices and thus improve device performance.

[0086] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An SOI MOS device, characterized in that, include: SOI substrate; The bulk region located within the SOI substrate; Gate structure located on the SOI substrate; The lightly doped regions located in the SOI substrate on both sides of the gate structure form a halo-like region at the bottom of the SOI MOS device to prevent punch-through of small-sized devices; The source and drain regions are located in the lightly doped regions on both sides of the gate structure. The surface of the drain region coincides with the surface of the lightly doped region. The surface of the source region is smaller than the surface of the lightly doped region. The source region is close to the gate structure. On the side of the source region away from the gate structure, a portion of the surface of the lightly doped region is exposed. The doping depth of both the source and drain regions is smaller than the doping depth of the lightly doped region. as well as A silicide located on the surface of the source region and partially in contact with the source region, and partially in direct contact with the exposed surface of the lightly doped region, wherein the silicide and the lightly doped region directly form an ohmic contact. Holes accumulated in the body region are discharged from the silicide through the lightly doped region on one side of the source region.

2. The SOI MOS device according to claim 1, characterized in that, The drain region includes a first drain region and a second drain region. The first drain region is located in the lightly doped region on the side closer to the gate structure, and the second drain region is located in the lightly doped region on the side farther away from the gate structure.

3. The SOI MOS device according to claim 1, characterized in that, An isolation structure is formed on the SOI substrate, and the gate structure, the lightly doped region, the source region, and the drain region are all located between adjacent isolation structures; the lightly doped region is in contact with the isolation structure, and the bottom of the lightly doped region is in contact with the buried oxide layer in the SOI substrate.

4. A method for fabricating an SOI MOS device, characterized in that, include: An SOI substrate is provided, a body region is formed within the SOI substrate, and a gate structure is formed on the SOI substrate; Lightly doped regions are formed in the SOI substrate on both sides of the gate structure. The lightly doped regions form a halo-like region at the bottom of the SOI MOS device to prevent punch-through of small-sized devices. Source and drain regions are formed in the SOI substrate on both sides of the gate structure. The source and drain regions are located in the lightly doped regions, and the surface of the drain region coincides with the surface of the lightly doped region. The surface of the source region is smaller than the surface of the lightly doped region. A portion of the surface of the lightly doped region is exposed on the side of the source region away from the gate structure. The doping depth of the source and drain regions is smaller than the doping depth of the lightly doped region. as well as A silicide is formed, which is located on the surface of the source region and partially contacts the source region, and partially contacts the exposed surface of the lightly doped region. The silicide and the lightly doped region directly form an ohmic contact. Holes accumulated in the body region are discharged from the silicide through the lightly doped region on one side of the source region.

5. The method for fabricating an SOI MOS device according to claim 4, characterized in that, A method for forming lightly doped regions in the SOI substrate on both sides of the gate structure includes: performing a first ion implantation to form lightly doped regions in the SOI substrate on both sides of the gate structure.

6. The method for fabricating an SOI MOS device according to claim 4, characterized in that, The method of forming source and drain regions in the SOI substrate on both sides of the gate structure includes: performing a second ion implantation to form the source and first drain regions in the lightly doped regions on both sides of the gate structure, so that the lightly doped regions expose a portion of their surface on the side away from the gate structure.

7. The method for fabricating an SOI MOS device according to claim 6, characterized in that, The method for forming the source and drain regions further includes: performing a third ion implantation to form a second drain region in the lightly doped region on one side of the gate structure, wherein the first drain region and the second drain region together constitute the drain region.

8. The method for fabricating an SOI MOS device according to claim 4, characterized in that, After providing the SOI substrate and before forming the gate structure, the fabrication method further includes: forming an isolation structure, wherein the gate structure, the lightly doped region, and the source region and the drain region are all located between adjacent isolation structures; The lightly doped region is in contact with the isolation structure, and the bottom of the lightly doped region is in contact with the buried oxide layer in the SOI substrate.

9. The method for fabricating an SOI MOS device according to claim 4, characterized in that, Methods for forming silicides include: A metal layer is formed on the surface of the exposed lightly doped region and on a portion of the surface of the source region and the drain region; The silicide is formed by heat treatment.

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